GS4881

GS1881, GS4881, GS4981 Monolithic Video Sync Separators Features • • • • • • • • • • • noise tolerant odd/even flag, back porch and horizontal sync pulse fast recovery from impulse noise excellent temperature stability 0.5V to 4Vpp input signal amplitude with 5V supply well-controlled clamp discharge current and slicing level programmable horizontal scan rate (up to 130kHz) composite, vertical, back porch, odd/even (GS1881, GS4881), horizontal (GS4981) outputs predictable vertical output pulse width with default trigger for non-standard video signals Pb-free and Green 5V to 12V supply voltage range pin compatible with LM1881 sync separator Description The GS1881, GS4881 and GS4981 are general purpose sync separators for use in a wide variety of video applications. The devices extract the timing information from composite video signals with scan rates from 15 to 130kHz. The GS1881 is a drop-in replacement for the industry standard LM1881 with much improved performance. The device generates composite sync, vertical sync, back porch and odd/even field signals. The GS4881 is identical to the GS1881 but features a noise immune back porch pulse which maintains a constant H rate during the vertical interval. The GS4981 is identical to the GS4881, except that it provides horizontal sync in place of the odd/even output. All three devices feature a self-adjusting windowing circuit for noise immunity, which synchronizes to H rate. This windowing circuit determines the odd or even field in the GS1881 and GS4881, gates the back porch pulse in the GS4881 and GS4981, and generates the horizontal sync output in the GS4981. The devices feature an improved input stage which ensures that the input signal is sliced at a predictable point due to well-controlled input clamp discharge current and sync slicing level. A missing pulse detector enables the devices to recover quickly from impulse noise disturbances by temporarily increasing the clamp discharge current by roughly ten times. The input stage will operate with signals from 0.5 to 4Vp-p with a 5V supply. The GS1881, GS4881 and GS4981 also feature a predictable vertical output pulse width with a default trigger for non-standard video signals. All three are available in commercial and industrial temperature ranges and are packaged in both DIP and SOIC. Application Selection Chart Application Direct LM1881 Replacement with Improved Performance New Applications Substitution for LM1881 New Applications Requiring Horizontal Sync Output Choose Device: GS1881 GS4881 GS4981 GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 www.gennum.com 1 of 29 Proprietary & Confidential Revision History Version 5 Date November 2009 Changes and/or Modifications Updated to latest Gennum template and changed from document number 52023 to 6926. Added lead-free and green information. Revisions made. Revisions made. New document. 4 3 2 1 July 2004 – – March 1991 Contents Features.................................................................................................................................................................1 Application Selection Chart ...........................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................2 1. Pin Connections .............................................................................................................................................3 1.1 Pin Connections ................................................................................................................................3 2. Electrical Characteristics ............................................................................................................................4 2.1 GS1881 Electrical Characteristics ...............................................................................................4 2.2 GS4881 Electrical Characteristics ...............................................................................................5 2.3 GS4981 Electrical Characteristics ...............................................................................................6 2.4 Typical Performance Characteristics .........................................................................................8 3. Temperature Characteristics .................................................................................................................. 11 4. Circuit Description..................................................................................................................................... 14 4.1 Composite Video Input (Pin 2) and Composite Sync Output (Pin 1) ............................. 14 4.2 Back Porch Output (Pin 5) ........................................................................................................... 15 4.3 Vertical Sync Output (Pin 3) ....................................................................................................... 16 4.4 Odd/Even Field Output (Pin 7 GS1881, GS4881) ................................................................ 16 4.5 Horizontal Output (Pin 7 GS4981) ............................................................................................ 17 4.6 Block Diagrams .............................................................................................................................. 17 5. Application Notes....................................................................................................................................... 20 5.1 Choosing the Appropriate Input Capacitor to Optimize Slicing Level and Hum Rejection ....................................................................................................................................... 20 5.2 Filtering ............................................................................................................................................. 22 5.3 Deriving Odd/Even Using the GS4981 ................................................................................... 25 6. Ordering Information................................................................................................................................ 27 6.1 GS1881 Ordering Information .................................................................................................. 27 6.2 GS4881 Ordering Information .................................................................................................. 27 6.3 GS4981 Ordering Information .................................................................................................. 28 GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 2 of 29 Proprietary & Confidential 1. Pin Connections 1.1 Pin Connections GS1881, GS4881 COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GROUND 1 2 3 4 8 7 6 5 V GS4981 cc COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GROUND 1 2 3 4 8 7 6 5 V cc ODD/EVEN RSET BACK PORCH HORIZONTAL RSET BACK PORCH 8-PIN DIP 8-PIN SOIC 8-PIN DIP 8-PIN SOIC Figure 1-1: 8-Pin DIP, 8-Pin SOIC GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 3 of 29 Proprietary & Confidential 2. Electrical Characteristics 2.1 GS1881 Electrical Characteristics Table 2-1 shows the electrical characteristics of the GS1881 where conditions are VCC = 5V, RSET = 680kΩ, TA =25°C, unless otherwise shown. Table 2-1: GS1881 Electrical Characteristics Parameter Supply Voltage Supply Current Outputs at Logic 1 Conditions – VCC = 5V VCC = 12V Min 4.5 – – Typ 5 4.6 5.0 Max 13.2 30 6.5 Units V mA mA Video Input (Pin 2) (a) Signal Level (b) Clamp Current VCC = 5V Charge Discharge - normal Discharge - Nosync flag raised (c) Delay to raising of Nosync flag (d) Sync Tip Clamp Voltage Sync Slice Level RSET Pin Reference Voltage (Pin 6) Composite Sync Out (Pin 1) Delay from Video Back Porch Pulse Out (Pin 5) (a) Delay from Rising Edge of Sync (b) Pulse Width Vertical Sync Out (Pin 3) (a) Pulse Width (b) Default Starting Time Horizontal Scan Rate Logic Outputs (a) VOH Ι OH = 40μA VCC = 5V VCC = 12V Ι OH = 1.6mA VCC = 5V VCC = 12V 4.2 11.2 2.4 9.4 4.6 11.6 3.4 10.4 – – – – V V V V Serrations during vertical interval No serrations during vertical interval Modified RSET 197.7 48 15 197.7 65 – 197.7 82 130 μs μs kHz CL = 15p 400 2.0 500 2.5 650 3.2 ns μs Video input held high – Relative to sync tip clamp voltage See Note 1. See Note 2. CL = 15p 0.5 500 9 65 64 – 70 1.14 40 – 650 11 95 95 1.55 77 1.24 60 4 850 13 115 130 – 84 1.34 80 Vp-p μA μA μA μs V mV V ns GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 4 of 29 Proprietary & Confidential Table 2-1: GS1881 Electrical Characteristics (Continued) Parameter (b) VOL NOTES: 1. When placing the RSET resistor and the 0.1μF decoupling capacitor, careful attention should be made to ensure that they are as close as possible to Pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (Pins 1, 3, 5 and 7) to Pin 6. 2. Measured from slicing point of input falling edge to 50% point of composite sync falling edge. Conditions Ι OL = 1.6mA Min – Typ 0.3 Max 0.6 Units V 2.2 GS4881 Electrical Characteristics Table 2-2 shows the electrical characteristics of the GS4881 where conditions are VCC = 5V, RSET = 680kΩ, TA =25°C, unless otherwise shown. Table 2-2: GS4881 Electrical Characteristics Parameter Supply Voltage Supply Current Outputs at Logic 1 Conditions – VCC = 5V VCC = 12V Min 4.5 – – Typ 5 4.6 5.0 Max 13.2 30 6.5 Units V mA mA Video Input (Pin 2) (a) Signal Level (b) Clamp Current VCC = 5V Charge Discharge - normal Discharge - Nosync flag raised (c) Delay to raising of Nosync flag (d) Sync Tip Clamp Voltage Sync Slice Level RSET Pin Reference Voltage (Pin 6) Composite Sync Out (Pin 1) Delay from Video Back Porch Pulse Out (Pin 5) (a) Delay from Rising Edge of Sync (b) Pulse Width (c) Occurrence Rate Vertical Sync Out (Pin 3) (a) Pulse Width (b) Default Starting Time Serrations during vertical interval No serrations during vertical interval 197.7 48 197.7 65 197.7 82 μs μs CL = 15p 400 2.0 H 500 2.5 H 650 3.2 H ns μs – Video input held high – Relative to sync tip clamp voltage See Note 1. See Note 2. CL = 15p 0.5 500 9 65 64 – 70 1.14 40 – 650 11 95 95 1.55 77 1.24 60 4 850 13 115 130 – 84 1.34 80 Vp-p μA μA μA μs V mV V ns GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 5 of 29 Proprietary & Confidential Table 2-2: GS4881 Electrical Characteristics (Continued) Parameter Horizontal Scan Rate Logic Outputs (a) VOH Ι OH = 40μA VCC = 5V VCC = 12V Ι OH = 1.6mA (b) VOL NOTES: 1. When placing the RSET resistor and the 0.1μF decoupling capacitor, careful attention should be made to ensure that they are as close as possible to Pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (Pins 1, 3, 5 and 7) to Pin 6. 2. Measured from slicing point of input falling edge to 50% point of composite sync falling edge. Ι OL = 1.6mA VCC = 5V VCC = 12V 4.2 11.2 2.4 9.4 – 4.6 11.6 3.4 10.4 0.3 – – – – 0.6 V V V V V Conditions Modified RSET Min 15 Typ – Max 130 Units kHz 2.3 GS4981 Electrical Characteristics Table 2-2 shows the electrical characteristics of the GS4981 where conditions are VCC = 5V, RSET = 680kΩ, TA =25°C, unless otherwise shown. Table 2-3: GS4981 Electrical Characteristics Parameter Supply Voltage Supply Current Outputs at Logic 1 Conditions – VCC = 5V VCC = 12V Min 4.5 – – Typ 5 4.6 5.0 Max 13.2 30 6.5 Units V mA mA Video Input (Pin 2) (a) Signal Level (b) Clamp Current VCC = 5V Charge Discharge - normal Discharge - Nosync flag raised (c) Delay to raising of Nosync flag (d) Sync Tip Clamp Voltage Sync Slice Level RSET Pin Reference Voltage (Pin 6) Composite Sync Out (Pin 1) Delay from Video Back Porch Pulse Out (Pin 5) Video input held high – Relative to sync tip clamp voltage See Note 1. See Note 2. CL = 15p 0.5 500 9 65 64 – 70 1.14 40 – 650 11 95 95 1.55 77 1.24 60 4 850 13 115 130 – 84 1.34 80 Vp-p μA μA μA μs V mV V ns GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 6 of 29 Proprietary & Confidential Table 2-3: GS4981 Electrical Characteristics (Continued) Parameter (a) Delay from Rising Edge of Sync (b) Pulse Width (c) Occurrence Rate Vertical Sync Out (Pin 3) (a) Pulse Width (b) Default Starting Time Horizontal Sync Out (Pin 7) (a) Delay From Video (b) Pulse Width Horizontal Scan Rate Logic Outputs (a) VOH Ι OH = 40μA VCC = 5V VCC = 12V Ι OH = 1.6mA See Note 3. (b) VOL NOTES: 1. When placing the RSET resistor and the 0.1μF decoupling capacitor, careful attention should be made to ensure that they are as close as possible to Pin 6. Care should also be taken to avoid parasitic capacitive coupling from any output pin (Pins 1, 3, 5 and 7) to Pin 6. 2. Measured from slicing point of input falling edge to 50% point of composite sync falling edge. 3. Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 10kΩ pull-up to VCC. Ι OL = 1.6mA VCC = 5V 4.2 11.2 2.4 4.6 11.6 3.4 – – – V V V Modified RSET CL = 15p 90 5.0 15 190 7.0 – 290 9.0 130 ns μs kHz Serrations during vertical interval No serrations during vertical interval 197.7 48 197.7 65 197.7 82 μs μs CL = 15p Conditions Min 400 2.0 H Typ 500 2.5 H Max 650 3.2 H Units ns μs – VCC = 12V 9.4 – 10.4 0.3 – 0.6 V V GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 7 of 29 Proprietary & Confidential 2.4 Typical Performance Characteristics Figure 2-1 through Figure 2-6 show the typical performance characteristics for the GS1881, GS4881, and GS4981, where VS = 5V, TA =25°C, unless otherwise specified. 700 600 500 RSET (kΩ) 400 300 200 100 0 15 35 55 75 95 115 135 SCAN RATE (kHz) Figure 2-1: RSET vs Scan Rate 70 VERTICAL DEFAULT TIME (μs) 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 RSET (kΩ) Figure 2-2: Vertical Sync Default Starting Time vs RSET GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 8 of 29 Proprietary & Confidential 700 600 BACK PORCH DELAY (ns) 500 400 300 200 100 0 0 100 200 300 400 500 600 700 RSET (kΩ) Figure 2-3: Back Porch Delay vs RSET 3000 2500 BACK PORCH WIDTH (ns) 2000 1500 1000 500 0 0 100 200 300 400 500 600 700 RSET (kΩ) Figure 2-4: Back Porch Width vs RSET 8000 7000 HORIZONTAL WIDTH (μs) 6000 5000 4000 3000 2000 1000 0 0 100 200 300 400 500 600 700 RSET (kΩ ) Figure 2-5: Horizontal Width vs RSET GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 9 of 29 Proprietary & Confidential 110 100 NOSYNC DELAY TIME (μs) 90 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 RSET (kΩ) Figure 2-6: Nosync Delay Time vs RSET GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 10 of 29 Proprietary & Confidential 3. Temperature Characteristics Figure 3-1 through Figure 3-6 show the typical temperature characteristics for the GS1881, GS4881, and GS4981, where VS = 5V, RSET =680kΩ, unless otherwise specified. NOTE: Grey shading on Figure 3-1 through Figure 3-6 indicates commercial temperature range (0 to 70°C). 10 COMPOSITE SYNC DELAY VARIATION (ns) 8 6 4 2 0 -2 -4 -6 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 3-1: Composite Sync Delay Variation vs Temperature 850 CLAMPING CURRENT (μA) 740 650 550 450 350 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 3-2: Clamping Current vs Temperature GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 11 of 29 Proprietary & Confidential 30 BACK PORCH DELAY VARIATION (ns) 20 10 0 -10 -20 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 3-3: Back Porch Delay Variation vs Temperature 125 BACK PORCH WIDTH VARIATION (ns) 100 75 50 25 0 -25 -50 -75 100 -125 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 3-4: Back Porch Width Variation vs Temperature 25 HORIZONTAL DELAY VARIATION (ns) 20 15 10 5 0 -5 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 3-5: Horizontal Delay Variation vs Temperature GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 12 of 29 Proprietary & Confidential 600 HORIZONTAL WIDTH VARIATION (ns) 500 400 300 200 100 0 -100 -200 -300 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 3-6: Horizontal Width Variation vs Temperature GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 13 of 29 Proprietary & Confidential 4. Circuit Description The block diagrams for the GS1881, GS4881 and GS4981, are shown in Figure 4-5 through Figure 4-7, with timing diagrams for the devices shown in Figure 4-8. When stimulated by a composite input signal, the GS1881 and GS4881 sync separators output composite sync, vertical sync, back porch, and odd/even field information. The GS4981 substitutes the odd/even output of the GS4881 with a horizontal output. An external resistor on Pin 6 is used to define internal currents allowing the devices to accommodate horizontal scan rates from 15kHz to 130kHz. 4.1 Composite Video Input (Pin 2) and Composite Sync Output (Pin 1) Composite video is AC coupled via an external coupling capacitor to Pin 2. The device clamps the sync tip of the input video to 1.5V (Vclamp) and then slices at 77mV above the clamp voltage (Vslice). The resultant signal, provided at Pin 1, is a reproduction of the input signal with the active video portion removed. As Vclamp and Vslice are supply and input signal independent, for 0.5Vp-p signals (sync height of 143mV) slicing will occur at just above the 50% point and for 2Vp-p signals (sync height of 572mV) slicing will occur at approximately 13% of sync height. The video signal path and composite sync slicing circuitry have been optimized and compensated to achieve a low propagation delay that is stable over temperature. The typical delay is 60ns with less than 3ns drift over the commercial temperature range. The typical input clamp discharge current is 11μA. This current is optimal under normal operating circumstances but needs to be increased when the clamp is trying to recover from negative going impulse noise. The device improves the recovery time by raising a NOSYNC flag when there has not been a sync pulse for approximately 1 1/2 horizontal lines. When this flag is raised the discharge current is increased by 85μA so that the recovery time is sped up by nearly 10 times. Figure 4-1 shows a comparison between the recovery times with and without the increased discharge current. GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 14 of 29 Proprietary & Confidential VIDEO INPUT IMPULSE NOISE COMPOSITE SYNC RECOVERY TIME without INCREASED DISCHARGE CURRENT (LM1881) RECOVERY TIME T1 COMPOSITE SYNC RECOVERY TIME with INCREASED DISCHARGE CURRENT (GS1881, GS4881, GS4981) RECOVERY TIME T1 / 10 Figure 4-1: Impulse Noise: Recovery Time Comparison 4.2 Back Porch Output (Pin 5) In an NTSC composite video signal, horizontal sync pulses are followed by the back porch interval. The device generates a negative going pulse on Pin 5 during this time. It is delayed typically 500ns from the rising edge of sync and has a typical width of 2.5μs. Both of these times are set by the external RSET resistor. During the pre-equalizing, vertical sync, and post-equalizing periods, composite sync doubles in frequency. The GS4881 and GS4981 maintain the back porch output at the horizontal rate due to Back Porch Enable (BPEN), generated by the internal windowing circuit, which forces back porch to be asserted at the horizontal rate. This gating circuit is also the reason for the excellent impulse noise immunity of the back porch output as shown in Figure 4-2. Video Input Impulse Noise Back Porch Output GS4881 GS4981 Figure 4-2: Back Porch Noise Immunity GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 15 of 29 Proprietary & Confidential The GS1881 does not gate the Back Porch which allows for total pin compatibility with the LM1881. 4.3 Vertical Sync Output (Pin 3) The vertical sync interval is detected by integrating the composite sync pulses. The first broad vertical sync pulse causes an internal capacitor to charge past a fixed threshold and raises an internal vertical flag. Once the vertical flag is raised, the positive edge of the next serration clocks out the vertical output. When the vertical sync interval ends, the first post equalizing pulse is unable to charge the capacitor sufficiently, causing the internal vertical flag to go high. The rising edge of the second post-equalizing pulse then clocks out the high flag to end the vertical sync pulse. The vertical output is clocked in and out and therefore is a fixed width of 197.7μs (3H + 4.7μs + 2.3μs). In the case of a non-standard vertical interval that has no serrations, a second internal capacitor is charged and clocks the vertical pulse out after typically 65μs. In this case the end of the vertical pulse will still be the rising edge of the second post-equalizing pulse. As the vertical detector is designed as a true integrator, it provides improved noise immunity. 4.4 Odd/Even Field Output (Pin 7 GS1881, GS4881) NTSC PAL and SECAM composite video standards are interlaced video schemes and therefore have odd and even fields. For odd fields the first broad vertical sync pulse is coincident with the start of horizontal, while for even fields the first broad vertical sync pulse starts in the middle of a horizontal line. Therefore by comparing the vertical sync with an internally generated horizontal sync the odd/even field information is determined. This output is clocked out by the falling edge of vertical sync. The odd/even output is low during even fields and high during odd fields. This method of detecting odd and even fields is very noise tolerant. Noise during the pre-equalizing pulses does not affect the output since the field decision is made at the beginning of the vertical interval. This noise immunity is displayed in Figure 4-3 in which an extra pre-equalizing pulse has been added to the video input with no negative effect on the odd/even field information. Video Input Impulse Noise Even Odd/Even Output Odd Figure 4-3: Odd/Even Output GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 16 of 29 Proprietary & Confidential 4.5 Horizontal Output (Pin 7 GS4981) As mentioned above, the odd/even field output of the GS1881 and GS4881 is generated by comparing vertical sync with an internal horizontal sync signal. This horizontal sync signal is a true horizontal signal (i.e. maintained during the vertical interval) and is outputted on Pin 7 for the GS4981. A delay of 190ns from the video input and a width of 6.5μs are typically characteristics for this signal. The windowing circuit which generates horizontal provides excellent impulse noise immunity as shown in Figure 4-4. This output buffer is an open collector stage with an internal 10kΩ pull up resistor. Video Input Impulse Noise Horizontal Output Figure 4-4: Horizontal Output 4.6 Block Diagrams C SYNC VIDEO INPUT (Pin 2) V SLICE COMPOSITE SYNC OUTPUT (Pin 1) + HORIZONTAL + V CLAMP + WINDOWING CIRCUIT D Q D Q ODD / EVEN OUTPUT (Pin 7) G Q CLK Q 11μ 85μ NOSYNC VCC (Pin 8) D VOLTAGE REGULATOR Q VERTICAL DETECTOR VERTICAL SYNC OUTPUT (PIN 3) CLK Q 1.2V R_SET (Pin 6) TIMING CURRENTS BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR Figure 4-5: GS1881 Block Diagram GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 17 of 29 Proprietary & Confidential C SYNC VIDEO INPUT (Pin 2) V SLICE COMPOSITE SYNC OUTPUT (Pin 1) + HORIZONTAL + V CLAMP + WINDOWING CIRCUIT D Q D Q ODD / EVEN OUTPUT (Pin 7) G Q CLK Q 11μ 85μ NOSYNC B PEN VCC (Pin 8) VOLTAGE REGULATOR D VERTICAL DETECTOR Q VERTICAL SYNC OUTPUT (PIN 3) CLK Q 1.2V R_SET (Pin 6) TIMING CURRENTS BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR Figure 4-6: GS4881 Block Diagram C SYNC VIDEO INPUT (Pin 2) V1 COMPOSITE SYNC OUTPUT (Pin 1) + 10k + V2 + WINDOWING CIRCUIT HORIZONTAL OUTPUT (Pin 7) 11μ 85μ NOSYNC B PEN VCC (Pin 8) VOLTAGE REGULATOR D Q VERTICAL DETECTOR VERTICAL SYNC OUTPUT (PIN 3) CLK Q 1.2V R_SET (Pin 6) TIMING CURRENTS BACK PORCH OUTPUT (Pin 5) BACK PORCH DETECTOR Figure 4-7: GS4981 Block Diagram GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 18 of 29 Proprietary & Confidential 525 1 2 3 4 5 6 7 8 COMPOSITE VIDEO INPUT COMPOSITE SYNC OUTPUT GS1881, GS4881, GS4981 BACK PORCH OUTPUT GS4881, GS4981 BACK PORCH OUTPUT GS1881 HORIZONTAL OUTPUT GS4981 VERTICAL SYNC OUTPUT GS1881, GS4881, GS4981 ODD/EVEN OUTPUT GS1881, GS4881 600ns 2.5μs COMPOSITE VIDEO INPUT BACK PORCH OUTPUT 500ns 2.5μs Figure 4-8: GS1881, GS4881, GS4981 Video Sync Separator Timing Diagram GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 19 of 29 Proprietary & Confidential 5. Application Notes 5.1 Choosing the Appropriate Input Capacitor to Optimize Slicing Level and Hum Rejection The video designer can adjust the slicing level by choosing the value of the input coupling capacitor. The relationship between slicing level and input coupling capacitor is described by the following equation: ∆VSLICE = where: IDIS CC ∆T = VDROOP IDIS = clamp discharge current = 11 μA ∆T = TLINE - TSYNC = (63.5 μs - 4.7 μs) CC = input coupling capacitor Figure 5-1 is a graphical representation of this equation and Figure 5-2 and Figure 5-3 show the input video waveforms for 0.1μF and 0.01μF input capacitors respectively. The advantage in choosing a smaller input coupling capacitor, is increased hum rejection as the following analyses illustrates. 137 127 SLICING LEVEL (mV) 117 107 97 87 77 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 INPUT COUPLING CAPACITOR (μF) Figure 5-1: Slicing Level vs Input Coupling Capacitor GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 20 of 29 Proprietary & Confidential CH1 CH2 VIDEO 2 0.1μF 75W 8 6 4 680k 0.1μ Figure 5-2: Test Circuit 1 and Video Waveforms for 0.1μF CH1 CH2 VIDEO 2 0.01μF 75W 8 6 4 680k 0.1μ Figure 5-3: Test Circuit 2 and Video Waveforms for 0.01μF The interfering hum component is defined by: vHUM(t) = V Pcos(2πƒ HUMt) where: VP = Peak voltage of AC hum ƒHUM = Frequency of hum (50Hz or 60Hz) The maximum rate of change of this hum signal occurs at the zero crossing points and is: dv HUM dt t= π 3π , 22 = ± V P2πƒ HUM Since the horizontal scan period is much faster than the period of the interference (63.5ms ΔVHUM. VDROOP is increased by decreasing the input coupling capacitor value. Therefore the video designer can increase hum rejection by decreasing the value of this capacitor. The following is a numerical example: choosing Cc ... VDROOP = = 0.022μF 11 (63.5μ - 4.7μ) = 29.4mV 0.022 the maximum amount of 60 Hz hum that could be rejected would be when: ∆VDROOP = ∆VHUM = VP 2πƒHUM TLINE ... VP = ∆VDROOP 2πƒ HUMTLINE = 29.4mV 2 π(60) (63.5μ) = 1.23V PEAK HUM verifying that there is enough clamping current ∆Vt = 29.4mV + 29.4 mV = 58.8mV ... i = 0.022μ ( 58.8mV ) = 275μA 4.7μ which is less than 650μA. 5.2 Filtering In order to keep the input to output delay small and temperature stable, no chrominance filtering is done within the device. External filtering may be necessary if the input signal contains large chrominance components (less than 77mV from sync tip) or has significant amounts of high frequency noise. This filter can be a simple low pass RC network constructed by a resistance (RS) in series with the source and a capacitor (Cƒ) to ground. A single pole low pass filter having a corner frequency of approximately 500kHz will provide ample bandwidth for passing sync pulses with almost 18dB attenuation at 3.58MHz. Care should be taken in choosing the value of the series resistor in the filter since the source resistance seen by the sync separator affects its performance. See Figure 5-4. GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 22 of 29 Proprietary & Confidential As the source resistance rises, the video input sync tip starts to be clipped due to the clamping current during the sync. This clamping current is relatively large due to the non-symmetric duty cycle of video. To a good approximation the amount of sync clamp current can be calculated as follows: ( I CLAMP ICLAMP AVG ) (TSYNC) = (I DIS) (TLINE - TSYNC) (4.7 μs) = (11μA) (63.5μs - 4.7μs) = 137.6μA AVG AVG ... I CLAMP This clamp current flows in the source resistance causing a voltage drop equal to: VCLIP = ( I CLAMP AVG ) (RS) = (137.6μ) (R S) I CLAMP RS 75Ω VCLIP + CC Cƒ 4 2 6 680k 0.1μ 8 VIDEO INPUT Figure 5-4: Simple Chrominance Filtering Figure 5-5 shows the amount of sync clipping for a 560Ω source resistor. A graph of VCLIP versus RS is shown in Figure 5-6, and Figure 5-7 shows the corresponding capacitor value for a particular series resistor to provide a corner frequency of 500kHz. In applications where signal levels are small the amount of attenuation should be minimized. It follows from Figure 5-6 and Figure 5-7 that in order to minimize attenuation a small series resistor and a larger capacitor to ground should be chosen. This however, increases the capacitive loading of the signal source. CH1 VIDEO CH2 8 2 560W 75W 0.1μF 6 4 680k 0.1μ Figure 5-5: Test Circuit 3 and Sync Clipping for a 650Ω Source Resistor GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 23 of 29 Proprietary & Confidential 100 90 80 70 VCLIP (mV) 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 SERIES RESISTOR (Ω) Figure 5-6: VCLIP vs Series Resistor 10 9 8 7 Cƒ (nF) 6 5 4 3 2 1 0 0 100 200 300 400 500 600 700 SERIES RESISTOR (Ω) Figure 5-7: Cƒ vs Series Resistor Another way to minimize the amount of attenuation is to control the source resistance seen by the sync separator by using a PNP emitter follower (Figure 5-8). A PNP emitter follower works well to drive the sync separator, and does not require much DC current because the transistor provides the current when it is needed during sync. Figure 5-9 is a typical application circuit that minimizes sync tip clipping. VCC 5.6k VIDEO INPUT FILTER 75Ω CC 8 2 6 680k -5V 0.1μ 4 Figure 5-8: PNP Emitter Follower Buffer GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 24 of 29 Proprietary & Confidential VCC 5.6k VIDEO INPUT 8 5.6k 2 CC 4 56p -5V 6 680k 0.1μ 75Ω Figure 5-9: Typical NTSC Application Circuit 5.3 Deriving Odd/Even Using the GS4981 Odd/even field information can be derived using the vertical and horizontal outputs from the GS4981 along with an external positive edge D flip/flop. The horizontal output is used as the D input and the vertical output as the clock, as shown in Figure 5-10. At the start of an odd field the vertical output ends in the middle of the horizontal line and a high will be latched. At the start of an even field, the vertical output ends near the beginning of the horizontal line and since the horizontal output is low, a low will be latched. This timing sequence is shown in Figure 5-11. COMPOSITE SYNC OUTPUT 0.1μF COMPOSITE VIDEO INPUT VERTICAL SYNC OUTPUT 1 2 3 4 GS4981 8 7 6 0.1μF 5 VCC 5 - 12V HORIZONTAL 680kW R SET BACK PORCH OUTPUT D FLIP/FLOP D Q Q ODD/EVEN OUTPUT Figure 5-10: Derivation of Odd/Even with GS4981 GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 V CLK 25 of 29 Proprietary & Confidential START OF ODD FIELD 525 1 2 3 4 5 6 7 8 COMPOSITE VIDEO INPUT HORIZONTAL OUTPUT GS4981 VERTICAL SYNC OUTPUT GS4981 ODD/EVEN OUTPUT START OF EVEN FIELD 263 264 265 266 267 268 269 270 COMPOSITE VIDEO INPUT HORIZONTAL GS4981 VERTICAL SYNC OUTPUT GS4981 ODD/EVEN OUTPUT Figure 5-11: Timing Diagram GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 26 of 29 Proprietary & Confidential 6. Ordering Information 6.1 GS1881 Ordering Information Table 6-1: GS1881 Ordering Information Part Number Package Type Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C -25°C to 85°C -25°C to 85°C -25°C to 85°C 0°C to 70°C 0°C to 70°C -25°C to 85°C Pb-Free and Green GS1881 - CDA GS1881 - CKA GS1881 - CTA GS1881 - IDA GS1881 - IKA GS1881 - ITA GS1881 - CKAE3 GS1881 - CTAE3 GS1881 - IKAE3 8-Pin PDIP 8-Pin SOIC 8-Pin TAPE 8-Pin PDIP 8-Pin SOIC 8-Pin TAPE 8-Pin SOIC 8-Pin TAPE 8-Pin SOIC No No No No No No Yes Yes Yes 6.2 GS4881 Ordering Information Table 6-2: GS4881 Ordering Information Part Number Package Type Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C -25°C to 85°C -25°C to 85°C -25°C to 85°C 0°C to 70°C 0°C to 70°C Pb-Free and Green GS4881 - CDA GS4881 - CKA GS4881 - CTA GS4881 - IDA GS4881 - IKA GS4881 - ITA GS4881 - CKAE3 GS4881 - CDAE3 8-Pin PDIP 8-Pin SOIC 8-Pin TAPE 8-Pin PDIP 8-Pin SOIC 8-Pin TAPE 8-Pin SOIC 8-Pin PDIP No No No No No No Yes Yes GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 27 of 29 Proprietary & Confidential 6.3 GS4981 Ordering Information Table 6-3: GS4981 Ordering Information Part Number Package Type Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C -25°C to 85°C -25°C to 85°C 0°C to 70°C 0°C to 70°C -25°C to 85°C Pb-Free and Green GS4981 - CDA GS4981 - CKA GS4981 - CTA GS4981 - IDA GS4981 - IKA GS4981 - CKAE3 GS4981 - CTAE3 GS4981 - IKAE3 8-Pin PDIP 8-Pin SOIC 8-Pin TAPE 8-Pin PDIP 8-Pin SOIC 8-Pin SOIC 8-Pin TAPE 8-Pin SOIC No No No No No Yes Yes Yes GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 28 of 29 Proprietary & Confidential DOCUMENT IDENTIFICATION CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATE HEADQUARTERS 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada Phone: +1 (905) 632-2996 E-mail: corporate@gennum.com Fax: +1 (905) 632-2055 www.gennum.com OTTAWA 232 Herzberg Road, Suite 101 Kanata, Ontario K2K 2A1 Canada Phone: +1 (613) 270-0458 Fax: +1 (613) 270-0429 SNOWBUSH IP - A DIVISION OF GENNUM 439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada Phone: +1 (416) 925-5643 Fax: +1 (416) 925-0581 E-mail: sales@snowbush.com Web Site: http://www.snowbush.com GERMANY Hainbuchenstraße 2 80935 Muenchen (Munich), Germany Phone: +49-89-35831696 Fax: +49-89-35804653 E-mail: gennum-germany@gennum.com CALGARY 3553 - 31st St. N.W., Suite 210 Calgary, Alberta T2L 2K7 Canada Phone: +1 (403) 284-2672 NORTH AMERICA WESTERN REGION 691 South Milpitas Blvd., Suite #200 Milpitas, CA 95035 United States Phone: +1 (408) 934-1301 Fax: +1 (408) 934-1029 E-mail: naw_sales@gennum.com MEXICO 288-A Paseo de Maravillas Jesus Ma., Aguascalientes Mexico 20900 Phone: +1 (416) 848-0328 UNITED KINGDOM North Building, Walden Court Parsonage Lane, Bishop’s Stortford Hertfordshire, CM23 5DB United Kingdom Phone: +44 1279 714170 Fax: +44 1279 714171 JAPAN KK Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo, 160-0023 Japan Phone: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 E-mail: gennum-japan@gennum.com Web Site: http://www.gennum.co.jp NORTH AMERICA EASTERN REGION 4281 Harvester Road Burlington, Ontario L7L 5M4 Canada Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055 E-mail: nae_sales@gennum.com INDIA #208(A), Nirmala Plaza, Airport Road, Forest Park Square Bhubaneswar 751009 India Phone: +91 (674) 653-4815 Fax: +91 (674) 259-5733 KOREA 8F Jinnex Lakeview Bldg. 65-2, Bangidong, Songpagu Seoul, Korea 138-828 Phone: +82-2-414-2991 Fax: +82-2-414-2998 E-mail: gennum-korea@gennum.com TAIWAN 6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C. Phone: (886) 2-8732-8879 Fax: (886) 2-8732-8870 E-mail: gennum-taiwan@gennum.com Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. All other trademarks mentioned are the properties of their respective owners. GENNUM and the Gennum logo are registered trademarks of Gennum Corporation. © Copyright 1991 Gennum Corporation. All rights reserved. www.gennum.com GS1881, GS4881, GS4981 Monolithic Video Sync Separators Data Sheet 6926 - 5 November 2009 29 of 29 29 Proprietary & Confidential