GS6150
GS6150 Multi-Rate 6G UHD-SDI
Reclocker
Gennum Products
Key Features
Applications
•
SMPTE ST 2081, ST 424, ST 292, and
ST 259-C compliant
•
•
Supports retiming data at rates of 125Mb/s, 270Mb/s,
1.485 and 1.485/1.001Gb/s, 2.97 and 2.97/1.001Gb/s,
5.94 and 5.94/1.001Gb/s
SMPTE ST 2081, SMPTE ST 424,
SMPTE ST 292, SMPTE ST 259-C coaxial cable serial
digital interfaces
•
EN50083-9 DVB-ASI interfaces
•
MADI standard
•
Supports retiming of DVB-ASI signals
•
Automatic or Manual Rate Selection
Description
Detected rate indication in Auto Mode
The GS6150 is a low-power, multi-rate serial digital
reclocker designed to automatically recover the embedded
clock from a digital video signal and re-time the incoming
video data.
•
4:1 input selector patented technology
•
Option of two reclocked data outputs
•
Four configurable GPIO pins with ability to output
device status, including:
Lock Detect
Loss of Signal (LOS)
Low/High bit-rate indication for slew-rate control of
•
SDI cable drivers
On-chip 100Ω differential input and output
termination
•
Bypass support for rates up to 5940Mb/s
Manual Bypass function
Configurable automatic Bypass when not locked
•
Option to use external reference or operate
referenceless
Cascading reference buffer supports multiple
reclockers using a single reference source
•
Input signal equalization and output signal
de-emphasis to compensate for trace dielectric losses
•
Single power supply operation at 1.8V
•
130mW typical power consumption (150mW with
second output enabled)
Pb-free and RoHS compliant
•
Operating temperature range: -40°C to 85°C
GS6150
Final Data Sheet
PDS-060127
The GS6150 features four high-speed differential signal
inputs feeding a 4:1 input selector. Input termination is onchip for seamless matching to 100Ω differential
transmission lines. The input selector is a component of a
video switching system with tightly constrained timing
requirements.
The GS6150 includes programmable trace equalization to
compensate for high-frequency losses associated with
board-level interconnect.
•
•
The GS6150 will recover the embedded clock signal and retime the data from 6G UHD-SDI signals compliant with
SMPTE ST 2081. In addition, it can also re-time SMPTE ST
259-C, SMPTE ST 292, SMPTE ST 424 or DVB-ASI compliant
digital video signals as well as MADI audio streams.
Two CML outputs interface seamlessly to devices with a
CML input reference between 1.2V and 2.5V.
Programmable output swing and de-emphasis provide
flexibility in managing signal integrity of the output signals.
The GS6150 can operate in either automatic rate detection
or manual rate selection mode. In auto mode the device
will automatically detect and lock onto incoming data
signals at any supported rate.
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The device can operate without an external 27MHz
frequency reference. For applications which require rapid
signal lock, an external 27MHz reference may be used to set
the VCO frequency when not locked to the input signal. The
presence of an external reference crystal is automatically
detected by the device.
In systems that require passing of non-supported data
rates, the GS6150 can be configured to either automatically
or manually enter a bypass mode in order to pass the signal
without reclocking.
XTAL_CLK_OUT
XTAL_CLK_IN
XTAL
Oscillator
XTAL_BUF_OUT
A four-wire serial Gennum Serial Peripheral Interface (GSPI)
facilitates configuration and status monitoring of the
device. Multiple GS6150 devices can be daisy-chained
together with a single 4-pin connection to the host system.
This device is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant. This
component and all homogenous sub-components are
RoHS compliant.
LF+, LF–
Buffer
DDO0
Reference Divide
Data Buffer
DDO0
Retimer
Phase
Frequency
Detector
DDI0
DDI0
Charge Pump
DDI1
DDI1
DDI2
DDI2
Equalizer/
Data Mux
Selectable
Divide
VCO
Phase Detector
Data
Buffer
DDO1
DDO1
DDI3
DDI3
LOS
Detect
DDI_SEL[1:0]/
STROBE
SDIN
SDO
SCLK
CS
SPI
Control
Oscillator
GPIO0 GPIO1 GPIO2 GPIO3
GS6150 Functional Block Diagram
GS6150
Final Data Sheet
PDS-060127
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Revision History
Version
ECO
PCN
Date
Changes and/or Modifications
2
024967
—
March 2015
Updated Table 2-2 and Table 2-3.
Updated Section 4.11 and Section 5.
Updated to Final Data Sheet.
1
022115
—
September 2014
Changed product title. Updated
Table 5-1 format. Updates
throughout Table 2-2 and Table 2-3.
Added Section 4.5.5. Updated
Table 5-1.
0
016784
—
December 2013
New Document
Contents
1. Pin Out.................................................................................................................................................................5
1.1 Pin Assignment ...................................................................................................................................5
1.2 Pin Descriptions ..................................................................................................................................6
2. Electrical Characteristics............................................................................................................................. 10
2.1 Absolute Maximum Ratings ........................................................................................................ 10
2.2 DC Electrical Characteristics ........................................................................................................ 10
2.3 AC Electrical Characteristics ......................................................................................................... 12
3. Input/Output Circuits.................................................................................................................................. 15
4. Detailed Description.................................................................................................................................... 17
4.1 Serial Data Inputs ............................................................................................................................. 17
4.1.1 Input Trace Equalization ................................................................................................... 17
4.1.2 Input Selection ..................................................................................................................... 17
4.2 Reference Clock ................................................................................................................................ 19
4.3 Signal Monitoring ............................................................................................................................ 19
4.3.1 Loss of Signal Detection.................................................................................................... 19
4.3.2 Lock Detection .................................................................................................................... 21
4.3.3 Rate Detection...................................................................................................................... 22
4.3.4 Low/High Bit Rate Detection for Slew Rate Control ............................................... 23
4.4 Low Power Modes ........................................................................................................................... 23
4.5 Serial Data Output ........................................................................................................................... 24
4.5.1 Output Impedance ............................................................................................................. 24
4.5.2 Output Signal Interface Levels ....................................................................................... 24
4.5.3 Adjustable Output Swing................................................................................................. 24
4.5.4 Output De-emphasis.......................................................................................................... 25
4.5.5 Output Common Mode Voltage.................................................................................... 26
4.6 Output Mute, Disable, and Data Selection ............................................................................. 26
4.7 Bypass Mode ..................................................................................................................................... 27
4.8 DVB-ASI ............................................................................................................................................... 27
GS6150
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4.9 Device Power Up ............................................................................................................................. 27
4.9.1 Power on Reset (POR) ........................................................................................................ 27
4.9.2 Reset Pin (RST) ...................................................................................................................... 27
4.10 GPIO Pins Configuration ............................................................................................................. 27
4.11 GSPI Host Interface ....................................................................................................................... 29
4.11.1 CS Pin..................................................................................................................................... 29
4.11.2 SDIN Pin................................................................................................................................ 29
4.11.3 SDOUT Pin ........................................................................................................................... 29
4.11.4 SCLK Pin................................................................................................................................ 31
4.11.5 Command Word Description........................................................................................ 31
4.11.6 GSPI Transaction Timing ................................................................................................ 34
4.11.7 Single Read/Write Access............................................................................................... 36
4.11.8 Auto-increment Read/Write Access ........................................................................... 37
4.11.9 Setting a Device Unit Address...................................................................................... 38
4.11.10 Default GSPI Operation ................................................................................................ 39
5. Host Interface Register Map...................................................................................................................... 41
6. Typical Application Circuit ........................................................................................................................ 60
7. Package and Ordering Information ....................................................................................................... 61
7.1 Package Dimensions ...................................................................................................................... 61
7.2 Recommended PCB Footprint .................................................................................................... 62
7.3 Packaging Data ................................................................................................................................ 62
7.4 Marking Diagram ............................................................................................................................. 63
7.5 Solder Reflow Profile ...................................................................................................................... 63
7.6 Ordering Information ..................................................................................................................... 63
GS6150
Final Data Sheet
PDS-060127
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1. Pin Out
VEE_CORE
VCC_CORE
VCO_FILT
LF–
LF+
VEE_CORE
VCC_CORE
RSV_41
RSV_40
RSV_39
RSV_38
RSV_37
1.1 Pin Assignment
48
47
46
45
44
43
42
41
40
39
38
37
36
DDI0
1
DDI0
2
35
VEE_DDO
GND
3
34
DDO0
DDI1
4
33
DDO0
DDI1
5
32
VEE_DDO
GND
6
31
DDO1
DDI2
7
30
DDO1
DDI2
8
29
VEE_DDO
GND
9
28
VCC_DDO1
DDI3
10
27
RST
DDI3
11
26
GPIO3
GPIO0
12
25
24
GPIO2
14
15
16
17
18
19
20
21
22
23
DDI_SEL0/STROBE
DDI_SEL1
XTAL_CLK_IN
XTAL_CLK_OUT
XTAL_BUF_OUT
SDIN
SDOUT
SCLK
CS
VDD_DIG
VSS_DIG
13
GPIO1
GS6150 48-pin QFN (6x6mm)
VCC_DDO0
Figure 1-1: GS6150 Pin Out
GS6150
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1.2 Pin Descriptions
Table 1-1: GS6150 Pin Descriptions
Pin Number
Name
Type
Description
1, 2
DDI0, DDI0
Input
Serial Digital Differential Input 0.
3, 6, 9
GND
Power
Input channel isolation. Connect to ground or leave unconnected.
4, 5
DDI1, DDI1
Input
Serial Digital Differential Input 1.
7, 8
DDI2, DDI2
Input
Serial Digital Differential Input 2.
10, 11
DDI3, DDI3
Input
Serial Digital Differential Input 3.
Multi-function Control/Status Input/Output 0.
Signal options are:
12
GPIO0
Digital
Input/Output
LOS (output; default)
LOCKED
LBR_HBR
RATE_DET0
RATE_DET1
RATE_DET2
LOCKED_125M
LOCKED_270M
LOCKED_1G485
LOCKED_2G97
LOCKED_5G94
RATE_CHANGE
DDO0_DISABLE
DDO1_DISABLE
This pin is configured using the GPIO0_SELECT and
GPIO0_IO_SELECT bits in the GPIO_CONTROL_REG_0 register.
Multi-function Control/Status Input/Output 1.
Signal options are:
13
GPIO1
Digital
Input/Output
LOS
LOCKED (output; default)
LBR_HBR
RATE_DET0
RATE_DET1
RATE_DET2
LOCKED_125M
LOCKED_270M
LOCKED_1G485
LOCKED_2G97
LOCKED_5G94
RATE_CHANGE
DDO0_DISABLE
DDO1_DISABLE
This pin is configured using the GPIO1_SELECT and
GPIO1_IO_SELECT bits in the GPIO_CONTROL_REG_0 register.
GS6150
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Table 1-1: GS6150 Pin Descriptions (Continued)
Pin Number
Name
Type
14, 15
DDI_SEL0/STROBE,
DDI_SEL1
Logic Input
16
XTAL_CLK_IN
Description
Input selection control.
Used to select the high-speed input for processing through the
device. Refer to Table 4-1 for details on input selection.
Input
Reference Crystal Pin/27MHz clock input. Connect to an external
circuit as shown in Figure 6-1: GS6150 Typical Application Circuit or
to a digital clock source (XTAL_BUF_OUT of another GS6150 or
GS6151). Connect to ground if operating referenceless.
17
XTAL_CLK_OUT
Output
Reference Crystal Pin. Connect to a external circuit as shown in Figure
6-1: GS6150 Typical Application Circuit, or leave unconnected if
XTAL_CLK_IN is driven by an external clock source or if XTAL_CLK_IN
is connected to ground (referenceless).
18
XTAL_BUF_OUT
Output
Buffered clock reference output. Leave unconnected if not used to
drive 27MHz clock input of another device.
19
SDIN
Digital Input
Serial digital data input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
Refer to 4.11 GSPI Host Interface for more details.
20
SDOUT
21
SCLK
Digital
Output
Digital Input
Serial digital data output for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
Refer to 4.11 GSPI Host Interface for more details.
Burst-mode clock input for the Gennum Serial Peripheral Interface
(GSPI) host control/status port.
Refer to 4.11 GSPI Host Interface for more details.
Chip select input for the Gennum Serial Peripheral Interface (GSPI)
host control/status port.
22
CS
Digital Input
Active-low input.
Refer to 4.11 GSPI Host Interface for more details.
23
VDD_DIG
Power
Most positive power supply for the internal logic
Connect to 1.8V.
24
VSS_DIG
Power
Most negative power supply for the internal logic
Connect to ground.
GS6150
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Table 1-1: GS6150 Pin Descriptions (Continued)
Pin Number
Name
Type
Description
Multi-function Control/Status Input/Output 2.
Signal options are:
25
GPIO2
Digital
Input/Output
LOS
LOCKED
LBR_HBR (output; default)
RATE_DET0
RATE_DET1
RATE_DET2
LOCKED_125M
LOCKED_270M
LOCKED_1G485
LOCKED_2G97
LOCKED_5G94
RATE_CHANGE
DDO0_DISABLE
DDO1_DISABLE
This pin is configured using the GPIO2_SELECT and
GPIO2_IO_SELECT bits in the GPIO_CONTROL_REG_1 register.
Multi-function Control/Status Input/Output 3.
Signal options are:
26
GPIO3
Digital
Input/Output
LOS
LOCKED
LBR_HBR
RATE_DET0
RATE_DET1
RATE_DET2
LOCKED_125M
LOCKED_270M
LOCKED_1G485
LOCKED_2G97
LOCKED_5G94
RATE_CHANGE
DDO0_DISABLE
DDO1_DISABLE (input; default)
This pin is configured using the GPIO3_SELECT and
GPIO3_IO_SELECT bits in the GPIO_CONTROL_REG_1 register.
27
RST
Digital Input
Reset pin. If set LOW, all blocks set to default conditions and inputs/
outputs set to high impedance. If HIGH, normal operation of the
device resumes. By default, internally pulled HIGH.
28
VCC_DDO1
Power
Most positive power supply connection for the DDO1/DDO1 output
driver. Connect to any voltage between 1.2V and 2.5V.
29, 32, 35
VEE_DDO
Power
Most negative power supply connections for the output drivers.
Connect to ground.
30, 31
DDO1, DDO1
Output
Differential serial data output 1.
33, 34
DDO0, DDO0
Output
Differential serial data output 0.
36
VCC_DDO0
Power
Most positive power supply connection for the DDO0/DDO0 output
driver. Connect to any voltage between 1.2V and 2.5V.
GS6150
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Table 1-1: GS6150 Pin Descriptions (Continued)
Pin Number
Name
Type
37
RSV_37
Power
Decoupling
38
RSV_38
Power
Connect to 1.8V.
39
RSV_39
Power
Connect to ground.
40, 41
RSV_40, RSV_41
Input
Leave unconnected.
42
VCC_CORE
Power
Most positive power supply connection to the analog core
Connect to 1.8V.
43
VEE_CORE
Power
Most negative power supply connection to the analog core
Connect to ground.
44
LF+
Passive
Connect to LF– through CLF
Refer to Figure 6-1: GS6150 Typical Application Circuit.
45
LF–
Passive
Connect to LF+ through CLF
Refer to Figure 6-1: GS6150 Typical Application Circuit.
46
VCO_FILT
Power
47
VCC_CORE
Power
Most positive power supply connection for the analog core
Connect to 1.8V.
48
VEE_CORE
Power
Most negative power supply connection to the analog core
Connect to ground.
—
Center Pad
Power
Ground pad on bottom of package.
GS6150
Final Data Sheet
PDS-060127
Description
Connect through decoupling capacitor to ground.
External decoupling for the VCO.
Refer to Figure 6-1: GS6150 Typical Application Circuit.
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value
Supply Voltage – Core (VCC_CORE, VDD_DIG)
–0.5 to +2.1VDC
Supply Voltage – Output Driver (VCC_DDO0,
VCC_DDO1)
–0.5 to +2.8VDC
Input ESD Voltage
4kV
Storage Temperature Range (TS)
–50ºC to +125ºC
Operating Temperature Range (TA)
–40ºC to +85ºC
Input Voltage Range (any input pin)
–0.3 to (VCC_CORE + 0.3)VDC
Solder Reflow Temperature
+260ºC
Note: Absolute Maximum Ratings are those values beyond which damage may occur.
Functional operation outside of the ranges shown in the AC/DC electrical characteristics tables
is not guaranteed.
2.2 DC Electrical Characteristics
Table 2-2: DC Electrical Characteristics
VCC_CORE, VDD_DIG = +1.8V ± 5%, TA= –40ºC to +85ºC unless otherwise specified
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage – Core
(VCC_CORE, VDD_DIG)
VCC_CORE,
VDD_DIG
—
1.710
1.8
1.890
V
Supply Voltage – Output
Driver (VCC_DDO0,
VCC_DDO1)
VCC_DDO0,
VCC_DDO1
—
1.140
—
2.625
V
GS6150
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Table 2-2: DC Electrical Characteristics (Continued)
VCC_CORE, VDD_DIG = +1.8V ± 5%, TA= –40ºC to +85ºC unless otherwise specified
Parameter
Symbol
Min
Typ
Max
Units
Notes
Data Rate 6G,
DDO1/DDO1 disabled
—
140
185
mW
1, 2
Data Rate SDOUT non-clocked path for all devices on chip select.
GS6150
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2. Write to Unit Address 0 selecting HOST_CONFIG (ADDRESS = 0), with the
GSPI_LINK_DISABLE bit set to 0 and the DEVICE_UNIT_ADDRESS field set to a
unique Unit Address. This configures DEVICE_UNIT_ADDRESS for the first device in
the chain. Each subsequent such write to Unit Address 0 will configure the next
device in the chain. If there are 32 devices in a chain, the last (32nd) device in the
chain must use DEVICE_UNIT_ADDRESS value 0.
3. Repeat step 2 using new, unique values for the DEVICE_UNIT_ADDRESS field in
HOST_CONFIG until all devices in the chain have been configured with their own
unique Unit Address value.
Note: tcmd_GSPI_conf delay must be observed after every write that modifies
HOST_CONFIG.
All connected devices receive this command (by default the Unit Address of all devices
is 0), and the Loop-Through operation will be re-established for all connected devices.
Once configured, each device will only respond to Command Words with a
UNIT ADDRESS field matching the DEVICE_UNIT_ADDRESS in HOST_CONFIG
Note: Although the Loop-Through and Bus-Through configurations are compatible
with previous generation GSPI enabled devices (backward compatibility), only devices
supporting Unit Addressing can share a chip select. All devices on any single chip select
must be connected in a contiguous chain with only the last device's SDOUT connected
to the application host processor. Multiple chains configured in Bus-Through mode can
have their final SDOUT outputs connected to a single application host processor input.
4.11.10 Default GSPI Operation
By default at power up or after a device reset, the GS6150 is set for Loop-Through
Operation and the internal DEVICE_UNIT_ADDRESS field of the device is set to 0.
Figure 4-21 shows a functional block diagram of the Configuration and Status Register
(CSR) map in the GS6150 for non-extended memory accesses (EMEM = 0).
At power-up or after a device reset, DEVICE_UNIT_ADDRESS = 00h
bits
[15]
[14]
[13]
[12]
[11:7]
[6:0]
CMD
R/W
BCAST
ALL
EMEM
Auto
Inc
Unit Address
32 devices
Local Address
128 registers
[15:0]
bits
DATA
bits
Reg 0
Compare
Data to be written / Read Data
[15]
[14]
[13]
[12:5]
[4:0]
RESERVED
GSPI_LINK
_DISABLE
GSPI_BUS_
THROUGH
_ENABLE
RESERVED
DEVICE_UNIT_ADDRESS
Read/Write
Reg 1
Configuration and Status Registers
Reg 128
Figure 4-21: Internal Register Map Functional Block Diagram
GS6150
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The steps required for the application host processor to write to the Configuration and
Status Registers via the GSPI, are as follows:
1. Set Command Word for write access (R/W = 0) to the local registers 0h-80h; set Auto
Increment; set the Unit Address field in the Command Word to match the
configured DEVICE_UNIT_ADDRESS which will be zero. Write the Command Word.
2. Write the Data Word to be written to the first register.
3. Write the Data Word to be written to the next register in Auto Increment mode, etc.
Read access is the same as the above with the exception of step 1, where the Command
Word is set for read access (R/W = 1).
Note: The UNIT ADDRESS field of the Command Word must always match
DEVICE_UNIT_ADDRESS for an access to be accepted by the device. Changing
DEVICE_UNIT_ADDRESS to a value other than 0 is only required if multiple devices are
connected to a single chip select (in Loop-Through or Bus-Through configuration.)
GS6150
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5. Host Interface Register Map
Table 5-1: Register Descriptions - Standard Address Space
Address Register Name
0h
1h
HOST_CONFIG
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
RSVD
15:15
RW
0h
Reserved. Do not change.
GSPI_LINK_DISABLE
14:14
RW
0h
GSPI loop-through disable.
GSPI_BUS_THROUGH_
ENABLE
13:13
RW
0h
GSPI bus-through enable.
RSVD
12:5
RW
0h
Reserved. Do not change.
DEVICE_UNIT_ADDRESS
4:0
RW
0h
Device address programmed by application.
RSVD
15:8
RO
1h
Reserved.
DEVICE_VERSION_ID
7:0
RO
-
Device Version Identifier.
RSVD
15:14
RW
0h
Reserved. Do not change.
GPIO1_IO_SELECT
13:13
RW
0h
0b: Output
1b: Input
RSVD
12:11
RW
0h
Reserved. Do not change.
DEVICE_INFO
GPIO1 Input/Output Select
GPIO1 Signal Selection
2h
GPIO_CONTROL_
REG_0
GPIO1_SELECT
10:7
RW
1h
If GPIO1_IO_SELECT is set to 0:
0000b: LOS
0001b: LOCKED (default)
0010b: LBR_HBR
0011b: Reserved
0100b: Reserved
0101b: RATE_DET0
0110b: RATE_DET1
0111b: RATE_DET2
1000b: LOCKED_125M
1001b: LOCKED_270M
1010b: LOCKED_1G485
1011b: LOCKED_2G97
1100b: LOCKED_5G94
1101b: RATE_CHANGE
If GPIO1_IO_SELECT is set to 1:
0000b: DDO0_DISABLE
0001b: DDO1_DISABLE
GPIO0 Input/Output Select
GS6150
Final Data Sheet
PDS-060127
GPIO0_IO_SELECT
6:6
RW
0h
0b: Output
1b: Input
RSVD
5:4
RW
0h
Reserved. Do not change.
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
GPIO0 Signal Selection
2h
GPIO_CONTROL_
REG_0
GPIO0_SELECT
3:0
RW
0h
If GPIO0_IO_SELECT is set to 0:
0000b: LOS (default)
0001b: LOCKED
0010b: LBR_HBR
0011b: Reserved
0100b: Reserved
0101b: RATE_DET0
0110b: RATE_DET1
0111b: RATE_DET2
1000b: LOCKED_125M
1001b: LOCKED_270M
1010b: LOCKED_1G485
1011b: LOCKED_2G97
1100b: LOCKED_5G94
1101b: RATE_CHANGE
If GPIO0_IO_SELECT is set to 1:
0000b: DDO0_DISABLE
0001b: DDO1_DISABLE
GS6150
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
RSVD
15:14
RW
0h
GPIO3_IO_SELECT
13:13
RW
1h
0b: Output
1b: Input
RSVD
12:11
RW
0h
Reserved. Do not change.
Reserved. Do not change.
GPIO3 Input/Output Select
GPIO3 Signal Selection
3h
GPIO_CONTROL_
REG_1
GPIO3_SELECT
10:7
RW
1h
If GPIO3_IO_SELECT is set to 0:
0000b: LOS
0001b: LOCKED
0010b: LBR_HBR
0011b: Reserved
0100b: Reserved
0101b: RATE_DET0
0110b: RATE_DET1
0111b: RATE_DET2
1000b: LOCKED_125M
1001b: LOCKED_270M
1010b: LOCKED_1G485
1011b: LOCKED_2G97
1100b: LOCKED_5G94
1101b: RATE_CHANGE
If GPIO3_IO_SELECT is set to 1:
0000b: DDO0_DISABLE
0001b: DDO1_DISABLE (default)
GPIO2 Input/Output Select
GPIO2_IO_SELECT
GS6150
Final Data Sheet
PDS-060127
6:6
RW
www.semtech.com
Rev.2
March 2015
0h
0b: Output
1b: Input
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Proprietary & Confidential
Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
RSVD
5:4
RW
Reset
Description
Value
0h
Reserved. Do not change.
GPIO2 Signal Selection
3h
GPIO_CONTROL_
REG_1
GPIO2_SELECT
3:0
RW
2h
If GPIO2_IO_SELECT is set to 0:
0000b: LOS
0001b: LOCKED
0010b: LBR_HBR (default)
0011b: Reserved
0100b: Reserved
0101b: RATE_DET0
0110b: RATE_DET1
0111b: RATE_DET2
1000b: LOCKED_125M
1001b: LOCKED_270M
1010b: LOCKED_1G485
1011b: LOCKED_2G97
1100b: LOCKED_5G94
1101b: RATE_CHANGE
If GPIO2_IO_SELECT is set to 1:
0000b: DDO0_DISABLE
0001b: DDO1_DISABLE
4h
RESERVED
RSVD
15:0
RW
1Ch
Reserved. Do not change.
DDI3 Trace-EQ Configuration
DDI3_TRACE_EQ_CONTROL
7:6
RW
0h
00b: OFF
01b: 0dB/EQ BYPASS
10b: LOW
11b: HIGH
DDI2 Trace-EQ Configuration
DDI2_TRACE_EQ_ CONTROL
5h
5:4
RW
0h
INPUT_CONTROL_
REG_0
00b: OFF
01b: 0dB/EQ BYPASS
10b: LOW
11b: HIGH
DDI1 Trace-EQ Configuration
DDI1_TRACE_EQ_ CONTROL
3:2
RW
0h
00b: OFF
01b: 0dB/EQ BYPASS
10b: LOW
11b: HIGH
DDI0 Trace-EQ Configuration
DDI0_TRACE_EQ_ CONTROL
GS6150
Final Data Sheet
PDS-060127
1:0
RW
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Rev.2
March 2015
0h
00b: OFF
01b: 0dB/EQ BYPASS
10b: LOW
11b: HIGH
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
6h
RESERVED
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
RSVD
15:0
RW
0h
Reserved. Do not change.
RSVD
15:12
RW
0h
Reserved. Do not change.
Input Selection
DDI_SELECT
11:10
RW
0h
00b: DDI0
01b: DDI1
10b: DDI2
11b: DDI3
Used when INPUT_SELECTION_CONTROL is
set to 01b or 11b
Determines the source for the input
selection block.
INPUT_SELECTION_CONTROL
7h
INPUT_CONTROL_
REG_2
DDI3_TRACE_EQ_DC_TERM_
ENABLE
DDI2_TRACE_EQ_DC_TERM_
ENABLE
DDI1_TRACE_EQ_DC_TERM_
ENABLE
9:8
7:7
6:6
5:5
RW
RW
RW
RW
0h
1h
1h
1h
X0b: Use DDI_SEL0_STROBE and DDI_SEL1
pins.
01b: Use DDI_SELECT bits
11b: Use DDI_SELECT bits; update occurs on
low-to-high transition of DDI_SEL0_STROBE
pin.
Enable DDI3 on-chip Trace-EQ DC
termination.
0b: Disabled
1b: Enabled
Enable DDI2 on-chip Trace-EQ DC
termination.
0b: Disabled
1b: Enabled
Enable DDI1 on-chip Trace-EQ DC
termination.
0b: Disabled
1b: Enabled
Enable DDI0 on-chip Trace-EQ DC
termination.
DDI0_TRACE_EQ_DC_TERM_
ENABLE
4:4
RW
1h
RSVD
3:0
RW
0h
Reserved. Do not change.
0b: Disabled
1b: Enabled
8h
RESERVED
RSVD
15:0
ROCW
—
Reserved. Do not change.
9h
RESERVED
RSVD
15:0
RO
—
Reserved.
Ah
RESERVED
RSVD
15:0
RO
—
Reserved.
Bh
RESERVED
RSVD
15:0
RO
—
Reserved.
Ch
RESERVED
RSVD
15:0
RO
—
Reserved.
GS6150
Final Data Sheet
PDS-060127
www.semtech.com
Rev.2
March 2015
45 of 64
Proprietary & Confidential
Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
Dh
RESERVED
RSVD
15:0
RO
—
Reserved.
Eh
RESERVED
RSVD
15:0
RO
—
Reserved.
RSVD
15:10
RW
0h
Reserved. Do not change.
0h
Enables LOS threshold adjustment based on
the settings in the
DDI[3:0]_LOS_THRESHOLD_CONTROL bits
in the LOS_CONTROL_REG_1 and
LOS_CONTROL_REG_2 registers.
LOS_THRESHOLD_CONTROL_
ENABLE
9:9
RW
0b: Default internal thresholds are used
1b: Thresholds used in the
LOS_CONTROL_REG_1 and
LOS_CONTROL_REG_2 registers
LOS De-Assert Time Delay:
LOS_DEASSERT_TIME
8:7
RW
2h
00b: 2.30μs
01b: 1.50μs
10b: 1.20μs
11b: 0.90μs
LOS Assert Time Delay:
LOS_ASSERT_TIME
Fh
6:5
RW
2h
LOS_CONTROL_
REG_0
LOS Threshold Hysteresis Adjustment:
LOS_HYSTERESIS
4:1
LOS_PWRDN_OVERRIDE
GS6150
Final Data Sheet
PDS-060127
0:0
RW
RW
www.semtech.com
Rev.2
March 2015
00b: 68μs
01b: 64μs
10b: 62μs
11b: 61μs
0h
0h
0000b: 0 dB
0001b: 0.32 dB
0010b: 0.64 dB
0011b: 0.98 dB
0100b: 1.34 dB
0101b: 1.70 dB
0110b: 2.09 dB
0111b: 2.49 dB
1000b: 2.84 dB
1001b: 3.28 dB
1010b: 3.74 dB
1011b: 4.23 dB
1100b: 4.75 dB
1101b: 5.30 dB
1110b: 5.89 dB
1111b: 6.53 dB
Override the internal power-down control
for the LOS circuit.
0b: LOS active
1b: LOS powered down
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
DDI1_LOS_THRESHOLD_
CONTROL
10h
Bit
Slice
R/W
Reset
Description
Value
LOS signal threshold for input DDI1 at
device pins is:
15:8
RW
5Ah
1.9mVppd x DDI1_LOS_THRESHOLD_CONTROL x
(53/DEVICE_SPECIFIC_LOS_THRESHOLD)
(All above values are in decimal)
LOS_CONTROL_
REG_1
DDI0_LOS_THRESHOLD_
CONTROL
LOS signal threshold for input DDI0 at
device pins is:
7:0
RW
5Ah
1.9mVppd x DDI0_LOS_THRESHOLD_CONTROL x
(53/DEVICE_SPECIFIC_LOS_THRESHOLD)
(All above values are in decimal)
DDI3_LOS_THRESHOLD_
CONTROL
11h
LOS signal threshold for input DDI3 at
device pins is:
15:8
RW
5Ah
1.9mVppd x DDI3_LOS_THRESHOLD_CONTROL x (53/
DEVICE_SPECIFIC_LOS_THRESHOLD)
(All above values are in decimal)
LOS_CONTROL_
REG_2
DDI2_LOS_THRESHOLD_
CONTROL
LOS signal threshold for input DDI2 at
device pins is:
7:0
RW
5Ah
1.9mVppd x DDI2_LOS_THRESHOLD_CONTROL x
(53/DEVICE_SPECIFIC_LOS_THRESHOLD)
(All above values are in decimal)
RSVD
12h
LOS_STATUS
DEVICE_SPECIFIC_LOS_
THRESHOLD
15:8
RO
—
Reserved.
7:0
RO
—
Trimmed setting to achieve LOS threshold of
100mVppd
13h
RESERVED
RSVD
15:0
RW
280h
14h
RESERVED
RSVD
15:0
RO
—
Reserved.
RSVD
15:3
RW
0h
Reserved. Do not change.
REF_CLK_
CONTROL
15h
16h
Reserved. Do not change.
Enables/Disables the reference buffer
output.
XTAL_BUF_OUT_ENABLE
2:2
RW
1h
RSVD
1:1
RW
0h
Reserved. Do not change.
RSVD
0:0
RW
0h
Reserved. Do not change.
RSVD
15:1
RO
—
Reserved.
REF_CLK_STATUS
XTAL_CLK_DET
0:0
RO
-
0b: XTAL_BUF_OUT disabled
1b: XTAL_BUF_OUT enabled
Indicates whether an external 27MHz
reference is being used by the device or its
internal oscillator.
0b: Internal oscillator being used
1b: External crystal being used
GS6150
Final Data Sheet
PDS-060127
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Rev.2
March 2015
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
AUTO_PWRDN_MODE
Bit
Slice
3:3
R/W
RW
Reset
Description
Value
0h
Selects the low power mode, SLEEP or
STANDBY that is entered into when
AUTO_PWRDN_DISABLE is set to 0 and LOS
is asserted.
0b: SLEEP mode is selected (default)
1b: STANDBY mode is selected
FORCE_PWRDN_STANDBY
17h
2:2
RW
0h
Forces the device into STANDBY mode when
FORCE_PWRDN_SLEEP is set to 0.
0b: Device not in STANDBY mode
1b: Device in STANDBY mode
Forces the device into SLEEP mode when
AUTO_PWRDN_DISABLE is set to 1.
PWRDN_
CONTROL
FORCE_PWRDN_SLEEP
1:1
RW
0h
0b: Device not in SLEEP mode
1b: Device in SLEEP mode
When FORCE_PWRDN_SLEEP is set to 1, it
takes precedence over the
FORCE_PWRDN_STANDBY bit.
Disables Auto Powerdown mode which
automatically enters SLEEP or STANDBY
mode when LOS is asserted.
18h
GS6150
Final Data Sheet
PDS-060127
RESERVED
AUTO_PWRDN_DISABLE
0:0
RW
1h
RSVD
15:0
RO
—
www.semtech.com
Rev.2
March 2015
0b: Device automatically enters SLEEP or
STANDBY when LOS is 1
1b: Device only enters SLEEP or STANDBY
when FORCE_PWRDN_SLEEP or
FORCE_PWRDN_STANDBY are set to 1
Reserved.
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
RSVD
15:8
RW
0h
Reserved. Do not change.
RSVD
7:7
RW
1h
Reserved. Do not change.
AUTO_LOS_MUTE_ENABLE
6:6
RW
0h
Auto-Mute Enable on LOS.
0b: Output is unaffected by LOS
1b: Output is muted when LOS is asserted
Mute control for the DDO1 output.
DDO1_MUTE
5:5
RW
0h
0b: DDO1 output not muted
1b: DDO1 output muted
Output across DDO1 and DDO1 is static and
of magnitude DDO1_SWING_MUTE/2 when
DDO1_DISABLE is set to 0.
Mute control for the DDO0 output.
DDO0_MUTE
4:4
RW
0h
0b: DDO0 output not muted
1b: DDO0 output muted
Output across DDO0 and DDO0 is static and
of magnitude DDO0_SWING_MUTE/2 when
DDO0_DISABLE is set to 0.
Disable control for the DDO1 output.
19h
DRIVER_CONTROL_
REG_0
DDO1_DISABLE
3:3
RW
0h
0b: DDO1 output not disabled
1b: DDO1 output disabled
Output of both DDO1 and DDO1 is
VCC_DDO1.
This bit takes precedence over DDO1_MUTE.
Disable control for the DDO0 output.
DDO0_DISABLE
2:2
RW
0h
0b: DDO0 output not disabled
1b: DDO0 output disabled
Output of both DDO0 and DDO0 is
VCC_DDO0.
This bit takes precedence over DDO0_MUTE.
DDO1_DISABLE_SELECT
DDO0_DISABLE_SELECT
GS6150
Final Data Sheet
PDS-060127
1:1
0:0
RW
RW
www.semtech.com
Rev.2
March 2015
0h
1h
Controls whether DDO1 is disabled using an
assigned GPIO pin or the DDO1_DISABLE
bit.
0b: DDO1 is disabled using assigned GPIO
1b: DDO1 is disabled using the
DDO1_DISABLE bit
Controls whether DDO0 is disabled using an
assigned GPIO pin or the DDO0_DISABLE
bit.
0b: DDO0 is disabled using assigned GPIO
1b: DDO0 is disabled using the
DDO0_DISABLE bit
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
RSVD
15:15
RW
DDO0_DEEMPHASIS_5G94
DDO0_DEEMPHASIS_2G97
1Ah
DRIVER_CONTROL_
REG_1
DDO0_DEEMPHASIS_1G485
DDO0_DEEMPHASIS_270M
DDO0_DEEMPHASIS_125M
GS6150
Final Data Sheet
PDS-060127
14:12
11:9
8:6
5:3
2:0
RW
RW
RW
RW
RW
www.semtech.com
Rev.2
March 2015
Reset
Description
Value
0h
Reserved. Do not change.
2h
De-emphasis control for 5.94Gb/s (6Gb/s
UHD-SDI) signals output on DDO0
000b: 0dB
001b: 0.3dB
010b: 0.6dB (default)
011b: 2.3 B
100b: 4.0dB
101b: 6.6dB
110b: 10.0dB
1h
De-emphasis control for 2.97Gb/s (3Gb/s SDI)
signals output on DDO0
000b: 0dB
001b: 0.4dB (default)
010b: 1.5dB
011b: 3.2dB
100b: 4.9dB
101b: 7.6dB
110b: 11.0dB
1h
De-emphasis control for 1.485Gb/s (HD-SDI)
signals output on DDO0
000b: 0dB
001b: 1.1dB (default)
010b: 2.4dB
011b: 4.0dB
100b: 5.7dB
101b: 8.2dB
110b: 11.5dB
0h
De-emphasis control for 0.27Gb/s (SD-SDI)
signals output on DDO0
000b: 0dB (default)
001b: 1.2dB
010b: 2.5dB
011b: 4.1dB
100b: 6.0dB
101b: 8.5dB
110b: 12.0dB
0h
De-emphasis control for 0.125Gb/s (MADI)
signals output on DDO0
000b: 0dB (default)
001b: 1.2dB
010b: 2.5dB
011b: 4.1dB
100b: 6.0dB
101b: 8.5dB
110b: 12.0dB
50 of 64
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
RSVD
15:15
RW
DDO1_DEEMPHASIS_5G94
DDO1_DEEMPHASIS_2G97
1Bh
DRIVER_CONTROL_
REG_2
DDO1_DEEMPHASIS_1G485
DDO1_DEEMPHASIS_270M
DDO1_DEEMPHASIS_125M
GS6150
Final Data Sheet
PDS-060127
14:12
11:9
8:6
5:3
2:0
RW
RW
RW
RW
RW
www.semtech.com
Rev.2
March 2015
Reset
Description
Value
0h
Reserved. Do not change.
2h
De-emphasis control for 5.94Gb/s (6Gb/s
UHD-SDI) signals output on DDO1
000b: 0dB
001b: 0.3dB
010b: 0.6dB (default)
011b: 2.3 B
100b: 4.0dB
101b: 6.6dB
110b: 10.0dB
1h
De-emphasis control for 2.97Gb/s (3Gb/s SDI)
signals output on DDO1
000b: 0dB
001b: 0.4dB (default)
010b: 1.5dB
011b: 3.2dB
100b: 4.9dB
101b: 7.6dB
110b: 11.0dB
1h
De-emphasis control for 1.485Gb/s (HD-SDI)
signals output on DDO1
000b: 0dB
001b: 1.1dB (default)
010b: 2.4dB
011b: 4.0dB
100b: 5.7dB
101b: 8.2dB
110b: 11.5dB
0h
De-emphasis control for 0.27Gb/s (SD-SDI)
signals output on DDO1
000b: 0dB (default)
001b: 1.2dB
010b: 2.5dB
011b: 4.1dB
100b: 6.0dB
101b: 8.5dB
110b: 12.0dB
0h
De-emphasis control for 0.125Gb/s (MADI)
signals output on DDO1
000b: 0dB (default)
001b: 1.2dB
010b: 2.5dB
011b: 4.1dB
100b: 6.0dB
101b: 8.5dB
110b: 12.0dB
51 of 64
Proprietary & Confidential
Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
1Ch
DRIVER_CONTROL_
REG_3
Parameter Name
Bit
Slice
R/W
RSVD
15:12
RW
0h
Reserved. Do not change.
DDO0_SWING_1G485
11:8
RW
3h
Differential swing (amplitude) control for
1.485Gb/s (HD-SDI) signals output on DDO0.
For details refer to Section 4.5.3.
DDO0_SWING_270M
7:4
RW
3h
Differential swing (amplitude) control for
0.27Gb/s (SD-SDI) signals output on DDO0.
For details refer to Section 4.5.3.
DDO0_SWING_125M
3:0
RW
3h
Differential swing (amplitude) control for
0.125Gb/s (MADI) signals output on DDO0.
For details refer to Section 4.5.3.
DDO0_SWING_BYPASS
15:12
RW
Reset
Description
Value
3h
Differential swing (amplitude) control for
unlocked signals output on DDO0 (when
reclocker is operating in BYPASS mode). For
details refer to Section 4.5.3.
Takes precedence over rate-specific swing
controls
1Dh
1Eh
DRIVER_CONTROL_
REG_4
DRIVER_CONTROL_
REG_5
GS6150
Final Data Sheet
PDS-060127
DDO0_SWING_MUTE
11:8
RW
Takes precedence over rate-specific swing
controls and bypass swing control
DDO0_SWING_5G94
7:4
RW
3h
Differential swing (amplitude) control for
5.94Gb/s (6G UHD-SDI) signals output on
DDO0. For details refer to Section 4.5.3.
DDO0_SWING_2G97
3:0
RW
3h
Differential swing (amplitude) control for
2.97Gb/s (3Gb/s SDI) signals output on
DDO0. For details refer to Section 4.5.3.
RSVD
15:12
RW
0h
Reserved. Do not change.
DDO1_SWING_1G485
11:8
RW
3h
Differential swing (amplitude) control for
1.485Gb/s (HD-SDI) signals output on DDO1.
For details refer to Section 4.5.3.
DDO1_SWING_270M
7:4
RW
3h
Differential swing (amplitude) control for
0.27Gb/s (SD-SDI) signals output on DDO1.
For details refer to Section 4.5.3.
DDO1_SWING_125M
3:0
RW
3h
Differential swing (amplitude) control for
0.125Gb/s (MADI) signals output on DDO1.
For details refer to Section 4.5.3.
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Rev.2
March 2015
3h
Differential static amplitude control for
DDO0 when the output is muted. For details
refer to Section 4.5.3.
52 of 64
Proprietary & Confidential
Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
DDO1_SWING_BYPASS
Bit
Slice
15:12
R/W
RW
Reset
Description
Value
3h
Differential swing (amplitude) control for
unlocked signals output on DDO1 (when
reclocker is operating in BYPASS mode). For
details refer to Section 4.5.3.
Also applies when the device is not locked.
Takes precedence over rate-specific swing
controls
1Fh
DRIVER_CONTROL_
REG_6
DDO1_SWING_MUTE
11:8
RW
3h
Differential static amplitude control for
DDO1 when the output is muted. For details
refer to Section 4.5.3.
Takes precedence over rate-specific swing
controls and bypass swing control
DDO1_SWING_5G94
7:4
RW
3h
Differential swing (amplitude) control for
5.94Gb/s (6G UHD-SDI) signals output on
DDO1. For details refer to Section 4.5.3.
DDO1_SWING_2G97
3:0
RW
3h
Differential swing (amplitude) control for
2.97Gb/s (3Gb/s SDI) signals output on
DDO1. For details refer to Section 4.5.3.
RSVD
15:2
RW
0h
Reserved. Do not change.
Used to manually bypass the retiming block
in the reclocker.
MANUAL_BYPASS
20h
1:1
RW
0h
0b: Retimer not bypassed
1b: Retimer bypassed
The assertion of MANUAL_BYPASS takes
precedence irrespective of the setting of
AUTO_BYPASS
RECLOCKER_
BYPASS
Selects between automatic and manual
bypass of the retiming block when the
reclocker is not locked.
AUTO_BYPASS
0:0
RW
1h
0b: Auto-Bypass is disabled
1b: Auto-Bypass is enabled
Even if AUTO_BYPASS is asserted, the
assertion of MANUAL_BYPASS will still cause
the retimer to be bypassed.
RSVD
15:7
RW
1h
Reserved. Do not change.
Selects sampling method for LOCK
DETECTION
LOCK_SAMPLE
21h
6:6
RW
0h
PD_CONTROL
GS6150
Final Data Sheet
PDS-060127
0b: Strict sampling
1b: High-jitter sampling
RSVD
5:1
RW
2h
Reserved. Do not change.
POLARITY_INVERT
0:0
RW
0h
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Proprietary & Confidential
Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
22h
RESERVED
RSVD
15:0
RW
23h
RESERVED
RSVD
15:0
RW
0h
Reserved. Do not change.
24h
RESERVED
RSVD
15:0
ROSW
0h
Reserved. Do not change.
25h
RESERVED
RSVD
15:0
RW
0h
Reserved. Do not change.
26h
RESERVED
RSVD
15:0
RW
2h
Reserved. Do not change.
27h
RESERVED
RSVD
15:0
RW
A8Bh
Reserved. Do not change.
28h
RESERVED
RSVD
15:0
RW
3h
Reserved. Do not change.
29h
RESERVED
RSVD
15:0
RW
3h
Reserved. Do not change.
2Ah
RESERVED
RSVD
15:0
RW
3h
Reserved. Do not change.
2Bh
RESERVED
RSVD
15:0
RW
2h
Reserved. Do not change.
2Ch
RESERVED
RSVD
15:0
RO
0h
Reserved.
2Dh
RESERVED
RSVD
15:0
RO
0h
Reserved.
2Eh
RESERVED
RSVD
15:0
RO
0h
Reserved.
2Fh
RESERVED
RSVD
15:0
RO
0h
Reserved.
30h
RESERVED
RSVD
15:0
RO
0h
Reserved.
31h
RESERVED
RSVD
15:0
RO
0h
Reserved.
32h
RESERVED
RSVD
15:0
RO
0h
Reserved.
33h
RESERVED
RSVD
15:0
RO
0h
Reserved.
34h
RESERVED
RSVD
15:0
RO
0h
Reserved.
35h
RESERVED
RSVD
15:0
RO
0h
Reserved.
36h
RESERVED
RSVD
15:0
RO
0h
Reserved.
37h
RESERVED
RSVD
15:0
RO
0h
Reserved.
38h
RESERVED
RSVD
15:0
RO
0h
Reserved.
39h
RESERVED
RSVD
15:0
RW
2h
Reserved. Do not change.
3Ah
RESERVED
RSVD
15:0
ROSW
0h
Reserved. Do not change.
3Bh
RESERVED
RSVD
15:0
RW
0h
Reserved. Do not change.
3Ch
RESERVED
RSVD
15:0
RW
2h
Reserved. Do not change.
3Dh
RESERVED
RSVD
15:0
RW
A8Bh
Reserved. Do not change.
GS6150
Final Data Sheet
PDS-060127
www.semtech.com
Rev.2
March 2015
4208h Reserved. Do not change.
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
3Eh
RESERVED
RSVD
15:0
RW
3h
Reserved. Do not change.
3Fh
RESERVED
RSVD
15:0
RW
3h
Reserved. Do not change.
40h
RESERVED
RSVD
15:0
RW
0h
Reserved. Do not change.
41h
RESERVED
RSVD
15:0
RO
0h
Reserved. Do not change.
42h
RESERVED
RSVD
15:0
RO
0h
Reserved.
43h
RESERVED
RSVD
15:0
RO
0h
Reserved.
44h
RESERVED
RSVD
15:0
RO
0h
Reserved.
45h
RESERVED
RSVD
15:0
RO
0h
Reserved.
46h
RESERVED
RSVD
15:0
RO
0h
Reserved.
47h
RESERVED
RSVD
15:0
RO
0h
Reserved.
48h
RESERVED
RSVD
15:0
RO
0h
Reserved.
49h
RESERVED
RSVD
15:0
RO
0h
Reserved.
4Ah
RESERVED
RSVD
15:0
RO
0h
Reserved.
4Bh
RESERVED
RSVD
15:0
RO
0h
Reserved.
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Final Data Sheet
PDS-060127
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Rev.2
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
RSVD
15:12
RW
0h
LOS_DETECTION_METHOD
11:10
RW
1h
Reserved. Do not change.
Determines the source of CARRIER_DETECT.
00b: Edge detection
01b: Strength detection
Force the PLL to retime a specific data rate.
FORCE_PLL_RATE
9:7
RW
1h
FORCE_PLL_RATE_ENABLE
6:6
RW
0h
Enables the forced PLL rate override set
using the FORCE_PLL_RATE bits.
0h
Enables auto-detection of 0.125Gb/s (MADI)
signals
0b: 0.125Gb/s signals will not be detected
1b: 0.125Gb/s signals will be detected
1h
Enables auto-detection of 5.94Gb/s
(6G UHD-SDI) signals.
0b: 5.94Gb/s signals will not be detected
1b: 5.94Gb/s signals will be detected
1h
Enables auto-detection of 2.97Gb/s
(3G SDI) signals.
0b: 2.97Gb/s signals will not be detected
1b: 2.97Gb/s signals will be detected
1h
Enables auto-detection of 1.485Gb/s (HDSDI) signals.
0b: 1.485Gb/s signals will not be detected
1b: 1.485Gb/s signals will be detected
1h
Enables auto-detection of 0.27Gb/s
(SD-SDI) signals.
0b: 0.27Gb/s signals will not be detected
1b: 0.27Gb/s signals will be detected
RATE_ENABLE_125M
4Ch
000b: Reserved
001b: 0.270Gb/s
010b: 1.485Gb/s
011b: 2.97Gb/s
100b: 5.94Gb/s
101b: Reserved
110b: Reserved
111b: Reserved
Used when FORCE_PLL_RATE_ENABLE is set
to 1.
5:5
RW
PLL_CONTROL
RATE_ENABLE_5G94
RATE_ENABLE_2G97
RATE_ENABLE_1G485
RATE_ENABLE_270M
4:4
3:3
2:2
1:1
RW
RW
RW
RW
Synchronous soft-reset for the PLL rate
detection state machine.
PLL_SOFT_RESET
GS6150
Final Data Sheet
PDS-060127
0:0
RW
www.semtech.com
Rev.2
March 2015
0h
0b: Normal operation of the PLL rate
detection state machine
1b: Resets the PLL rate detection state
machine
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
Bit
Slice
R/W
Reset
Description
Value
4Dh
RESERVED
RSVD
15:0
RW
110h
Reserved. Do not change.
4Eh
RESERVED
RSVD
15:0
RW
110h
Reserved. Do not change.
RETIMER_BYPASS
15:15
RO
—
Indicates whether the retimer is active or
bypassed.
0b: Retimer is active
1b: Retimer is bypassed
Indicates high-bit-rate versus low-bit-rate.
LBR_HBR
14:14
RO
—
0b: Input data rate is 5.94Gb/s,
2.97Gb/s, 1.485Gb/s, or BYPASS
1b: Input data rate is 270Mb/s or 125Mb/s
Indicates the current rate found by the PLL
rate detection state machine.
4Fh
DETECTED_RATE
13:11
RO
—
RSVD
10:10
RO
—
LOCKED
9:9
RO
—
PLL_STATUS
000b: 0.125Gb/s
001b: 0.270Gb/s
010b: 1.485Gb/s
011b: 2.97Gb/s
100b: 5.94Gb/s
101b: Reserved
110b: Reserved
111b: Reserved
Reserved.
Indicates if the CDR is locked or unlocked.
GS6150
Final Data Sheet
PDS-060127
LOS
8:8
RO
—
RSVD
7:0
RO
—
www.semtech.com
Rev.2
March 2015
0b: CDR is unlocked
1b: CDR is locked
Indicates whether or not the CDR has lost
the signal.
0b: Signal is present
1b: Loss of signal
Reserved.
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Table 5-1: Register Descriptions - Standard Address Space (Continued)
Address Register Name
Parameter Name
STANDBY_STICKY
11:11
SLEEP_STICKY
10:10
RETIMER_BYPASS_STICKY
LBR_HBR_STICKY
50h
Bit
Slice
9:9
8:8
R/W
ROCW
ROCW
ROCW
ROCW
Reset
Description
Value
—
Sticky bit indicating that the device entered
STANDBY mode at least once.
0b: Device has not entered STANDBY mode
since this bit was last cleared
1b: Devices has entered STANDBY mode since
this bit was last cleared
—
Sticky bit indicating that the device entered
SLEEP mode at least once
0b: Device has not entered SLEEP mode since
this bit was last cleared
1b: Device has entered SLEEP mode since this
bit was last cleared
—
Sticky bit indicating that the retimer is/has
been bypassed.
0b: Retimer has not been bypassed since this
bit was last cleared
1b: Retimer has been bypassed since this bit
was last cleared
This bit is cleared by writing any value to it.
—
Sticky bit indicating that the rate is/has been
270Mb/s (low bit-rate).
0b: Rate has not been 270Mb/s since this bit
was last cleared
1b: Rate has been 270Mb/s since this bit was
last cleared
This bit is cleared by writing any value to it.
—
Sticky bit indicating that a rate change has
occurred.
0b: Rate has not changed since this bit was last
cleared
1b: Rate has changed since this bit was last
cleared
This bit is cleared by writing any value to it.
STICKY_STATUS
RATE_CHANGE_STICKY
GS6150
Final Data Sheet
PDS-060127
7:7
ROCW
LOCK_LOST_STICKY
6:6
ROCW
—
Sticky bit indicating that lock was lost.
0b: Lock has not been lost since this bit was last
cleared
1b: Lock has been lost since this bit was last
cleared
This bit is cleared by writing any value to it.
RSVD
5:5
ROCW
—
Reserved.
LOS_STICKY
4:4
ROCW
—
Sticky bit indicating a loss of signal.
0b: Signal has not been lost since this bit was
last cleared
1b: Signal has been lost since this bit was last
cleared
This bit is cleared by writing any value to it.
RSVD
3:0
ROCW
—
Reserved.
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Table 5-2: Register Descriptions - Extended Address Space
Register
Name
Address
Parameter
Name
Bit
Slice
R/W
Reset
Value
(Dec)
RSVD
15:5
RW
4h
Description
Reserved. Do not change.
Sets the rate specific PLL loop-bandwidth
when the device is locked.
E4h
PLL_LBW_
CONTROL_
REG_0
PLL_LOOP_BANDWIDTH
4:0
RW
4h
00001b: Nominal / 4
00010b: Nominal / 2
00100b: Nominal (default)
01000b: Nominal x 2
11100b: Nominal x 4
See Table 2-3: AC Electrical Characteristics
for the PLL loop-bandwidth value set at
each rate by each of these settings.
RW = Read/Write
RO = Read Only
ROCW = Read Only/ Clear on Write
ROSW = Read Only/ Set on Write
GS6150
Final Data Sheet
PDS-060127
www.semtech.com
Rev.2
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6. Typical Application Circuit
27MHz
VCC_DDO1
*C1
*C2
10nF
10nF
VCC_DDO0
10nF
10nF
10nF
10nF
VCC
VCC_DDO1
VCC_DDO0
RSV_38
DDI0N
VCC_CORE
IN
VCC_CORE
DDI0P
VDD_DIG
1MW
IN
XTAL/CLK_IN
GND
IN
XTAL_OUT
DDI1P
XTAL_BUFF_OUT
IN
1
DDI1N
GND
IN
DDO0P
OUT
DDO0N
OUT
DDO1P
OUT
DDO1N
OUT
DDI2P
IN
DDI2N
GND
IN
DDI3P
IN
DDI3N
GS6150
RSV_40
RSV_41
IO
IO
IO
IO
GPIO0
GPIO1
IN
DDI_SEL1
IN
SDIN
GPIO2
GPIO3
RSV_37
VCO_FILT
LF+
CENTER
PAD
VEE_CORE
VEE_CORE
RSV_39
VEE_DDO
IN
CS
VEE_DDO
CLF
SCLK
VEE_DDO
IN
SDOUT
VSS_DIG
OUT
10μF
DDI_SEL0/STROBE
10nF
IN
10μF
RST
10nF
IN
1μF
LF-
Notes:
VCC IS 1.8V
VCC_DDO0 AND VCC_DDO1 ARE IN THE RANGE +1.2V TO +2.5V
XTAL IS OPTIONAL
*VALUES FOR C1 AND C2 ARE CHOSEN BASED ON THE REQUIRED LOADING FOR THE SELECTED CRYSTAL
IF AC COUPLING IS REQUIRED ON THE HIGH-SPEED SERIAL INPUTS AND OUTPUTS BY THE APPLICATION, A CERAMIC CAPACITOR 4.7μF OR HIGHER WITH A STABLE DIELECTRIC IS RECOMMENDED
Figure 6-1: GS6150 Typical Application Circuit
GS6150
Final Data Sheet
PDS-060127
www.semtech.com
Rev.2
March 2015
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7. Package and Ordering Information
7.1 Package Dimensions
A
6.00
4.65±0.15
B
0.10 M C A B
DATUM A
0.10 M C A B
DATUM B
6.00
4.65±0.15
DETAIL A
0.10 C
0.10 C
0.10 C
DATUM A OR B
+0.03
–0.02
48x
0.07 M C A B
0.05 M C
0.40/2
0.02
0.08 C
SEATING PLANE
0.90±0.10
48x
0.20±0.050
C
0.40
2x
0.20 REF
2x
0.40±0.10
DETAIL A (SCALE 3:1)
NOTES:
1. DIMENSIONS AND TOLERANCE IS IN CONFORMANCE TO ASME Y14.5–1994
2. ALL DIMENSIONS ARE IN MILLIMETERS OR IN DEGREES
Figure 7-1: Package Dimensions
GS6150
Final Data Sheet
PDS-060127
www.semtech.com
Rev.2
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7.2 Recommended PCB Footprint
0.4
0.2
0.6
5.8 4.3
CENTER PAD
4.3
Note: All dimensions
in millimeters
5.8
Figure 7-2: GS6150 PCB Footprint
7.3 Packaging Data
Table 7-1: Packaging Data
Parameter
Value
Package Type
6mm x 6mm 48-pin QFN
Moisture Sensitivity Level (Note 1)
3
Junction to Case Thermal Resistance, θj-c
26.2°C/W
Junction to Air Thermal Resistance, θj-a
21.6°C/W
Junction to Board Thermal Resistance, θj-b
4.4°C/W
Psi, Ψ
0.2°C/W
Pb-free and RoHS Compliant
Yes
Note:
1. Value per JEDEC J-STD-020C
GS6150
Final Data Sheet
PDS-060127
www.semtech.com
Rev.2
March 2015
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7.4 Marking Diagram
Pin 1 ID
GS6150
XXXXE3
YYWW
XXXX - Last 4 digits of Assembly lot
E3 - Pb-free & Green indicator
YYWW - Date Code
Figure 7-3: GS6150 Marking Diagram
7.5 Solder Reflow Profile
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 7-4: Maximum Pb-free Solder Reflow Profile
7.6 Ordering Information
Table 7-2: Ordering Information
Part Number
Package
Temperature Range
GS6150-INE3
Pb-free 48-pin QFN
-40°C to 85°C
GS6150-INTE3
GS6150-INTE3Z
GS6150
Final Data Sheet
PDS-060127
Pb-free 48-pin QFN
(250pc. tape and reel)
Pb-free 48-pin QFN
(2.5k tape and reel)
-40°C to 85°C
-40°C to 85°C
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DOCUMENT IDENTIFICATION
CAUTION
FINAL DATA SHEET
ELECTROSTATIC SENSITIVE DEVICES
The product is in production. Semtech reserves the right to make changes to the
product at any time without notice to improve reliability, function or design, in
order to provide the best product possible.
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATICFREE WORKSTATION
© Semtech 2014
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes
no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper
installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to
parameters beyond the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFESUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN
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purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and
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Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
GS6150
Final Data Sheet
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