GS7025-CQME3

GS7025 PRO-LINX™ Serial Digital Receiver Key Features • • • • • • • • • SMPTE 259M-C compliant (270Mb/s) Automatic cable equalization (typically greater than 350m of high-quality cable) Serial data outputs muted and serial clock remains active when input data is lost Operation independent of SAV/EAV sync signals Signal strength indicator output Carrier detect with programmable threshold level Power savings mode (output serial clock disable) Large IJT, typically 0.56UI beyond loop bandwidth Robust lock detect Description The GS7025 provides automatic cable equalization and high-performance clock and data recovery for serial digital signals. The GS7025 receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 35dB of gain at 135MHz, which typically results in equalization of greater than 350m of high-quality cable at 270Mb/s. The GS7025 requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. The GS7025 has dedicated pins to indicate signal strength, carrier detect, and LOCK. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS7025 provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to re-slicing. The serial clock outputs can be disabled to reduce power. The GS7025 operates from a single +5V or -5V supply. Applications Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M-C. A/D DDI DDI ANALOG DIGITAL MUX CARRIER DETECT PHASELOCK HARMONIC COSC LOCK LOGIC MUTE SDO SDI SDI + - VARIABLE GAIN EQ STAGE FREQUENCY ACQUISITION PHASE DETECTOR SDO CLK_EN SCO SCO OEM_TEST EYE MONITOR AUTO EQ CONTROL CHARGE PUMP LF+ LFS LF- + AGC CAP CD_ADJ SSI/CD VCO CBG RVCO GS7025 Functional Block Diagram GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 www.gennum.com 1 of 23 Revision History Version 7 ECR 152762 PCN − Date October 2009 Changes and/or Modifications Converted document to new format. Changed Part Numbers in 5.3 Ordering Information. Contents Key Features........................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................2 1. Pin Out...............................................................................................................................................................3 1.1 GS7025 Pin Assignment .................................................................................................................3 1.2 GS7025 Pin Descriptions ................................................................................................................4 2. Electrical Characteristics ............................................................................................................................5 2.1 Absolute Maximum Ratings ..........................................................................................................5 2.2 DC Electrical Characteristics ........................................................................................................5 2.3 AC Electrical Characteristics ........................................................................................................6 2.4 Typical Performance Curves ........................................................................................................8 3. Detailed Description.................................................................................................................................. 10 3.1 Cable Equalizer .............................................................................................................................. 10 3.1.1 Signal Strength Indication/Carrier Detect ................................................................ 10 3.1.2 Carrier Detect Threshold Adjust................................................................................... 11 3.1.3 Output Eye Monitor Test................................................................................................. 11 3.2 Reclocker .......................................................................................................................................... 12 3.2.1 Phase Locked Loop (PLL) ................................................................................................. 12 3.2.2 Frequency Acquisition..................................................................................................... 13 3.2.3 Logic Circuit ........................................................................................................................ 14 3.2.4 Locking.................................................................................................................................. 14 3.2.5 Output Data Muting.......................................................................................................... 16 3.2.6 Clock Enable........................................................................................................................ 16 3.2.7 Stressful Data Patterns..................................................................................................... 16 3.3 I/O Description ............................................................................................................................... 16 3.3.1 High Speed Analog Inputs (SDI/SDI)........................................................................... 16 3.3.2 High Speed Outputs (SDO/SDO and SCO/SCO)...................................................... 18 4. Application Information .......................................................................................................................... 19 4.1 Typical Application Circuit ........................................................................................................ 19 5. Package & Ordering Information .......................................................................................................... 20 5.1 Package Dimensions ..................................................................................................................... 20 5.2 Solder Reflow Profiles .................................................................................................................. 21 5.3 Ordering Information ................................................................................................................... 21 GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 2 of 23 1. Pin Out 1.1 GS7025 Pin Assignment OEM_TEST VCC_75 SSI/CD LOCK CLK_EN MOD COSC A/D 44 DDI DDI VCC_75 VCC VEE SDI SDI VCC VEE CD_ADJ AGC1 2 3 4 5 6 7 8 9 10 11 12 43 42 41 40 39 38 37 VEE 36 35 34 33 32 31 30 VEE SDO SDO VEE SCO SCO VEE nc nc RSV1 nc VCC VEE GS7025 TOP VIEW 29 28 27 26 25 24 23 13 14 15 16 17 18 19 20 21 22 AGC+ CBG VCC VEE Figure 1-1: GS7025 Pin Out GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 RVCO_RTN RVCO VCC LF+ LFS LF- VEE 3 of 23 1.2 GS7025 Pin Descriptions Table 1-1: GS7025 Pin Descriptions Pin Number 1, 2 3, 44 4, 8, 13, 22, 35 5, 9, 14, 18, 27, 30, 33, 34, 37 6, 7 10 11, 12 Name DDI/DDI VCC_75 VCC VEE SDI/SDI CD_ADJ AGC-, AGC+ LF+, LFS, LFRVCO_RTN RVCO CBG nc RSV1 SCO/SCO Type I I I I Description Digital data inputs (Differential ECL/PECL). Power supply connection for internal 75Ω pullup resistors connected to DDI/DDI. Most positive power supply connection. Most negative power supply connection. I I I Differential analog data inputs. Carrier detect threshold adjust. External AGC capacitor. Vcommon mode = 2.7V typ. Loop filter component connection. 15, 16, 17 I 19 20 21 23, 25, 26 24 28, 29 I I I I O RVCO Return. Frequency setting resistor return connection. Frequency setting resistor connection. Internal bandgap voltage filter capacitor. No connect - Do not connect to power or ground. Leave floating. Reserved pin 1. Always set HIGH. Serial clock output. SCO/SCO are differential current mode outputs and require external 75Ω pullup resistors. Equalized and reclocked serial digital data outputs. SDO/SDO are differential current mode outputs and require external 75Ω pullup resistors. Clock enable. When HIGH, the serial clock outputs are enabled. Timing control capacitor for internal system clock. Lock indication. When HIGH, the GS7025 is locked. LOCK is an open collector output and requires an external 10kΩ pullup resistor. Signal strength indicator/Carrier detect. Analog/Digital select. 270 Mb/s modulus select - always set HIGH. Output ‘Eye’ monitor test. Single-ended current mode output that requires an external 50Ω pullup resistor. This feature is recommended for debugging purposes only. If enabled during normal operation, the maximum operating temperature is rated to 60°C. For maximum cable length performance the OEM_TEST must be disabled. 31, 32 SDO/SDO O 36 38 39 CLK_EN COSC LOCK I I O 40 41 42 43 SSI/CD A/D MOD OEM_TEST O I I O GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 4 of 23 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage (VS) Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) Moisture Sensitivity Level Value 5.5V VCC + 0.5 to VEE - 0.5V 0°C ≤ TA ≤ 70°C -65°C ≤ TS ≤ 150°C 260°C 3 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 5.0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Condition Min Typical1 5 115 125 2.4 Max Units Note s Test Level 3 9 3 3 Supply Voltage Supply Current CLK_EN = 0 CLK_EN = 1 SDI Common Mode Voltage DDI/DDI Common Mode Input Voltage Range DDI/DDI Differential Input Drive SSI/CD Output Current HIGH, Om ΙOH = -10µA HIGH, 300m ΙOH = -10µA OEM_TEST Bias Potential A/D Input Voltage 50Ω HIGH LOW 4.75 - 5.25 - V mA mA V VEE+(VDIFF/2) 200 0.4 to 4.6 VCC-(VDIFF/2) 2000 V 2 3 800 mV 3 - 3 - V 3 - 2.1 - V 3 2.3 - 4.75 - 0.8 V V 4 3 3 GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 5 of 23 Table 2-1: DC Electrical Characteristics VCC = 5.0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Condition Min Typical1 0.25 Max Units Note s Test Level 3 RSV1, IN _ENABLE Input Voltage CLK_EN Input Voltage HIGH LOW HIGH LOW 2.0 2.5 - 0.8 0.8 0.4 V V 3 LOCK Output Low Voltage CLK_EN Source Current IOL = 500µA LOW, VIL =0V - V 3 1 26 55 µA 1 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. 7. 8. 9. NOTES: TYPICAL - measured on characterization board. VDIFF is the differential input signal swing. LOCK is an open collector output and requires an external pullup resistor. If OEM_TEST is permanently enabled, operating temperature range is limited from 0°C to 60°C inclusive. TEST LEVELS: Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. Production test at room temperature and nominal supply voltage. QA sample test. Calculated result based on Level 1,2, or 3. Not tested. Guaranteed by design simulations. Not tested. Based on characterization of nominal parts. Not tested. Based on existing design/characterization data of similar product. Indirect test. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Condition Min Typical1 270 (only) 35 Max Units Note s Test Level 3 6 Serial Data Rate Maximum Equalizer Gain (see Figure 3) Additive Jitter [Pseudorandom (2 Intrinsic Jitter [Pseudorandom (2 Intrinsic Jitter [Pathological (SDI checkfield)] 23 23 SDI @ 135MHz - - Mb/s dB -1)] 270Mb/s, 300m (Belden 8281) 270Mb/s - 300 - ps p-p 2, 7 9 - 185 - ps p-p 2, 6 4 -1)] 270Mb/s 462 ps p-p 2, 6 3 GS7025 PRO-LINX™ Serial Digital Receiver Data Sheet 13813 - 7 October 2009 6 of 23 Table 2-2: AC Electrical Characteristics VCC = 5.0V, VEE = 0V, TA = 0° – 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF Parameter Condition Min Typical1 0.56 1 Max Units Note s 3, 6 4 Test Level 9 7 Input Jitter Tolerance Lock Time Synchronous Switch 270Mb/s tswitch < 0.5µs, 270Mb/s 0.5µs< tswitch 10 ms 0.40 - - UI p-p µs - 1 - ms 0.5 -200 4 1 0 2 200 ms µs ps 5 7 7 SDO Mute Time SDO to SCO Synchronization SDO, SCO Output Signal Swing SDO, SCO Rise & Fall Times SDI/SDI Input Resistance SDI/SDI Input Capacitance Carrier Detect Response Time Carrier Applied 75Ω DC load 600 800 1000 mV p-p ps kΩ pF µs 1 20%-80% 200 300 400 7 - 10 1.0 3 - 7 7 7, 8 6 6 6 Carrier Removed - 30 - 1. 2. 3. 4. 5. 6. 7. 8. 1. 2. 3. 4. 5. 6. 7. 8. 9. NOTES: TYPICAL - measured on characterization board. Characterized 6 sigma RMS. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component NTSC). Carrier Loss Time refers to the response of the SDO output from valid re-clocked input data to mute mode when the input signal is removed. Using the DDI input, A/D=0. Using the SDI input, A/D=1. Carrier Detect Response Time refers to the response of the SSI/CD output from a logic high to a logic low state when the input signal is removed or amplitude drops below the threshold set by the CD_ADJ pin. SSI/CD pin loading CL