GS9024-CKBE3

GS9024 GENLINX™ Automatic Cable Equalizer GS9024 Data Sheet Features • • • • • • • • • • • • automatic cable equalization fully compatible with SMPTE 259M typically equalizes greater than 350m of high quality cable at 270Mb/s signal strength indicator output data muting when input data is lost output 'eye' monitor (OEM) with large signal amplitude and power down option low power: 240mW at 5V 14 pin SOIC package programmable output data squelch for max cable length limiting carrier detect with programmable threshold level serial data output "High Z" select to allow muxing of EQ inputs Pb-free and Green Description The GS9024 is a high performance automatic cable equalizer designed for serial digital data rates from 143Mb/s to 540Mb/s. The GS9024 receives either single-ended or differential serial data and outputs equalized differential signals at PECL levels (800mV). The GS9024 provides up to 40dB of gain at 200MHz which will typically result in equalization of greater than 350m at 270Mb/s of Belden 8281 cable. The GS9024 incorporates an analog signal strength indicator/carrier detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. The GS9024 also features selectable High Z serial data outputs eliminating the need for input muxing circuitry in routers. In addition, the GS9024 provides an 'Output Eye Monitor' (OEM) which allows the verification of signal integrity after equalization, prior to reslicing. The GS9024 operates from a single +5V or -5V power supply and consumes only 240mW of power. Packaged in a small 14 pin SOIC, the GS9024 is ideal for router applications where high density component placement is required. Applications Front-end cable equalization for digital video systems; Input equalization for serial digital distribution amplifiers, routers, production switchers and other receiving equipment. SDI + - VARIABLE GAIN EQ STAGE + + - SDO SDO HIGH Z SDI OEM EYE MONITOR AUTO EQ CONTROL SSI/CD + AGC CD_ADJ Block diagram 521-70-10 February 2005 1 of 16 www.gennum.com GS9024 Data Sheet Contents 1. Electrical Characteristics ...........................................................................................3 1.1 DC Electrical Characteristics ..........................................................................3 1.2 AC Electrical Characteristics ...........................................................................4 2. Test Setup................................................................................................................5 3. Pin Connections ........................................................................................................6 4. Typical Performance Curves .....................................................................................7 5. Detailed Description ................................................................................................11 5.1 Output HIGH Z ..............................................................................................11 5.2 Signal Strength Indication/Carrier Detect ......................................................11 5.3 Carrier Detect Threshold Adjust ....................................................................12 5.4 Output Eye Monitor .......................................................................................12 5.5 I/O Description ..............................................................................................13 5.5.1 High Speed Analog Inputs (SDI/SDI)...................................................13 5.5.2 High Speed Outputs (SDO/SDO) ........................................................13 6. Applications Information..........................................................................................14 7. Typical Application Circuit .......................................................................................14 8. Package Dimensions ..............................................................................................15 9. Ordering Information ...............................................................................................15 10. Revision History ....................................................................................................16 521-70-10 February 2005 2 of 16 GS9024 Data Sheet 1. Electrical Characteristics Table 1-1: Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) Value 5.5V VCC +0.5 to VEE -0.5V 0°C ≤ TA ≤ 70°C -65°C ≤ TS ≤ 150°C 260°C 1.1 DC Electrical Characteristics Table 1-2: DC Electrical Characteristics VCC = 5V, VEE = 0V, TA = 0°C TO 70°C unless otherwise shown. Parameter Supply Voltage Power Consumption Symbol VCC PD – – Conditions Min 4.75 – – – – – – – – – – – 2.4 – NOTES Typ1 5.0 240 340 44 58 11 2.5 2.7 4.5 – – 1.0 – – Max 5.25 – – – – – – – – 18 110 1.5 – 0.8 Units V mW mW mA mA mA V V V µA µA mA V V Notes Test Level 3 3 1 1 3 1 1 1 with OEM active Supply Current ΙS – with OEM active Serial Data O/P Current SDI/SDI Common Mode Voltage AGC+/AGC- Mode Voltage OEM Bias Potential SSI/CD Output Current ΙSDO – – – ΙSOURCE RL = 75Ω – – – CLMAX = 50pF RL = ∞ CLMAX = 50pF RL = 5kΩ ISINK High Z Input Voltage VHIGH VLOW TEST LEVELS 1. 100% tested at 25°C. 2. Guaranteed by design. 3. Inferred or co-related value. – – – 1 1 1. Typical values are parametric norms at 25°C. 521-70-10 February 2005 3 of 16 GS9024 Data Sheet 1.2 AC Electrical Characteristics Table 1-3: AC Electrical Characteristics VCC = 5V, VEE = 0V, TA = 0°C TO 70°C unless otherwise shown. Parameter Data Rate Output Signal Swing Additive Jitter Symb ol Conditions Min 143 Typ1 – 850 275 200 0.65 30 10 1.0 3 Max 540 1000 – – – – – – – Units Mb/s mV ps p-p ps p-p ns ps kΩ pF µs Notes Test Level 1 1 VSDO RL = 75Ω 270Mb/s, 300m 540Mb/s, 100m 700 – – 0.5 – – – – tJ see Fig 5 see Fig 5 5 5 3 2 2 2 2 Output Rise and Fall Times (20-80%) Output Duty Cycle Distortion Input Resistance Input Capacitance Carrier Detect Response Time tr, tf – RIN CIN – – SDI, SDI SDI, SDI Carrier Applied RL = ∞, CL ≤ 50pF on SSI/CD Carrier Removed RL = ∞, CL ≤ 50pF on SSI/CD – at 270MHz tCDON tCDOFF – 30 – µs 2 High Z Response Time Input Return Loss Maximum Equalizer Gain TEST LEVELS 1. 2. 3. 4. 5. trHIGHZ – 15 – NOTES 17 20 40 – – – ns dB dB see Fig 8 see Fig 4 2 3 3, 5 AEQ at 200MHz 100% tested at 25°C. Guaranteed by design. Inferred or co-related value. Evaluated using test setup Figure 2-1. Evaluated using test setup Figure 2-2. 1. Typical values are parametric norms at 25°C. 521-70-10 February 2005 4 of 16 GS9024 Data Sheet 2. Test Setup DATA TEKTRONIX GigaBERT 700 TRANSMITTER DATA GS9028 CABLE DRIVER BELDEN 8281 CABLE EB9024 BOARD TEKTRONIX GigaBERT 700 ANALYZER TRIGGER CLOCK Figure 2-1: Test Setup for Figure 4-1. DATA ANRITSU DATA ME522A or GigaBERT 700 TRANSMITTER CLOCK GS9028 CABLE DRIVER BELDEN 8281 CABLE EB9024 BOARD VERTICAL IN SSI/CD V V CD_ADJ OSCILLOSCOPE TRIGGER IN Figure 2-2: Test Setup for Figure 4-2, Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-8, and Figure . 521-70-10 February 2005 5 of 16 GS9024 Data Sheet 3. Pin Connections AGCVEE VCC SDI SDI VEE VCC 1 2 3 4 14 13 12 AGC+ HIGH Z SSI/CD SDO SDO CD_ADJ OEM GS9024 11 TOP VIEW 5 10 6 7 9 8 Table 3-1: Pin Descriptions Number 1, 14 4, 5 8 9 10, 11 12 13 Symbol AGC-, AGC+ SDI/SDI OEM CD_ADJ SDO/SDO SSI/CD HIGH Z Type I I O I O O I Description External AGC capacitor. Differential serial digital data inputs. Output ‘Eye’ monitor. OEM is a single ended current mode output and requires an external 50Ω pullup resistor. Carrier detect threshold adjust. Equalized serial digital data outputs. Signal strength indicator/Carrier Detect. The SDO/SDO outputs are High Z when this pin is HIGH. If High Z functionality is not used, this input can be left floating or tied LOW. 521-70-10 February 2005 6 of 16 GS9024 Data Sheet 4. Typical Performance Curves (VS = 5V, TA = 25°C unless otherwise shown.) 500 0.5 UI Output Additive Jitter 400 CABLE LENGTH (m) 300 0.2 UI Output Additive Jitter 200 100 0 90 180 270 360 450 540 630 DATA RATE (Mb/s) Figure 4-1: Maximum Data Rate vs. Cable Length - Belden 8281n (see Test Setup in Figure 2-1) 50 45 40 35 30 GAIN (dB) 25 20 15 10 5 0 1 10 100 1000 FREQUENCY (MHz) Figure 4-2: Equalizer Gain vs. Frequency 521-70-10 February 2005 7 of 16 GS9024 Data Sheet 1500 1400 1200 ADDITIVE JITTER (ps p-p) 1000 800 600 540Mb/s 400 200 270Mb/s 0 0 50 100 150 200 250 300 350 CABLE LENGTH (m) Figure 4-3: Additive Jitter vs. Input Cable Length — Belden 8281 5.00 4.50 SSI/CD OUTPUT VOLTAGE (V) 4.00 3.50 3.00 2.50 0 50 100 150 200 250 300 350 400 450 500 CABLE LENGTH (m) Figure 4-4: SSI/CD Voltage vs. Cable Length — Belden 8281 (CD_ADJ = 0V) 5.0 4.5 CD_ADJ VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 200 250 300 350 400 CABLE LENGTH (m) Figure 4-5: Carrier Detect Adjust Voltage Threshold Characteristics 521-70-10 February 2005 8 of 16 GS9024 Data Sheet j1 j0.5 j2 j0.2 j5 3000 -j0.2 1620 810 -j0.5 -j1 -j2 720 -j5 Frequencies in MHz, impedances normalized to 50Ω. Figure 4-6: Input Impedance Figure 4-7: Output Data Waveform at 270Mb/s, 300m 521-70-10 February 2005 9 of 16 GS9024 Data Sheet Figure 4-8: Output Data Waveform at 540Mb/s, 200m 521-70-10 February 2005 10 of 16 GS9024 Data Sheet 5. Detailed Description The GS9024 Automatic Cable Equalizer is a bipolar integrated circuit designed to equalize serial digital data signals between 30Mbps and 622Mbps. Powered from a single +5V or -5V supply, the device consumes approximately 240mW of power. The serial data signal is connected to the input pins (SDI/SDI) either differentially or single ended. The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 40dB of gain at 200MHz which will typically result in equalization of greater than 350m at 270Mb/s of Belden 8281 cable. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is DC restored, thereby restoring its logic threshold to its corrective level regardless of shifts due to AC coupling. The digital output signals have PECL voltage levels (800mV) and are available at pins SDO and SDO. 5.1 Output HIGH Z A HIGH Z pin allows the data outputs to be put into a high impedance state which disconnects them from the output traces. This feature is ideal for input expansion in router applications as it eliminates the need for input muxes or crosspoints. NOTE: The high impedance feature will only take effect if the device outputs are not muted. 5.2 Signal Strength Indication/Carrier Detect The GS9024 incorporates an analog signal strength indicator/carrier detect output (SSI/CD) which indicates both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figure . With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length. 521-70-10 February 2005 11 of 16 GS9024 Data Sheet When the signal strength decreases to the level set at the "Carrier Detect Threshold Adjust" pin, the SSI/CD voltage goes to a logic "0" state (0.8V) and can be used to drive other TTL/CMOS compatible logic inputs. In addition, when loss of carrier is detected the SDO/SDO outputs are muted (set to a known static state). 5 SSI/CD OUTPUT VOLTAGE (V) 4 3 CD_ADJ CONTROL RANGE 2 1 0 0 50 100 150 200 250 300 350 400 450 500 CABLE LENGTH (m) 5.3 Carrier Detect Threshold Adjust The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin. The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit. The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. Connecting this pin to Ground disables the SDO/SDO muting function and allows for maximum possible cable length equalization. This feature is designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. This problem is not solved by using a Carrier Detect function with a fixed internal reference because the signal to noise ratio on the circuit board may be significantly less than the default signal detection level set by the on- chip reference. To solve this problem, the GS9024 provides a user adjustable threshold to meet the unique conditions that exist in each user's application. Override and internal default settings are provided to give the user total flexibility. 5.4 Output Eye Monitor The GS9024 provides an 'Output Eye Monitor' (OEM) which allows the verification of signal integrity after equalization, prior to reslicing. The OEM pin is an open collector current output that requires an external 50Ω pullup resistor. When the pullup resistor is not used, the OEM block is disabled and the internal OEM circuit is powered down. The OEM provides a 0.25Vp-p signal when driving a 50Ω oscilloscope input. 521-70-10 February 2005 12 of 16 GS9024 Data Sheet 5.5 I/O Description 5.5.1 High Speed Analog Inputs (SDI/SDI) SDI/SDI are high impedance inputs which accept differential or single-ended input drive. Figure shows the recommended interface when a single-ended serial digital signal is used. 10nF 75Ω 75Ω 10nF SDI 37.5Ω 75Ω SDI GS9024 5.5.2 High Speed Outputs (SDO/SDO) SDO/SDO are current mode outputs that require external pullups (see Figure ). The output signal swings are 800mV when 75Ω resistors are used. A diode can be placed between VCC and the pullups to shift the signal levels down by approximately 0.7 volts. When the output traces are longer than 1 inch, controlled impedance traces should be used. The pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75Ω). VCC 75Ω GS9024 SDO SDO 75Ω 521-70-10 February 2005 13 of 16 GS9024 Data Sheet 6. Applications Information The Typical Application Circuit shown on page 14 is useful for both SMPTE and DVB-ASI signals. The two AGC capacitors shown however increase the AGC time constant from the original times shown in earlier SMPTE-only application circuits. In this case a minimum off-time of 50ms is needed when break-before-make switching is used at the input in order for the AGC voltage to recover. 7. Typical Application Circuit 100n 100n VCC 1 AGC2 3 SDI INPUT 30 - 622Mb/s 75 37.5 75 75 10n VCC 10n 4 5 SDI 6 7 VEE VCC SDO 9 CD_ADJ OEM 8 VEE VCC SDI GS9024 HIGH Z 12 SSI/CD SDO 11 10 AGC+ 13 14 VCC VCC 75 75 DATA OUT DATA OUT VCC 100k POT (optional) All resistors in ohms, all capacitors in farads, unless otherwise shown. 50 1n EYE MONITOR OUTPUT 521-70-10 February 2005 14 of 16 GS9024 Data Sheet 8. Package Dimensions All dimensions in millimeters. 8.75 MAX 0.49 MAX 1.91 MAX 1.27 MAX 14 8 4.0 MAX 6.20 MAX 0.25 MAX 1 7 0.25 MAX O.56 MAX = = = = = = 7.62 ±0.05 6 spaces@ 1.27±0.05 9. Ordering Information Part Number GS9024-CKB GS9024-CTB GS9024-CKBE3 GS9024-CTBE3 Package 14 pin SOIC 14 pin SOIC Tape 14 pin SOIC 14 pin SOIC Tape Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Pb-Free and Green No No Yes Yes 521-70-10 February 2005 15 of 16 GS9024 Data Sheet 10. Revision History Version 10 ECR 135403 Date February 2005 Changes Added note to clarify that the High Impedance feature is available only when the device outputs are not muted. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 1996 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 521-70-10 February 2005 16 16 of 16