GS9024C-CKB

G S9024C *(1/,1; ™,, GS9024C Automatic Cable Equalizer PRELIMINARY DATA SHEET FEATURES • automatic cable equalization • fully compatible with SMPTE 259M • typically equalizes greater than 350m of high quality cable at 270Mb/s • signal strength indicator • output data muting when input data is lost • output 'eye' monitor (OEM) with large signal amplitude and power down option • low power: 240mW at 5V • 14 pin SOIC package • programmable output data squelch for max cable length limiting • carrier detect with programmable threshold level • serial data output "High Z" select to allow muxing of EQ inputs APPLICATIONS Front-end cable equalization for digital video systems; Input equalization for serial digital distribution amplifiers, routers, production switchers and other receiving equipment. DESCRIPTION The GS9024C is a high performance automatic cable equalizer designed for serial digital data rates from 143Mb/s to 360Mb/s. The GS9024C receives either single-ended or differential serial data and outputs equalized differential signals at PECL levels (800mV). The GS9024C provides up to 40dB of gain at 200MHz which will typically result in equalization of greater than 350m at 270Mb/s of Belden 8281 cable. The GS9024C incorporates an analog signal strength indicator/carrier detect (SSI/CD) output indicating both the presence of a carrier and the amount of equalization applied to the signal. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. The GS9024C also features selectable High Z serial data outputs eliminating the need for input muxing circuitry in routers. In addition, the GS9024C provides an 'Output Eye Monitor' (OEM) which allows the verification of signal integrity after equalization, prior to reslicing. The GS9024C operates from a single +5V or -5V power supply and consumes only 240mW of power. Packaged in a small 14 pin SOIC, the GS9024C is ideal for router applications where high density component placement is required. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE GS9024C GS9024C-CKB GS9024C-CTB 14 pin SOIC 14 pin SOIC Tape 0°C to 70°C 0°C to 70°C SDI + - VARIABLE GAIN EQ STAGE + + - SDO SDO HIGH Z SDI OEM EYE MONITOR AUTO EQ CONTROL SSI/CD + AGC CD_ADJ BLOCK DIAGRAM Revision Date: October 2001 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 20581 - 0 ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) 5.5V VCC +0.5 to VEE -0.5V 0°C ≤ TA ≤ 70°C GS9024C -65°C ≤ TS ≤ 150°C 260°C DC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0°C TO 70°C unless otherwise shown. PARAMETER SYMBOL CONDITIONS MIN TYP1 MAX UNITS NOTES TEST LEVEL Supply Voltage Power Consumption VCC PD with OEM active 4.75 with OEM active - 5.0 240 340 44 58 11 2.5 5.25 - V mW mW mA mA mA V 3 3 1 1 3 1 Supply Current ΙS Serial Data O/P Current SDI/SDI Common Mode Voltage AGC+/AGC- Mode Voltage OEM Bias Potential SSI/CD Output Current ΙSDO RL = 75Ω - 2.7 - V 1 ΙSOURCE 4.5 1.0 - 18 110 1.5 0.8 V µA µA mA V V 1 CLMAX = 50pF RL = ∞ CLMAX = 50pF RL = 5kΩ 2.4 - ΙSINK High Z Input Voltage VHIGH VLOW 1 1 TEST LEVELS 1. 100% tested at 25°C. 2. Guaranteed by design. 3. Inferred or co-related value. NOTES 1. Typical values are parametric norms at 25°C. 2 GENNUM CORPORATION 20581 - 0 AC ELECTRICAL CHARACTERISTICS VCC = 5V, VEE = 0V, TA = 0°C TO 70°C unless otherwise shown. PARAMETER SYMBOL CONDITIONS MIN TYP1 MAX UNITS NOTES TEST LEVEL Data Rate Output Signal Swing Additive Jitter VSDO RL = 75Ω 270Mb/s, 300m 143 700 - 850 275 360 1000 - Mb/s mV ps p-p see Fig 5 1 1 GS9024C tJ tr, tf 5 Output Rise and Fall Times (20-80%) Output Duty Cycle Distortion Input Resistance Input Capacitance Carrier Detect Response Time 0.5 0.65 - ns 3 - 30 - ps kΩ pF µs 2 RIN CIN SDI, SDI SDI, SDI Carrier Applied RL = ∞, CL ≤ 50pF on SSI/CD Carrier Removed RL = CL ≤ 50pF on SSI/CD - 10 1.0 3 - 2 2 2 tCDON tCDOFF ∞, - 30 - µs 2 High Z Response Time Input Return Loss Maximum Equalizer Gain trHIGHZ at 270MHz AEQ at 200MHz 15 - 17 20 40 - ns dB dB see Fig 8 see Fig 4 2 3 3, 5 TEST LEVELS 1. 100% tested at 25°C. 2. Guaranteed by design. 3. Inferred or co-related value. 4. Evaluated using test setup Figure 1. 5. Evaluated using test setup Figure 2. NOTES 1. Typical values are parametric norms at 25°C. TEST TEST SETUP DATA TEKTRONIX GigaBERT 700 TRANSMITTER DATA GS9028 CABLE DRIVER BELDEN 8281 CABLE EB9024 BOARD TEKTRONIX GigaBERT 700 ANALYZER TRIGGER CLOCK Fig. 1 Test Setup for Figure 3. BELDEN 8281 CABLE GS9028 CABLE DRIVER EB9024 BOARD VERTICAL IN DATA ANRITSU DATA ME522A or GigaBERT 700 TRANSMITTER CLOCK SSI/CD V V CD_ADJ OSCILLOSCOPE TRIGGER IN Fig. 2 Test Setup for Figures 4, 5, 6, 7 and 10. 3 GENNUM CORPORATION 20581 - 0 PIN CONNECTIONS AGCVEE VCC SDI SDI VEE VCC 1 2 3 14 13 12 AGC+ HIGH Z SSI/CD SDO 4 GS9024C 11 TOP VIEW 5 10 6 7 9 8 GS9024C SDO CD_ADJ OEM PIN DESCRIPTIONS NUMBER SYMBOL TYPE DESCRIPTION 1, 14 4, 5 8 AGC-, AGC+ SDI/SDI OEM I I O External AGC capacitor. Differential serial digital data inputs. Output ‘Eye’ monitor. OEM is a single ended current mode output and requires an external 50Ω pullup resistor. Carrier detect threshold adjust. Equalized serial digital data outputs. Signal strength indicator/Carrier Detect. The SDO/SDO outputs are High Z when this pin is HIGH. If High Z functionality is not used, this input can be left floating or tied LOW. 9 10, 11 12 13 CD_ADJ SDO/SDO SSI/CD HIGH Z I O O I 4 GENNUM CORPORATION 20581 - 0 TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown.) 500 0.5 UI Output Additive Jitter 5.00 400 4.50 SSI/CD OUTPUT VOLTAGE (V) CABLE LENGTH (m) 300 0.2 UI Output Additive Jitter 4.00 GS9024C 200 3.50 100 3.00 0 2.50 0 50 100 150 200 250 300 350 400 450 500 DATA RATE (Mb/s) CABLE LENGTH (m) Fig. 3 Maximum Data Rate vs. Cable Length - Belden 8281n (see Test Setup in Figure 1) 50 45 40 35 30 Fig. 6 SSI/CD Voltage vs. Cable Length - Belden 8281 (CD_ADJ = 0V) 5.0 4.5 CD_ADJ VOLTAGE (V) 4.0 GAIN (dB) 25 20 15 10 5 0 1 10 100 1000 3.5 3.0 2.5 2.0 200 250 300 350 400 FREQUENCY (MHz) CABLE LENGTH (m) Fig. 4 Equalizer Gain vs. Frequency Fig. 7 Carrier Detect Adjust Voltage Threshold Characteristics j1 600 j0.5 j2 ADDITIVE JITTER (ps p-p) 400 j0.2 j5 200 270Mb/s 3000 -j0.2 1620 810 720 -j5 0 0 50 100 150 200 250 300 350 CABLE LENGTH (m) -j0.5 -j1 -j2 Fig. 5 Additive Jitter vs. Input Cable Length - Belden 8281 Frequencies in MHz, impedances normalized to 50Ω. Fig. 8 Input Impedance 5 GENNUM CORPORATION 20581 - 0 1. OUTPUT HIGH Z A HIGH Z pin allows the data outputs to be put into a high impedance state which disconnects them from the output traces. This feature is ideal for input expansion in router applications as it eliminates the need for input muxes or crosspoints. 2. SIGNAL STRENGTH INDICATION/CARRIER DETECT GS9024C The GS9024C incorporates an analog signal strength indicator/carrier detect output (SSI/CD) which indicates both the presence of a carrier and the amount of equalization applied to the signal. The voltage output of this pin versus cable length (signal strength) is shown in Figure 10. With 0m of cable (800mV input signal levels), the SSI/CD output voltage is approximately 4.5V. As the cable length increases, the SSI/CD voltage decreases linearly providing accurate correlation between the SSI/CD voltage and cable length. Fig. 9 Output Data Waveform at 270Mb/s, 300m DETAILED DESCRIPTION The GS9024C Automatic Cable Equalizer is a bipolar integrated circuit designed to equalize serial digital data signals between 30Mbps and 360Mbps. Powered from a single +5V or -5V supply, the device consumes approximately 240mW of power. The serial data signal is connected to the input pins (SDI/SDI) either differentially or single ended. The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The gain stage provides up to 40dB of gain at 200MHz which will typically result in equalization of greater than 350m at 270Mb/s of Belden 8281 cable. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by an external differential AGC filter capacitor (AGC+/AGC-) providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is DC restored, thereby restoring its logic threshold to its corrective level regardless of shifts due to AC coupling. The digital output signals have PECL voltage levels (800mV) and are available at pins SDO and SDO. 6 GENNUM CORPORATION When the signal strength decreases to the level set at the "Carrier Detect Threshold Adjust" pin, the SSI/CD voltage goes to a logic "0" state (0.8V) and can be used to drive other TTL/CMOS compatible logic inputs. In addition, when loss of carrier is detected the SDO/SDO outputs are muted (set to a known static state). 5 SSI/CD OUTPUT VOLTAGE (V) 4 3 CD_ADJ CONTROL RANGE 2 1 0 0 50 100 150 200 250 300 350 400 450 500 CABLE LENGTH (m) Fig. 10 3. CARRIER DETECT THRESHOLD ADJUST The threshold level at which loss of carrier is detected is adjustable via external resistors at the CD_ADJ pin. The control voltage at the CD_ADJ pin is set by a simple resistor divider circuit. The threshold level is adjustable from 200m to 350m. By default (no external resistors), the threshold is typically 320m. Connecting this pin to Ground disables the SDO/SDO muting function and allows for maximum possible cable length equalization. This feature is designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. This problem is not solved by using a 20581 - 0 Carrier Detect function with a fixed internal reference because the signal to noise ratio on the circuit board may be significantly less than the default signal detection level set by the on- chip reference. To solve this problem, the GS9024C provides a user adjustable threshold to meet the unique conditions that exist in each user's application. Override and internal default settings are provided to give the user total flexibility. 4. OUTPUT EYE MONITOR 5.2. High Speed Outputs (SDO/SDO) SDO/SDO are current mode outputs that require external pullups (see Figure 12). The output signal swings are 800mV when 75Ω resistors are used. A diode can be placed between VCC and the pullups to shift the signal levels down by approximately 0.7 volts. When the output traces are longer than 1 inch, controlled impedance traces should be used. The pullup resistors should be placed at the end of the output traces as they terminate the trace in its characteristic impedance (75Ω). GS9024C The GS9024C provides an 'Output Eye Monitor' (OEM) which allows the verification of signal integrity after equalization, prior to reslicing. The OEM pin is an open collector current output that requires an external 50Ω pullup resistor. When the pullup resistor is not used, the OEM block is disabled and the internal OEM circuit is powered down. The OEM provides a 0.25Vp-p signal when driving a 50Ω oscilloscope input. 5. I/O DESCRIPTION 5.1. High Speed Analog Inputs (SDI/SDI) GS9024C SDO SDO VCC 75Ω 75Ω Fig. 12 SDI/SDI are high impedance inputs differential or single-ended input drive. which accept Figure 11 shows the recommended interface when a singleended serial digital signal is used. 10nF 75Ω 75Ω 10nF SDI 37.5Ω 75Ω SDI GS9024C APPLICATIONS INFORMATION The Typical Application Circuit shown on page 8 is useful for both SMPTE and DVB-ASI signals. The two AGC capacitors shown however increase the AGC time constant from the original times shown in earlier SMPTE-only application circuits. In this case a minimum off-time of 50ms is needed when break-before-make switching is used at the input in order for the AGC voltage to recover. Fig. 11 7 GENNUM CORPORATION 20581 - 0 TYPICAL APPLICATION CIRCUIT 100n 100n VCC 1 AGC2 3 SDI INPUT 30 - 360Mb/s 75 37.5 75 75 10n VCC 10n 4 5 SDI 6 7 VEE VCC SDO 9 CD_ADJ OEM 8 VEE VCC SDI HIGH Z 12 SSI/CD GS9024C SDO 11 10 AGC+ 13 14 VCC VCC 75 75 DATA OUT DATA OUT VCC 100k POT (optional) GS9024C All resistors in ohms, all capacitors in farads, unless otherwise shown. 50 1n EYE MONITOR OUTPUT PACKAGE DIMENSIONS All dimensions in millimeters. 8.75 MAX 0.49 MAX 1.91 MAX 1.27 MAX 14 8 4.0 MAX 6.20 MAX 0.25 MAX 1 7 0.25 MAX O.56 MAX = = = = = = 7.62 ±0.05 6 spaces@ 1.27±0.05 16 Pin SOIC Narrow CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice. REVISION NOTES: New Document For latest product information, visit www.gennum.com GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright October 2001 Gennum Corporation. All rights reserved. Printed in Canada. 8 20581 - 0