GS9025ACQME3

GENLINX ™II GS9025A Serial Digital Receiver DATA SHEET FEATURES • SMPTE 259M compliant • operational to 540Mb/s • automatic cable equalization (typically greater than 350m of high quality cable at 270Mb/s) • adjustment-free operation • auto-rate selection (5 rates) with manual override • single external VCO resistor for operation with five input data rates • data rate indication output • serial data outputs muted and serial clock remains active when input data is lost • operation independent of SAV/EAV sync signals • signal strength indicator output • carrier detect with programmable threshold level • power savings mode (output serial clock disable) • Pb-free and Green APPLICATIONS Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M and other data standards. ORDERING INFORMATION PART NUMBER GS9025ACQM GS9025ACTM GS9025ACQME3 GS9025ACTME3 PACKAGE 44 pin MQFP Tray 44 pin MQFP Tape 44 pin MQFP Tray 44 pin MQFP Tape TEMPERATURE 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Pb-FREE AND GREEN No No Yes Yes DESCRIPTION The GS9025A provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS9025A receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 40dB of gain at 200MHz which typically results in equalization of greater than 350m of high quality cable at 270Mb/s. The GS9025A operates in either auto or manual data rate selection mode. In both modes, the GS9025A requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. The GS9025A has dedicated pins to indicate signal strength/carrier detect, LOCK and data rate. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS9025A provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to reslicing. The serial clock outputs can also be disabled to reduce power. The GS9025A operates from a single +5 or -5 volt supply. GS9025A A/D DDI DDI ANALOG DIGITAL MUX CARRIER DETECT PHASELOCK HARMONIC COSC LOCK LOGIC MUTE SDO SDI SDI + - VARIABLE GAIN EQ STAGE FREQUENCY ACQUISITION PHASE DETECTOR SDO CLK_EN SCO SCO OEM_TEST EYE MONITOR DIVISION AUTO EQ CONTROL CHARGE PUMP 3 BIT COUNTER SMPTE AUTO/MAN SS0 SS1 SS2 + AGC CAP CD_ADJ SSI/CD VCO DECODER LF+ LFS LF- CBG RVCO BLOCK DIAGRAM Revision Date: August 2005 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 75 - 05 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage (VS) Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE 5.5V VCC + 0.5 to VEE - 0.5V 0°C ≤ TA ≤ 70°C GS9025A -65°C ≤ TS ≤ 150°C 260°C DC ELECTRICAL CHARACTERISTICS VCC = 5.0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER Supply Voltage Supply Current CONDITION MIN 4.75 TYPICAL1 5 115 125 2.4 0.4 to 4.6 MAX 5.25 UNITS V mA mA NOTES TEST LEVEL 3 9 3 3 CLK_EN = 0 CLK_EN = 1 VEE+(VDIFF/2) 200 SDI Common Mode Voltage DDI Common Mode Input Voltage Range DDI Differential Input Drive SSI/CD Output Current HIGH, 100m, 143Mb/s, ΙOH=-10µA HIGH, 300m, 143Mb/s, ΙOH=-10µA LOW, ΙOL=1mA OEM_TEST Bias Potential A/D RL=50Ω High Low AUTO/MAN, SMPTE, SS[2:0] Input Voltage CLK_EN Input Voltage High Low High Low LOCK Output Low Voltage SS[2:0] Output Voltage ΙOL=500µA HIGH, ΙOH=-180µA, Auto Mode LOW, ΙOL=600µA, Auto Mode VCC-(VDIFF/2) 2000 - V V 2 3 800 4.2 mV V 3 3 - - 3.7 - 2.3 2.0 2.5 4.4 0.4 4.75 0.25 4.8 0.8 0.8 0.8 0.8 0.4 - V V V 5 1 3 3 V 3 V 3 V V 3 1 1 - 0.3 0.4 2 of 18 GENNUM CORPORATION 522 - 75 - 05 DC ELECTRICAL CHARACTERISTICS (Continued) VCC = 5.0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER SS[2:0] Input Voltage CONDITION HIGH, Manual Mode LOW, Manual Mode MIN 2 - TYPICAL 26 1 MAX 0.8 UNITS V NOTES TEST LEVEL 3 GS9025A CLK_EN Source Current NOTES Low, VIL = 0V 55 µA 1 TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 1. TYPICAL - measured on EB9025A board. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pull-up resistor. 4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode. 5. If OEM_TEST is permanently enabled, operating temperature range is limited from 0°C to 60°C inclusive. AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER Serial Data Rate Maximum Equalizer Gain Additive Jitter [Pseudorandom (2 23 CONDITIONS SDI @ 200MHz 270Mb/s, 300m (Belden 8281) 540Mb/s, 100m (Belden 8281) MIN 143 - TYPICAL 40 300 1 MAX 540 - UNITS Mb/s dB ps p-p NOTES TEST LEVEL 3 6 2, 8 9 -1)] - 275 - Intrinsic Jitter [Pseudorandom (2 Intrinsic Jitter [Pathological (SDI checkfield)] 23 270Mb/s -1)] 540Mb/s 270Mb/s 360Mb/s 540Mb/s 0.40 0.32 - 185 164 462 308 260 0.56 0.43 1 1 4 10 see Figure 12 ps p-p 2, 7 4 see Figure 13 ps p-p 2, 7 3 Input Jitter Tolerance 270Mb/s 540Mb/s - UI p-p 3, 7 9 Lock Time Synchronous Switch tswitch < 0.5µs, 270Mb/s 0.5µs< tswitch 10 ms µs ms ms ms 4 7 Lock Time Asynchronous Switch Loop Bandwidth = 6MHz @ 540Mb/s 5 7 3 of 18 GENNUM CORPORATION 522 - 75 - 05 AC ELECTRICAL CHARACTERISTICS (Continued) VCC = 5.0V, VEE = 0V, TA = 0° to 70°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER SDO Mute Time SDO to SCO Synchronization SDO, SCO Output Signal Swing SDO, SCO Rise & Fall times SDI/SDI Input Resistance SDI/SDI Input Capacitance Carrier Detect Response Time CONDITIONS MIN 0.5 -200 TYPICAL 1 0 800 1 MAX 2 200 1000 UNITS µs ps mV p-p NOTES 6 TEST LEVEL 7 7 GS9025A 75Ω DC load 600 1 20%-80% 200 - 300 10 1.0 3 400 - ps kΩ pF µs 8 8 8, 9 7 6 6 6 Carrier Applied, - Carrier Removed, - 30 - NOTES 1. TYPICAL - measured on CB9025A board. 2. Characterized 6 sigma rms. 3. IJT measured with sinusoidal modulation beyond Loop Bandwidth (at 6.5MHz). 4. Synchronous switching refers to switching the input data from one source to another source which is at the same data rate (ie. line 10 switching for component NTSC). 5. Asynchronous switching refers to switching the input data from one source to another source which is at a different data rate. 6. SDO Mute Time refers to the response of the SDO outputs from valid re-clocked input data to mute mode when the input signal is removed. 7. Using the DDI input, A/D=0. 8. Using the SDI input, A/D=1. 9. Carrier detect response time refers to the response of the SSI/CD output from a logic high to logic low state when the input signal is removed or its amplitude drops below the threshold set by the CD_ADJ PIN. SSI/CD PIN loading CL