GS9025ACTM

GENLINX ™II GS9025A Serial Digital Receiver PRELIMINARY DATA SHEET FEATURES • SMPTE 259M compliant • operational to 540Mb/s • automatic cable equalization (typically greater than 350m of high quality cable at 270Mb/s) • adjustment-free operation • auto-rate selection (5 rates) with manual override • single external VCO resistor for operation with five input data rates • data rate indication output • serial data outputs muted and serial clock remains active when input data is lost • operation independent of SAV/EAV sync signals • signal strength indicator output • carrier detect with programmable threshold level • power savings mode (output serial clock disable) APPLICATIONS Cable equalization plus clock and data recovery for all high speed serial digital interface applications involving SMPTE 259M and other data standards. DESCRIPTION The GS9025A provides automatic cable equalization and high performance clock and data recovery for serial digital signals. The GS9025A receives either single-ended or differential serial digital data and outputs differential clock and retimed data signals at PECL levels (800mV). The onboard cable equalizer provides up to 40dB of gain at 200MHz which typically results in equalization of greater than 350m of high quality cable at 270Mb/s. The GS9025A operates in either auto or manual data rate selection mode. In both modes, the GS9025A requires only one external resistor to set the VCO centre frequency and provides adjustment free operation. The GS9025A has dedicated pins to indicate signal strength/carrier detect, LOCK and data rate. Optional external resistors allow the carrier detect threshold level to be customized to the user's requirement. In addition, the GS9025A provides an 'Output Eye Monitor Test' (OEM_TEST) for diagnostic testing of signal integrity after equalization, prior to reslicing. The serial clock outputs can also be disabled to reduce power. The GS9025A operates from a single +5 or -5 volt supply. ORDERING INFORMATION PART NUMBER GS9025ACQM GS9025ACTM PACKAGE 44 pin MQFP Tray 44 pin MQFP Tape TEMPERATURE 0°C to 70°C 0°C to 70°C GS9025A A/D DDI DDI ANALOG DIGITAL MUX CARRIER DETECT PHASELOCK HARMONIC COSC LOCK LOGIC MUTE SDO SDI SDI + - VARIABLE GAIN EQ STAGE FREQUENCY ACQUISITION PHASE DETECTOR SDO CLK_EN SCO SCO OEM_TEST EYE MONITOR DIVISION AUTO EQ CONTROL CHARGE PUMP 3 BIT COUNTER SMPTE AUTO/MAN SS0 SS1 SS2 + AGC CAP CD_ADJ SSI/CD VCO DECODER LF+ LFS LF- CBG RVCO BLOCK DIAGRAM Revision Date: June 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 75 - 00 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage (VS) Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) VALUE 5.5V VCC + 0.5 to VEE - 0.5V 0°C ≤ TA ≤ 70°C GS9025A -65°C ≤ TS ≤ 150°C 260°C DC ELECTRICAL CHARACTERISTICS VCC = 5.0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER Supply Voltage Supply Current CONDITION MIN 4.75 TYPICAL 5 115 125 2.5 1 MAX 5.25 UNITS V mA NOTES TEST LEVEL 1 1 CLK_EN = 0 CLK_EN = 1 VEE+(VDIFF/2) 200 SDI Common Mode Voltage DDI Common Mode Input Voltage Range DDI Differential Input Drive SSI/CD Output Current Source, CLMAX = 50pF, RL = open cct. Source, CLMAX = 50pF, RL=5K Sink AGC Common Mode Voltage OEM_TEST Bias Potential A/D, AUTO/MAN, SMPTE, SS[2:0] Input Voltage CLK_EN Input Voltage High Low High Low LOCK Output Sink Current SS[2:0] Output Voltage High Low SS[2:0] Source Current SS[2:0] Sink Current SS[2:0] Source Current Auto Mode Auto Mode Manual Mode VCC-(VDIFF/2) 2000 18 V V 2 1 1 0.4 to 4.6 800 - mV µA 1 3 - - - 110 µA 3 2.0 2.5 500 4.4 180 0.6 - 1.0 2.7 4.5 4.7 0.2 300 1.0 0 1.5 0.8 0.8 0.4 - mA V V V 5 3 1 1 1 V 1 µA V 3 1 1 µA mA µA 4 1 1 2 GENNUM CORPORATION 522 - 75 - 00 DC ELECTRICAL CHARACTERISTICS (continued) VCC = 5.0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER SS[2:0] Sink Current CLK_EN Source Current NOTES CONDITION Manual Mode Low MIN - TYPICAL 0.8 26 1 MAX 5 55 UNITS µA µA NOTES TEST LEVEL 1 GS9025A TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1,2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 1. TYPICAL - measured on EB9025A board. 2. VDIFF is the differential input signal swing. 3. LOCK is an open collector output and requires an external pullup resistor. 4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL mode. 5. If OEM_TEST is permanently enabled, operating temperature range is limited from 0°C to 60°C inclusive. AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER Serial Data Rate Maximum Equalizer Gain Additive Jitter [Pseudorandom (2 23 CONDITIONS SDI @ 200MHz 270Mb/s, 300m (Belden 8281) 540Mb/s, 100m (Belden 8281) MIN 143 - TYPICAL 40 300 1 MAX 540 - UNITS Mb/s dB ps p-p NOTES TEST LEVEL 1 7 2, 8 3 -1)] - 275 - Intrinsic Jitter [Pseudorandom (2 Intrinsic Jitter [Pathological (SDI checkfield)] 23 270Mb/s -1)] 540Mb/s 270Mb/s 360Mb/s 540Mb/s 0.40 0.35 - 185 164 462 308 260 0.56 0.43 1 1 4 10 see Figure 12 ps p-p 2, 7 4 see Figure 13 ps p-p 2, 7 1 Input Jitter Tolerance 270Mb/s 540Mb/s - UI p-p 3, 7 1 Lock Time Synchronous Switch tswitch < 0.5µs, 270Mb/s 0.5µs< tswitch 10 ms µs ms ms ms 4 7 Lock Time Asynchronous Switch Carrier Loss Time SDO to SCO Synchronization Loop Bandwidth = 6MHz @ 540Mb/s 5 7 0.5 -200 1 0 2 200 µs ps 6 7 7 3 GENNUM CORPORATION 522 - 75 - 00 AC ELECTRICAL CHARACTERISTICS VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8k, CLF1 = 15nF, CLF2 = 3.3pF PARAMETER SDO, SCO Output Signal Swing SDO, SCO Rise & Fall times SDI/SDI Input Resistance SDI/SDI Input Capacitance SDI/SDI Input Return Loss Carrier Detect Response Time CONDITIONS 75Ω DC load MIN 600 TYPICAL 800 1 MAX 1000 UNITS mV p-p NOTES TEST LEVEL 1 GS9025A 20%-80% 200 - 300 10 1.0 20 3 400 - ps kΩ pF dB µs 8 8 8 8 7 6 6 6 6 at 270MHz Carrier Applied, CL 4 R LF2 C LF2 RLF or GENNUM CORPORATION 522 - 75 - 00 This causes lift in the transfer function given by: w P1 1 20 LOG --------- = 20 LOG --------------------wZ wZ 1 – ----------w BW To keep peaking to less than 0.05dB: wZ < 0.0057wBW 9.3 Selection of Loop Filter Components 9-4. SPICE Simulations More detailed analysis of the GS9025A PLL can be done using SPICE. A SPICE model of the PLL is shown below: PHII IN+ INRLF 1 CLF1 R2 G1 LF PHIO E1 2 π Kƒ Ns GS9025A V1 Based on the above analysis, the loop filter components should be selected for a given PLL bandwidth, ƒ3dB, as follows: 1. Calculate 2N L = -------------ICP K ƒ where: ICP is the charge pump current and is a function of the RVCO resistor and is obtained from Figure 24. Kƒ = 90MHz/V for VCO frequencies corresponding to the ƒL curve. Kƒ = 140MHz/V for VCO frequencies corresponding to the ƒH curve. N is the divider modulus (ƒL, ƒH and N can be obtained from Table 2 or Table 3) 2. Choose RLF = 2(3.14)ƒ3dB(0.78)L 3. Choose CLF1 = 174L/(RLF) 4. Choose CLF2 = L/4(RLF) 400 CLF2 NOTE: PHII, PHIO, LF, and 1 are node names in the SPICE netlist. Fig. 25 SPICE Model of the PLL The model consists of a voltage controlled current source (G1), the loop filter components (RLF, CLF1, and CLF2), a voltage controlled voltage source (E1), and a voltage source (V1). R2 is necessary to create a DC path to ground for Node 1. V1 is used to generate the input phase waveform. G1 compares the input and output phase waveforms and generates the charge pump current, ΙCP. The loop filter components integrate the charge pump current to establish the loop filter voltage. E1 creates the output phase waveform (PHIO) by multiplying the loop filter voltage by the value of the Laplace transform (2πKƒ/Ns). The net list for the model is given below. The .PARAM statements are used to set values for ΙCP, Kƒ, N, and D. ΙCP is determined by the RVCO resistor and is obtained from Figure 24. 2 2 350 300 250 200 150 100 50 0 0 200 400 600 800 1000 1200 1400 1600 1800 RVCO (Ω) Fig. 24 RVCO vs. Charge Pump Current SPICE NETLIST * GS9025A PLL Model .PARAM ICP = 165E-6 KF= 90E+6 .PARAM N = 1 D = 0.5 .PARAM PI = 3.14 .IC V(Phio) = 0 .ac dec 30 1k 10meg RLF 1 LF 1000 CLF1 1 0 15n CLF2 0 LF 15p E_LAPLACE1 Phio 0 LAPLACE {V(LF)} {(2*PI*KF)/(N*s)} G1 0 LF VALUE{D * ICP/(2*pi)*V(Phii, Phio)} V1 2 0 DC 0V AC 1V R2 0 1 1g .END CHANGE PUMP CURRENT (µA) 15 GENNUM CORPORATION 522 - 75 - 00 10. I/O DESCRIPTION RSOURCE ZO DDI RLOAD DDI ZO GS9025 10-1. High Speed Analog Inputs (SDI/SDI) SDI/SDI are high impedance inputs differential or single-ended input drive. which accept RSOURCE Figure 26 shows the recommended interface when a singleended serial digital signal is used. 75 75 113 10nF SDI 10nF GS9025 SDI Fig. 28 Figure 29 shows the recommended interface when the GS9025A digital inputs are driven single-endedly. In this case, the input must be AC-coupled and a matching resistor (Zo) must be used. DDI GS9025A Fig. 26 10-2. High Speed Digital Inputs (DDI/DDI) ZO DDI GS9025 DDI/DDI are high impedance inputs which accept differential or single-ended input drive. Two conditions must be observed when interfacing to these inputs: 1. Input signal amplitudes are between 200 and 2000 mV 2. The common mode input voltage range is as specified in the DC Characteristics table. Commonly used interface examples are shown in Figures 27 to 29. Figure 27 illustrates the simplest interface to the GS9025A digital inputs. In this example, the driving device generates the PECL level signals (800mV amplitudes) having a common mode input range between 0.4 and 4.6V. This scheme is recommended when the trace lengths are less than 1in. The value of the resistors depends on the output driver circuitry. Fig. 29 When the DDI and the DDI inputs are not used, saturate one input of the differential amplifier for improved noise immunity. To saturate, connect either pins 44 and 1 or pins 2 and 3 to VCC. Leave the other pair floating. 10-3. High Speed Outputs (SDO/SDO and SCO/SCO) SDO/SDO and SCO/SCO are current mode outputs that require external pullups (see Figure 30). The output signal swings are 800mV when 75Ω resistors are used. To shift the signal levels down by approximately 0.7 volts, place a diode between VCC and the pullups. When the output traces are longer than 1in, use controlled impedance traces. Place the pullup resistors at the end of the output traces as they terminate the trace in its characteristic impedance (75Ω). VCC DDI DDI GS9025 SDO SDO GS9025 SCO SCO 75 75 Fig. 27 75 VCC 75 When trace lengths become greater than 1in, controlled impedance traces should be used. The recommended interface is shown in Figure 29. In this case, a parallel resistor (RLOAD) is placed near the GS9025A inputs to terminate the controlled impedance trace. The value of RLOAD should be twice the value of the characteristic impedance of the trace. In addition, place series resistors (RSOURCE) near the driving chip to serve as source terminations. They should be equal to the value of the trace impedance. Assuming 800mV output swings at the driver, RLOAD = 100Ω, RSOURCE = 50Ω and ZO = 50Ω. Fig. 30 16 GENNUM CORPORATION 522 - 75 - 00 TYPICAL APPLICATION CIRCUIT VCC VCC VCC VCC 10k 4.7n VCC VCC VCC VCC 44 43 42 41 40 39 38 37 36 35 34 GS9025A OEM_TEST SMPTE SSI/CD LOCK A/D CLK_EN VCC VCC_75 COSC VEE VEE From GS9024 see Note 1 VCC VCC 1 2 3 4 5 6 DDI DDI VEE SDO SDO VEE 33 32 31 30 29 28 27 26 25 24 23 4 x 75 see Note 2 VCC_75 VCC VEE SDI SDI VCC VEE RVCO_RTN CD_ADJ AGC+ AGC- To GS9020 GS9025A TOP VIEW SCO SCO VEE AUTO/MAN SS0 SS1 RVCO 75 75 37.5 VCC 10n 7 75 10n VCC 8 9 10 11 VCC 100k Pot (Optional) SS2 CBG VCC } To LED Driver (optional) VCC VEE LF+ LFS 12 All resistors in ohms, all capacitors in microfarads, unless otherwise stated. Power supply decoupling capacitors are not shown. 13 14 15 16 17 18 VEE LF- 19 20 21 22 0.1µ VCC 1.8k 15n 3.3p 365 (1%) VCC 0.1µ 0.1µ NOTES 1. It is recommended that the DDI/DDI inputs are not driven when the SDI/SDI inputs are being used. This minimizes crosstalk between the DDI/DDI and SDI/SDI inputs and maximizes performance. 2. These resistors are not needed if the internal pull-up resistors on the GS9020 are used. TABLE 5. RVCO = 365, ƒH = 540MHz, ƒL = 360MHz SMPTE 1 1 1 1 1 SS[2:0] 000 001 010 011 100 DATA RATE (Mb/s) 143 177 270 360 540 LOOP BANDWIDTH (MHz) 1.2 1.9 3.0 4.5 6.0 17 GENNUM CORPORATION 522 - 75 - 00 PACKAGE DIMENSIONS 13.20 ±0.25 10.00 ±0.10 GS9025A 13.20 ±0.25 10.00 ±0.10 PIN 1 0.80 BSC 0.45 MAX 0.30 MIN 5˚ to 16˚ 0.20 MIN 0˚ MIN 0.3 MAX. RADIUS 7˚ MAX 0˚ MIN 2.20 MAX 1.85 MIN 0.23 MAX. All dimensions in millimetres 2.55 MAX 5˚ to 16˚ 0.13 MIN. RADIUS 1.60 REF 0.88 NOM. 0.35 MAX 0.15 MIN 44 pin MQFP CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice. REVISION NOTES: New document. For latest product information, visit www.gennum.com GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright June 2000 Gennum Corporation. All rights reserved. Printed in Canada. 18 522 - 75 - 00