GS9076-CNE3

GS9076 HD-LINX® III SD-SDI Automatic Reclocker with Dual Differential Outputs GS9076 Data Sheet Features • • • • • • • • • • • • • SMPTE 259M-C compliant Automatic lock to SDI and DVB-ASI at 270Mb/s 4:1 input multiplexer patented technology Choice of dual reclocked data outputs or one data output and one recovered clock output Loss of Signal (LOS) Output Lock Detect Output On-chip Input and Output Termination Differential 50Ω inputs and outputs Mute, Bypass and Autobypass functions Footprint and drop-in compatible with existing GS2975A designs Pb-free and RoHS Compliant Single 3.3V power supply Operating temperature range: 0°C to 70°C Description The GS9076 is an SD-SDI Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The device automatically detects and locks to incoming SMPTE 259M-C SDI and DVB-ASI signals at 270Mb/s. The GS9076 removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50Ω transmission lines. The device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing of non-SMPTE data rates, the GS9076 can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The GS9076 offers a choice of dual reclocked data outputs or one data output and one recovered clock output. The device is footprint and drop-in compatible with existing GS2975A designs, with no additional application changes required. The GS9076 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous sub-components are RoHS compliant. Applications • SMPTE 259M-C Serial Digital Interfaces 44617 - 1 January 2008 1 of 25 www.gennum.com GS9076 Data Sheet Functional Block Diagram XTAL+ XTALXTAL XTAL OUT+ OUTLF+ LFKBB XTAL OSC BUFFER RE-TIMER M U X L DATA BUFFER DDO 0 DDO_MUTE RCO_MUTE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X DIVIDER M U X CHARGE PUMP M U X CLOCK/DATA BUFFER RCO/DDO1 VCO DDI 1 PHASE DETECTOR DIVIDER DATA/CLOCK DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] AUTO/MAN SD LD LOS AUTOBYPASS BYPASS GS9076 Functional Block Diagram 44617 - 1 January 2008 2 of 25 GS9076 Data Sheet Contents Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 Functional Block Diagram .............................................................................................2 1. Pin Out ......................................................................................................................4 1.1 GS9076 Pin Assignment .................................................................................4 1.2 GS9076 Pin Descriptions ................................................................................5 2. Electrical Characteristics ...........................................................................................8 2.1 Absolute Maximum Ratings ............................................................................8 2.2 DC Electrical Characteristics ..........................................................................8 2.3 AC Electrical Characteristics ...........................................................................9 2.4 Solder Reflow Profiles ...................................................................................12 3. Input / Output Circuits .............................................................................................13 4. Detailed Description ................................................................................................16 4.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................16 4.2 VCO ..............................................................................................................17 4.3 Charge Pump ................................................................................................17 4.4 Frequency Acquisition Loop — The Phase-Frequency Detector ..................18 4.5 Phase Acquisition Loop — The Phase Detector ...........................................18 4.6 4:1 Input Mux ................................................................................................19 4.7 Automatic and Manual Data Rate Selection .................................................19 4.8 Bypass Mode ................................................................................................20 4.9 Lock and LOS ...............................................................................................20 5. Typical Application Circuit .......................................................................................21 6. Package & Ordering Information .............................................................................22 6.1 Package Dimensions ....................................................................................22 6.2 Recommended PCB Footprint ......................................................................23 6.3 Packaging Data .............................................................................................24 6.4 Marking Diagram ...........................................................................................24 6.5 Ordering Information .....................................................................................24 7. Revision History ......................................................................................................25 44617 - 1 January 2008 3 of 25 GS9076 Data Sheet 1. Pin Out 1.1 GS9076 Pin Assignment XTAL_OUTXTAL_OUT+ VCC_CP VEE_CP XTAL+ XTAL- DDI0 DDI0_VTT 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 GND LF+ NC LF- NC NC NC NC NC NC VEE_DDO VCC_DDO DDO0 RSV DDO0 GND_DRV VEE_RCO VCC_RCO RCO/DDO1 – DDI0 GND DDI1 2 3 4 5 6 7 8 9 10 11 12 13 14 DDI1_VTT – DDI1 GND DDI2 GS9076 64-pin QFN (Top View) 42 41 40 39 38 37 36 35 DDI2_VTT – DDI2 GND DDI3 DDI3_VTT – RCO/DDO1 DATA/CLOCK DDO_MUTE RCO_MUTE KBB SD RSV – DDI3 GND 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DDI_SEL1 BYPASS AUTOBYPASS VCC_VCO VEE_VCO LOCKED LOS VCC_DIG AUTO SS0 SS1 SS2 NC VEE_DIG Ground Pad (bottom of package) Figure 1-1: 64-Pin QFN DDI_SEL0 44617 - 1 January 2008 GND 4 of 25 GS9076 Data Sheet 1.2 GS9076 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1, 3 2 4, 8, 12,16, 32, 43, 49 5, 7 6 9, 11 10 13, 15 14 17, 18 Name DDI0, DDI0 DDI0_VTT GND DDI1,DDI1 DDI1_VTT DDI2, DDI2 DDI2_VTT DDI3, DDI3 DDI3_VTT DDI_SEL[1:0] Type Input Passive Passive Input Passive Input Passive Input Passive Logic Input Description Serial digital differential input 0. Center tap of two 50Ω on-chip termination resistors between DDI0 and DDI0. Recommended connect to GND. Serial digital differential input 1. Center tap of two 50Ω on-chip termination resistors between DDI1 and DDI1. Serial digital differential input 2. Center tap of two 50Ω on-chip termination resistors between DDI2 and DDI2. Serial digital differential input 3. Center tap of two 50Ω on-chip termination resistors between DDI3 and DDI3. Serial digital input select. DDI_SEL1 0 0 1 1 DDI_SEL0 0 1 0 1 INPUT SELECTED DDI0 DDI1 DDI2 DDI3 19 BYPASS Logic Input Bypass the reclocker stage. When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked This pin is ignored when BYPASS is HIGH. 21 AUTO Logic Input Auto select. This pin should be set HIGH for automatic SD-SDI and DVB-ASI standard detection. 22 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to 3.3V. 23 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. 24, 25, 26 27 28 SS[2:0] NC LOCKED Bi-directional No Connect Output The SS[2:0] pins will display 010 when the internal PLL has locked to a 270Mb/s input data rate. Not connected internally. Lock Detect. This pin is set HIGH by the device when the PLL is locked. 44617 - 1 January 2008 5 of 25 GS9076 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 29 Name LOS Type Output Description Loss of Signal. Set HIGH when there are no transitions on the active DDI[3:0] input. 30 VCC_DIG Power Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 34 35 SD KBB RCO_MUTE Output Analog Input Power This signal will be set HIGH when the reclocker has locked to 270Mbps or LOW when a non-SMPTE standard is applied. (i.e. the device is not locked). Controls the loop bandwidth of the PLL. Serial clock or secondary data output mute. Assert LOW for reduced power consumption, see Section 2.2 DC Electrical Characteristics. When RCO_MUTE = LOW, the RCO/DDO1 output is powered down. When RCO_MUTE = HIGH, the RCO/DDO1 output is active. NOTE: This is not a logic input pin. 36 DDO_MUTE Logic Input Mutes the DDO0 and/or RCO/DDO1 outputs. DDO_MUTE 1 1 0 0 1 0 RCO_MUTE 1 1 1 1 0 0 DATA/CLOCK 0 1 0 1 X X DDO0 DATA DATA MUTE MUTE DATA MUTE RCO/DDO1 CLOCK DATA CLOCK MUTE Power down Power down NOTE: MUTE = Outputs latched at previous data bit. Power down = Outputs pulled to Vcc through 50Ω resistor. 37 DATA/CLOCK Logic Input Data/Clock select. When set HIGH, the RCO/DDO1 pin will output a copy of the serial digital ouput (DDO0). When set LOW, the RCO/DDO1 pin will output a re-timed clock (RCO). 38, 40 RCO/DDO1 / RCO/DDO1 Output Serial clock or secondary data output. When RCO_MUTE is connected to VCC, the serial digital differential clock or secondary data output will be presented. 39, 45 41 RSV VCC_RCO Reserved Power Do not connect. Most positive power supply connection for the RCO/DDO1 and RCO/DDO1 output driver. Connect to 3.3V. 44617 - 1 January 2008 6 of 25 GS9076 Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 42 Name VEE_RCO Type Power Description Most negative power supply connection for theRCO/DDO1 and RCO/DDO1 output driver. Connect to GND. 43 44, 46 47 GND_DRV DDO0, DDO0 VCC_DDO Passive Output Power Recommended connect to GND. Differential Serial Digital Outputs. Most positive power supply connection for the DDO0/DDO0 output driver. Connect to 3.3V. 48 VEE_DDO Power Most negative power supply connection for the DDO0/DDO0 output driver. Connect to GND. 50, 51 52, 53 54 - 59 60 XTAL_OUT+, XTAL_OUTXTAL+, XTALNC VEE_CP Output Input No Connect Power Differential outputs of the reference oscillator used for monitoring or test purposes. Reference crystal input. Connect to the GO1535 as shown in the Typical Application Circuit on page 21. Not connected internally. Most negative power supply connection for the internal charge pump. Connect to GND. 61 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V. 62, 63 64 – LF+, LFNC Center Pad Passive No Connect – Loop filter capacitor connection. Connect as shown in the Typical Application Circuit on page 21. Not connected internally. Recommended connect to GND. Ground pad on bottom of package. Solder to main ground plane following recommendations under Recommended PCB Footprint on page 23 44617 - 1 January 2008 7 of 25 GS9076 Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Range Input Voltage Range Operating Temperature Range Storage Temperature Range Input ESD Voltage Solder Reflow Temperature Value -0.5V to +3.6 VDC Vee - 0.5V to Vcc + 0.5V -20°C to 85°C -50°C < Ts < 125°C 4kV HBM, 100V MM 260°C NOTE: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the AC/DC Electrical Characteristic sections is not implied. 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Supply Voltage Supply Current Symbol VCC ICC ICC Conditions Operating Range RCO/DD01 enabled RCO/DDO1 disabled RCO/DD01 enabled RCO/DD01 disabled High Low IOH = -2mA IOL = 2mA IOH = -2mA IOL = 2mA High Low Min 3.135 – – – – 2.0 – 2.4 – 2.4 – – – Typ 3.3 142 123 468 404 – – – – – – VCC - 0.075 VCC - 0.300 Max 3.465 170 152 590 528 – 0.8 – 0.4 – 0.4 – – Units V mA mA mW mW V V V V V V V V Power Consumption – – Logic Inputs DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO, DDO_MUTE Logic Outputs SD, LOCKED, LOS Bi-Directional Pins (Auto Mode) SS[2:0], AUTO = 1 XTAL_OUT+, XTAL_OUT- VIH VIL VOH VOL VOH VOL VOH VOL 44617 - 1 January 2008 8 of 25 GS9076 Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter RCO_MUTE Serial Input Voltage Symbol – – Conditions I = -1.5mA Common Mode Min VCC - 0.165 1.65 + (VSID/2) – Typ VCC – Max VCC + 0.165 VCC (VSID/2) – Units V V Serial Output Voltage DDO0/DDO0, RCO/DDO1 / RCO/DDO1 – Common Mode VCC - (VOD/2) V 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Serial Input Data Rate Serial Input Jitter Tolerance PLL Lock Time - Asynchronous PLL Lock Time - Synchronous Serial Output Rise/Fall Time SDO0 and RCO/DDO1 (20% 80%) Serial Digital Input Signal Swing Symbol – – t ALOCK t SLOCK trSDO,trRCO tfSDO,tfRCO VSID Conditions – Worst case modulation (e.g. square wave modulation) – KBB = Float, CLF=47nF, 270Mb/s 50Ω load (on chip) 50Ω load (on chip) Differential with internal 100Ω input termination See Figure 2-1 Min – 0.8 – – – – 100 Typ 270 – 0.5 5 110 110 – Max – – 2.0 20 – – 800 Units Mb/s UI ms us ps ps mVp-p Notes – – – – – – – Serial Digital Output Signal Swing DDO0 and RCO/DDO1 DDO0 to DDO1 skew DDO0 to RCO skew Serial Output Jitter on DDO0 and DDO1 Additive Jitter VOD DDskew DRskew tOJ tAJ 100Ω load differential See Figure 2-2 270Mb/s 270 Mb/s 270 Mb/s Bypass mode, 270 Mb/s 300 450 600 mVp-p – – – – – 156 37 0.02 15 – – 0.07 – ps ps UI ps 1 2 3 – 44617 - 1 January 2008 9 of 25 GS9076 Data Sheet Table 2-2: AC Electrical Characteristics (Continued) VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C Parameter Loop Bandwidth Symbol BWLOOP Conditions 270 Mb/s, KBB = VCC 270 Mb/s, KBB = FLOAT 270 Mb/s, KBB = GND, 0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 4-2: Phase Detector Characteristics When the PA loop is active, the crystal frequency and the incoming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. 44617 - 1 January 2008 18 of 25 GS9076 Data Sheet 4.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 4-1: Bit Pattern for Input Select DDI_SEL[1:0] 00 01 10 11 Selected Input DDI0 DDI1 DDI2 DDI3 The DDI inputs are designed to be DC interfaced with the output of the GS9074A Cable Equalizer. There are on chip 50Ω termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 Automatic and Manual Data Rate Selection The GS9076 can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic data rate detection mode (Auto mode) when HIGH and manual data rate selection mode (Manual mode) when LOW. In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). In Manual mode, the data rate can be programmed and the SS[2:0] pins become inputs. In this mode, the PLL will only lock to the data rate selected. Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual mode) or the data rate that the PLL has locked to (in Auto mode). Table 4-2: Data Rate Indication/Selection Bit Pattern SS[2:0] 010 Data Rate (Mb/s) 270 44617 - 1 January 2008 19 of 25 GS9076 Data Sheet 4.8 Bypass Mode In Bypass mode, the GS9076 passes the data at the inputs directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. When BYPASS is set HIGH, the GS9076 will be in Bypass mode. When AUTOBYPASS is set HIGH, the GS9076 will be configured to enter Bypass mode only when the PLL has not locked to a data rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored. When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial digital output DDO0/DDO0 or DDO1/DDO1 will produce invalid data. 4.9 Lock and LOS The LOCKED signal is an active high output which indicates when the PLL is locked. The internal lock logic of the GS9076 includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. The LOS (Loss of Signal) output is an active HIGH output which indicates the absence of data transitions at the DDIx input. In order for this output to be asserted, transitions must not be present for a period of tLA = 5 - 10 us. After this output has been asserted, LOS will deassert within tLD = 0 - 5 us after the appearance of a transition at the DDIx input. t LA t LD DATA LOS Figure 4-3: LOS signal timing NOTE: LOS is sensitive to transitions appearing at the input, and does not distinguish between transitions caused by input data, and transitions due to noise. 44617 - 1 January 2008 20 of 25 GS9076 Data Sheet 5. Typical Application Circuit GO1535 (14.140MHz) 47n 3.3V 100 10n 55 64 63 62 61 60 59 58 57 56 54 53 XTAL+ 52 51 XTAL_OUT50 XTAL_OUT+ VCC_CP XTAL- VEE_CP GND NC NC LF+ NC NC LF- NC NC NC 49 1 DDI0 DDI0_VT DDI0 GND DDI1 DDI1_VT DDI1 GND DDI2 DDI2_VT DDI2 GND DDI3 DDI3_VT DDI3 AUTOBYPASS VEE_DDO VCC_DDO DDO0 RSV DDO0 GND_DRV VEE_RCO 48 10n 47 46 45 44 43 42 10n 41 40 3.3V 3.3V DATA INPUT 0 Zo = 50 2 10n 3 4 5 Zo = 50 DATA OUTPUT DATA INPUT 1 Zo = 50 6 10n 7 8 9 GS9076 VCC_RCO RCO/DDO1 RSV RCO/DDO1 DATA/CLOCK DDO_MUTE RCO_MUTE KBB SD 33 SD 39 38 37 36 35 34 DATA/CLOCK DDO_MUTE RCO_MUTE DATA INPUT 2 Zo = 50 10 10n 11 12 13 Zo = 50 CLOCK OUTPUT DATA INPUT 3 Zo = 50 14 10n 15 16 GND DDI_SEL0 DDI_SEL1 BYPASS VCC_VCO VCC_DIG VEE_VC0 VEE_DIG 31 LOCKED AUTO 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n DDI_SEL0 DDI_SEL1 3.3V 10n 3.3V 32 GND LOS SS0 SS1 SS2 NC LOS LOCKED Note: All resistors in ohms and all capacitors in Farads. Figure 5-1: GS9076 Typical Application Circuit 44617 - 1 January 2008 21 of 25 GS9076 Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions 0.40+/-0.05 9.00 4.50 A B 0.3+/-0.05 7.10+/-0.15 3.55 5 45˚ 45 ˚ 4.50 0.35 9.00 PIN 1 AREA CENTRE TAB 2X 0.15 C 0.20 REF 2X 0.10 C 0.15 C 0.25+/-0.05 0.50 64X C CAB 0.10 C 0.05 64X 0.08 C 0.90 +/- 0.10 +0.03 0.02-0.02 SEATING PLANE ALL DIMENSIONS IN MM 44617 - 1 January 2008 3.55 7.10+/-0.15 22 of 25 GS9076 Data Sheet 6.2 Recommended PCB Footprint 0.50 0.25 0.55 CENTER PAD 8.70 7.10 7.10 8.70 NOTE: All dimensions are in millimeters. The center pad of the PCB footprint should be connected to the ground plane by a minimum of 36 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations. 44617 - 1 January 2008 23 of 25 GS9076 Data Sheet 6.3 Packaging Data Parameter Package Type Moisture Sensitivity Level (per JEDEC J-STD-020C) Junction to Case Thermal Resistance, θj-c Junction to Air Thermal Resistance, θj-a (at zero airflow) Junction to Board Thermal Resistance, θj-b Psi, Ψ Pb-free and RoHS Compliant Value 9mm x 9mm 64-pin QFN 3 9.1°C/W 21.5°C/W 5.6°C/W 0.2°C/W Yes 6.4 Marking Diagram Pin 1 ID GS9076 XXXXE3 YYWW 6.5 Ordering Information Part Number GS9076 GS9076-CNE3 XXXX - Lot/Work Order ID YYWW - Date Code YY - 2-digit year WW - 2-digit week number Package Pb-free 64-pin QFN Temperature Range 0°C to 70°C 44617 - 1 January 2008 24 of 25 GS9076 Data Sheet 7. Revision History Version 1 ECR 149009 PCN – Date January 2008 Changes and/or Modifications Changes to Functional Block Diagram, Figure 3-7 and Ordering Information. Addition of section 4.7 Automatic and Manual Data Rate Selection. New Document. 0 144926 – May 2007 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2007 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 44617 - 1 January 2008 25 25 of 25