GV7601
Aviia™ Receiver
Key Features
Applications
•
Serial digital video receiver for standard and high
definition component video:
•
Digital video recorders (DVR)
•
Video servers
•
•
•
•
•
Video mixers and switchers
•
Image capture devices
•
Video framegrabbers
•
Camcorders
•
Video monitors & displays
•
Supports 8-bit, 10-bit or 12-bit component digital
video:
•
•
•
SD 525i and 625i
HD 720p 24, 25, 30, 50 and 60
HD 1080i 50, 60
HD 1080p 24, 25, 30, 50 and 60
RGB or YCbCr 4:4:4 sampled
YCbCr 4:2:2 or 4:2:0 sampled
Description
Integrated cable equalizer for long reach cable
performance
•
•
230m typical HD performance over high-quality 75Ω
coaxial cable (Belden 1694A or equivalent)
160m typical HD performance over RG59 or equivalent
75Ω coaxial cable
•
Serial digital loop-though output
•
Integrated audio de-embedder for the extraction of up
to 8 channels of 48kHz digital audio
•
Supports IEC 13818-1 compliant transport streams
over the Asynchronous Serial Interface (ASI)
•
Automatic selection between SD/HD component
video and ASI input data
•
Ancillary (ANC) data detection and extraction
•
User selectable processing features, including:
• Timing Reference Signal (TRS) error detection and
correction
• ANC data checksum error detection and correction
• Programmable ANC data detection
• Line number and CRC error detection and correction
• Illegal video code word re-mapping
4-wire Gennum Serial Peripheral Interface (GSPI) for
external host command and control
•
•
JTAG test interface
•
1.2V core and 3.3V analog voltage power supplies
•
1.8V or 3.3V selectable digital I/O power supply
•
Small footprint 100-BGA (11mm x 11mm)
•
Low power operation, typically 570mW at HD
•
Pb-free and RoHS compliant
GV7601
Final Data Sheet
GENDOC-052155
The GV7601 is a serial digital video receiver for standard
and high definition component video, operating at
270Mb/s, 1.485Gb/s and 2.97Gb/s data rates. With
integrated cable equalizer technology, the GV7601 is
capable of receiving digital video over 75Ω coaxial cable at
lengths up to 460m for standard definition video, and up to
230m for high definition. This provides a complete receive
solution for the transmission of both interlaced and
progressive component digital video, up to 1920 x 1080, in
coaxial cable-based video systems.
Using the GV7601 with the complete Aviia™ receiver
reference design, it is possible to implement an all-digital,
bi-directional multimedia interface over coax. This
interface allows both DC power and a bi-directional,
half-duplex, auxiliary data interface to be carried over the
same single, robust and cost effective coaxial cable as the
high-speed serial digital video. The GV7601 also provides a
re-timed serial digital output for video loop-through
applications.
The GV7601 includes a broad range of user-selectable
processing features, such as Timing Reference Signal (TRS)
error detection and extraction, illegal code word
re-mapping, and ancillary data packet extraction. The
content of ancillary data packets, embedded by an Aviia
transmitter, can be extracted and retrieved via the host
interface. Device configuration and status reporting is
accomplished via the Gennum Serial Peripheral Interface
(GSPI). Alternatively, many processing features and
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48kHz synchronous or asynchronous for HD formats.
Additional audio processing features include: individual
channel extraction, audio group selection, group
replacement, channel swapping and audio channel status
extraction.
operational modes can be configured directly through
external pin settings.
The device can output both 8-bit, 10-bit and 12-bit video
data, for RGB or YCbCr 4:4:4, and YCbCr 4:2:2 or 4:2:0. A
configurable 20-bit wide parallel digital video output bus is
provided, with associated pixel clock and timing signal
outputs. The GV7601 supports ITU-R BT.656 SD formats, and
HD formats conforming to ITU-R BT.709 and BT.1120-6 for
1125-line formats, and SMPTE 296M for 750-line formats.
The device may also be configured to output CEA-861
timing.
The GV7601 also supports an Asynchronous Serial Interface
(ASI) 270Mb/s input, carrying compressed audio and video
transport streams, conforming to IEC 13818-1. Transport
stream data is output from the device at a synchronous
27MHz clock rate. The device will automatically deserialize
and 8b/10b decode the data.
20BIT/10BIT
PROC_EN
AUDIO_EN
ASI
656_BYPASS
XTAL_OUT
XTAL1
XTAL2
LB_CONT
VBG
LF
EQ_VDD
EQ_GND
861_EN
Packaged in a space saving 100-BGA, the GV7601 is ideal for
designs where high-density component placement is
required. Typically requiring only 570mW power, the device
can be used as a high bandwidth alternative to analog
composite or component video interfaces, providing a high
quality, all-digital, long reach video receive solution.
The GV7601 audio de-embedding function allows the up to
8 channels of serial digital audio within the ancillary data
space of the video data stream to be extracted. The audio
output signal formats supported by the device include
AES/EBU for professional applications, S/PDIF, and I2S.
16-bit, 20-bit and 24-bit audio formats are supported at
48kHz synchronous-to-video for SD video formats and
MCLK
ACLK
WCLK
Crystal
Buffer/
Oscillator
AGC
AGC
SDI
Cable
Equalizer
Serial to
Parallel
Conversion
Data
Re-timer
SDI
Serial Video
Descrambler,
Word Alignment
& Flywheel
Audio
De-embedder
and
Audio Clock
Generation
ASI Sync Detect,
Word Alignment &
8b/10b Decode
AOUT1/2
AOUT3/4
AOUT5/6
AOUT7/8
Error
Detection,
ANC Data
Extraction
TRS, Line
Number, CRC
and EDH
Insertion
Video/Data
Buffer
DOUT[19:0]
PCLK
Output
Buffer &
Mux
STAT[5:0]
IO_VDD (x4)
IO_GND (x4)
CORE_VDD (x4)
CORE_GND (x5)
JTAG_EN
I/O Control
CS_TMS
SDIN_TDI
STANDBY
VCO_VDD
VCO_GND
PLL_GND (x3)
PLL_VDD (x3)
AGND (x6)
AVDD
BUFF_GND
BUFF_VDD
SCLK_TCK
Host Interface &
JTAG Test
RECLK_EN
SDOUT_TDO
SDO
RESET
SDO
YANC/CANC
ERROR
RATE_DET[1:0]
F/DE
V/VSYNC
H/HSYNC
LOCKED
SDO_EN
Figure A: GV7601 Block Diagram
GV7601
Final Data Sheet
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Revision History
Version
ECR
Date
Changes and / or Modifications
7
019059
April 2014
Updated Figure 6-1: GV7601 Package
Dimensions.
6
158071
May 2012
Changed VIL and VIH (Min and Max) in Table
2-3: DC Electrical Characteristics.
5
153582
February 2010
4
152345
August 2009
Added analog input absolute maximum
ratings to Table 2-1: Absolute Maximum
Ratings. Updated device latency values in
Table 2-4: AC Electrical Characteristics.
Modified Key Features, Description, Table 2-3,
Table 2-4 and Table 4-1.
Modified Section 4.11.1.1, Section 4.12,
Section 4.17.4, Section 4.19, and Table 4-33.
3
152159
June 2009
Added Figure 4-64.
Changed 6.3 Marking Diagram.
2
151833
May 2009
Re-ordered the DOUT[19:10] & DOUT[9:0] in
Table 1-1 to reflect the pin names.
Changed Figure 4-41.
1
151651
April 2009
0
151484
February 2009
GV7601
Final Data Sheet
GENDOC-052155
Changed DOUT[18_10] and DOUT[9:0] pin
descriptions.
Changed 4.16.8 Ancillary Data Extraction and
its registers.
New document.
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Contents
Key Features...........................................................................................................................................................1
Applications ...........................................................................................................................................................1
Description .............................................................................................................................................................1
1. Pin Out.................................................................................................................................................................9
1.1 Pin Assignment ...................................................................................................................................9
1.2 Pin Descriptions ..................................................................................................................................9
2. Electrical Characteristics............................................................................................................................. 16
2.1 Absolute Maximum Ratings ........................................................................................................ 16
2.2 Recommended Operating Conditions .................................................................................... 16
2.3 DC Electrical Characteristics ........................................................................................................ 17
2.4 AC Electrical Characteristics ......................................................................................................... 19
3. Input/Output Circuits.................................................................................................................................. 28
4. Detailed Description.................................................................................................................................... 32
4.1 Functional Overview ...................................................................................................................... 32
4.2 Serial Digital Input ........................................................................................................................... 32
4.3 Serial Digital Output ....................................................................................................................... 33
4.4 Serial Digital Reclocker .................................................................................................................. 33
4.4.1 Reclocker PLL Loop Bandwidth...................................................................................... 34
4.5 External Crystal/Reference Clock ............................................................................................... 34
4.6 Lock Detect ........................................................................................................................................ 35
4.6.1 Asynchronous Lock ............................................................................................................ 36
4.6.2 Signal Interruption.............................................................................................................. 36
4.7 Video Functionality ......................................................................................................................... 37
4.7.1 Standard Definition Video Output Formats .............................................................. 37
4.7.2 High Definition Video Output Formats ....................................................................... 40
4.7.3 Descrambling and Word Alignment ............................................................................ 50
4.8 Parallel Video Data Outputs DOUT[19:0] and DOUT[9:0] .................................................. 50
4.8.1 Parallel Data Bus Buffers ................................................................................................... 50
4.8.2 Parallel Output in Video Mode ....................................................................................... 54
4.8.3 Parallel Output in ASI Mode ............................................................................................ 54
4.8.4 Parallel Output In Data-Through Mode ...................................................................... 55
4.8.5 Parallel Output Clock (PCLK) ........................................................................................... 55
4.8.6 DDR Parallel Clock Timing................................................................................................ 56
4.9 Timing Signal Generator ............................................................................................................... 57
4.10 Programmable Multi-function Outputs ................................................................................ 58
4.11 H:V:F Timing Signal Generation ............................................................................................... 59
4.11.1 CEA-861 Timing Generation ......................................................................................... 61
4.12 Automatic Video Standards Detection ................................................................................. 72
4.13 EDH Detection ................................................................................................................................ 74
4.13.1 EDH Packet Detection ..................................................................................................... 75
4.13.2 EDH Flag Detection .......................................................................................................... 75
4.14 Video Signal Error Detection & Indication ........................................................................... 76
4.14.1 TRS Error Detection .......................................................................................................... 77
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4.14.2 Line Based CRC Error Detection................................................................................... 77
4.14.3 EDH CRC Error Detection................................................................................................ 78
4.14.4 HD Line Number Error Detection................................................................................ 78
4.15 Ancillary Data Detection & Indication ................................................................................... 78
4.15.1 Programmable Ancillary Data Detection ................................................................. 81
4.15.2 Ancillary Data Checksum Error..................................................................................... 81
4.16 Video Error Correction ................................................................................................................. 82
4.16.1 TRS Correction & Insertion............................................................................................. 83
4.16.2 Line Based CRC Correction & Insertion ..................................................................... 83
4.16.3 Line Number Error Correction & Insertion ............................................................... 84
4.16.4 Ancillary Data Checksum Error Correction & Insertion ....................................... 84
4.16.5 EDH CRC Correction & Insertion .................................................................................. 84
4.16.6 Illegal Word Remapping................................................................................................. 84
4.16.7 TRS and Ancillary Data Preamble Remapping ....................................................... 85
4.16.8 Ancillary Data Extraction................................................................................................ 85
4.17 Audio De-embedder .................................................................................................................... 90
4.17.1 Serial Audio Data I/O Signals ........................................................................................ 90
4.17.2 Serial Audio Data Format Support.............................................................................. 92
4.17.3 Audio Processing .............................................................................................................. 96
4.17.4 Error Reporting ................................................................................................................100
4.18 Gennum Serial Peripheral Interface .....................................................................................101
4.18.1 Command Word Description......................................................................................101
4.18.2 Data Read or Write Access...........................................................................................102
4.18.3 GSPI Timing.......................................................................................................................103
4.19 Host Interface Register Maps ..................................................................................................105
4.19.1 Video Core Registers......................................................................................................105
4.19.2 SD Audio Core..................................................................................................................113
4.19.3 HD Audio Core Registers..............................................................................................125
4.20 JTAG Test Operation ..................................................................................................................138
4.21 Device Power-up .........................................................................................................................140
4.22 Device Reset ..................................................................................................................................140
4.23 Standby Mode ..............................................................................................................................140
5. References & Relevant Standards .........................................................................................................141
6. Package & Ordering Information ..........................................................................................................142
6.1 Package Dimensions ....................................................................................................................142
6.2 Packaging Data ..............................................................................................................................143
6.3 Marking Diagram ...........................................................................................................................143
6.4 Solder Reflow Profiles ..................................................................................................................144
6.5 Ordering Information ...................................................................................................................144
GV7601
Final Data Sheet
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List of Tables
Table 1-1: Pin Descriptions .............................................................................................................................. 9
Table 2-1: Absolute Maximum Ratings..................................................................................................... 16
Table 2-2: Recommended Operating Conditions................................................................................. 16
Table 2-3: DC Electrical Characteristics..................................................................................................... 17
Table 2-4: AC Electrical Characteristics..................................................................................................... 19
Table 4-1: Typical Cable Length Performance ....................................................................................... 32
Table 4-2: Serial Digital Output ................................................................................................................... 33
Table 4-3: PLL Loop Bandwidth .................................................................................................................. 34
Table 4-4: Input Clock Requirements........................................................................................................ 35
Table 4-5: Lock Detect Conditions ............................................................................................................. 36
Table 4-6: 525/60Hz Format ......................................................................................................................... 37
Table 4-7: 625/50Hz Format ......................................................................................................................... 39
Table 4-8: 1080-line Interlaced Horizontal Timing............................................................................... 41
Table 4-9: 1080-line Progressive Horizontal Timing............................................................................ 43
Table 4-10: 720p Horizontal Timing .......................................................................................................... 43
Table 4-11: Full HD 1080-line and 720-line Progressive Image Formats...................................... 44
Table 4-12: 1080p Y'C'BC'R 4:2:0 & 4:2:2 10-bit Bit Structure Mapping.......................................... 45
Table 4-13: 1080p R'G'B' or Y'C'BC'R 4:4:4 10-bit Bit Structure Mapping....................................... 46
Table 4-14: 1080p R'G'B' or Y'C'BC'R 4:4:4 12-bit Bit Structure Mapping....................................... 48
Table 4-15: 1080p Y'C'BC'R 4:2:2 12-bit Bit Structure Mapping ........................................................ 49
Table 4-16: 720p R'G'B' or Y'C'BC'R 4:4:4 10-bit Bit Structure Mapping ......................................... 50
Table 4-17: GV7601 Output Video Data Format Selections.............................................................. 53
Table 4-18: GV7601 PCLK Output Rates................................................................................................... 55
Table 4-19: Output Signals Available on Programmable Multi-Function Pins .......................... 58
Table 4-20: Supported CEA-861 Formats ................................................................................................ 61
Table 4-21: Supported Video Standard Codes ...................................................................................... 73
Table 4-22: Video Error Status Register and Error Disable Mask Bits............................................. 77
Table 4-23: PROC_DISABLE Register Bits ................................................................................................. 83
Table 4-24: Serial Audio Pin Descriptions................................................................................................ 90
Table 4-25: Audio Output Formats ............................................................................................................ 92
Table 4-26: Audio Data Packet Detect Register..................................................................................... 94
Table 4-27: Audio Group DID Host Interface Settings ........................................................................ 95
Table 4-28: Audio Data and Control Packet DID Setting Register .................................................. 95
Table 4-29: Audio Channel Mapping Codes........................................................................................... 97
Table 4-30: Audio Sample Word Lengths................................................................................................ 97
Table 4-31: Audio Channel Status Information Registers.................................................................. 99
Table 4-31: Audio Channel Status Block for Regenerate Mode Default Settings ..................... 99
Table 4-32: Audio Mute Control Bits ....................................................................................................... 100
Table 4-34: GV7601 GSPI Electrical Characteristics ............................................................................ 104
Table 4-33: Video Core Configuration and Status Registers........................................................... 105
Table 4-34: SD Audio Core Configuration and Status Registers.................................................... 113
Table 4-35: HD Audio Core Configuration and Status Registers................................................... 125
Table 4-36: Ancillary Data Extraction Memory Access Registers .................................................. 138
Table 6-1: Packaging Data........................................................................................................................... 143
GV7601
Final Data Sheet
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List of Figures
Figure A: GV7601 Block Diagram....................................................................................................................2
Figure 3-1: Digital Input Pin with Schmitt Trigger (20BIT/10BIT, AUDIO_EN, CS_TMS, PROC_EN,
JTAG_EN, RECLK_EN, RESET, SCLK_TCK, SDIN_TDI, SDO_EN, STANDBY, 861_EN) ................... 28
Figure 3-2: Bidirectional Digital Input/Output Pin - Configured to Output unless in Reset Mode.
(ACLK, MCLK, AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8, ASI, 656_BYPASS, WCLK) .................. 28
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength. ....... 29
Figure 3-4: XTAL1/XTAL2/XTAL_OUT ....................................................................................................... 29
Figure 3-5: VBG .................................................................................................................................................. 30
Figure 3-6: LB_CONT ....................................................................................................................................... 30
Figure 3-7: Loop Filter (LF) ............................................................................................................................ 30
Figure 3-8: Serial Input Equivalent Circuit ............................................................................................... 31
Figure 3-9: SDO/SDO ....................................................................................................................................... 31
Figure 4-1: 27MHz Clock Sources ............................................................................................................... 35
Figure 4-2: Data transmitting with blanking, 525/60Hz ..................................................................... 38
Figure 4-3: Multiplexing 10-bit 4:2:2 YCbCr data for 525 lines at 60Hz ........................................ 38
Figure 4-4: Data transmitting with blanking, 625/50Hz ..................................................................... 39
Figure 4-5: Multiplexing 10-bit 4:2:2 YCbCr data for 625 lines at 50Hz ........................................ 39
Figure 4-6: Field Timing Relationship for 1080-line Interlaced Systems ...................................... 40
Figure 4-7: Multiplexed Luma and Chroma Over One Video Line - 1080i ................................... 40
Figure 4-8: Luma Stream Over One Video Line - 1080i ....................................................................... 41
Figure 4-9: Chroma Stream Over One Video Line - 1080i .................................................................. 41
Figure 4-10: Frame Timing Relationship For 1080-line Progressive Systems ............................. 42
Figure 4-11: Multiplexed Luma and Chroma Over One Video Line - 1080p ............................... 42
Figure 4-12: Luma Stream Over One Video Line - 1080p .................................................................. 42
Figure 4-13: Chroma Stream Over One Video Line - 1080p .............................................................. 42
Figure 4-14: 720p Digital Vertical Timing ................................................................................................ 43
Figure 4-15: Aviia 20-bit Mapping Structure for 1920 x 1080 50/60Hz Progressive 4:2:0 & 4:2:2
(Y‘C‘BC‘R) 8/10-bit Signals .............................................................................................................................. 45
Figure 4-16: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz Progressive 4:4:4 (R‘G‘B‘)
8/10-bit Signals ................................................................................................................................................. 46
Figure 4-17: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz Progressive 4:4:4 (R‘G‘B‘
or Y‘C‘BC‘R) 12-bit Signals .............................................................................................................................. 47
Figure 4-18: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz Progressive 4:2:2 (Y‘C‘BC‘R)
12-bit Signals ..................................................................................................................................................... 48
Figure 4-19: Aviia 20-bit Mapping Structure for 1280 x 720 24/25/30/25/60Hz Progressive 4:4:4
(R‘G‘B‘ or Y‘C‘BC‘R) 8/10-bit Signals ............................................................................................................ 49
Figure 4-20: PCLK to Data and Control Signal Output Timing - SDR Mode 1 ............................. 51
Figure 4-21: PCLK to Data and Control Signal Output Timing - SDR Mode 2 ............................. 52
Figure 4-22: PCLK to Data and Control Signal Output Timing - DDR Mode ............................... 53
Figure 4-23: DDR Video Interface ............................................................................................................... 56
Figure 4-24: Delay Adjustment Ranges .................................................................................................... 57
Figure 4-25: H:V:F Output Timing - Full HD 20-bit Output Mode ................................................... 59
Figure 4-26: H:V:F Output Timing - HD 20-bit Output Mode ............................................................ 59
Figure 4-27: H:V:F Output Timing - HD & Full HD 10-bit Output Mode ........................................ 60
Figure 4-28: H:V:F Output Timing - SD 20-bit Output Mode ............................................................ 60
Figure 4-29: H:V:F Output Timing - SD 10-bit Output Mode ............................................................ 60
Figure 4-30: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ..................................... 62
Figure 4-31: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) .................................... 63
Figure 4-32: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6 & 7) .................... 64
Figure 4-33: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................... 65
Figure 4-34: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) .............................................. 66
Figure 4-35: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ............................. 67
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Figure 4-36: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) ................................ 68
Figure 4-37: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) ............................................. 69
Figure 4-38: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) ................................ 70
Figure 4-39: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) ............................................. 71
Figure 4-40: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) ................................ 72
Figure 4-41: Ancillary Data Packets ........................................................................................................... 79
Figure 4-42: Y/1ANC and C/2ANC Signal Timing - HD 20-bit ........................................................... 80
Figure 4-43: Y/1ANC and C/2ANC Signal Timing - HD 10-bit ........................................................... 80
Figure 4-44: Y/1ANC and C/2ANC Signal Timing - SD 20-bit ............................................................ 81
Figure 4-45: Y/1ANC and C/2ANC Signal Timing - SD 10-bit ............................................................ 81
Figure 4-46: Ancillary Data Extraction - Step A ...................................................................................... 86
Figure 4-47: Ancillary Data Extraction - Step B ...................................................................................... 87
Figure 4-48: Ancillary Data Extraction - Step C ...................................................................................... 88
Figure 4-49: Ancillary Data Extraction - Step D ..................................................................................... 89
Figure 4-50: ACLK to Data and WCLK Signal Output Timing ............................................................ 91
Figure 4-51: I2S Audio Output Format ...................................................................................................... 92
Figure 4-52: AES/EBU or S/PDIF Audio Output Format ...................................................................... 92
Figure 4-53: Serial Audio, Left Justified, MSB First ............................................................................... 93
Figure 4-54: Serial Audio, Left Justified, LSB First ................................................................................. 93
Figure 4-55: Serial Audio, Right Justified, MSB First ............................................................................ 93
Figure 4-56: Serial Audio, Right Justified, LSB First .............................................................................. 93
Figure 4-57: AES/EBU or S/PDIF Audio Output to Bit Clock Timing ............................................... 93
Figure 4-58: ECC 24-bit Array and Examples .......................................................................................... 96
Figure 4-59: GSPI Application Interface Connection .........................................................................101
Figure 4-60: Command Word Format .....................................................................................................101
Figure 4-61: Data Word Format .................................................................................................................102
Figure 4-62: Write Mode ..............................................................................................................................103
Figure 4-63: Read Mode ...............................................................................................................................103
Figure 4-64: GV7601 GSPI Timing Delays ..............................................................................................104
Figure 4-65: In-Circuit JTAG ........................................................................................................................139
Figure 4-66: System JTAG ............................................................................................................................139
Figure 4-67: Reset Pulse ...............................................................................................................................140
Figure 6-1: GV7601 Package Dimensions ..............................................................................................142
Figure 6-2: GV7601 Marking Diagram ....................................................................................................143
Figure 6-3: Pb-free Solder reflow Profile ................................................................................................144
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1. Pin Out
1.1 Pin Assignment
1
2
3
4
5
6
7
8
A
VBG
LF
LB_
CONT
VCO_
VDD
STAT0
STAT1
IO_VDD
PCLK
B
AVDD
PLL_
VDD
RSV
VCO_
GND
STAT2
STAT3
IO_GND DOUT19 DOUT16 DOUT15
C
SDI
AGND
PLL_
VDD
PLL_
VDD
STAT4
STAT5
RESET
D
SDI
AGND
AGND
PLL_
GND
CORE_
GND
CORE_
VDD
RSV
JTAG_
EN
IO_GND
E
EQ_
VDD
EQ_
GND
AGND
PLL_
GND
CORE_
GND
CORE_
VDD
SDOUT_
TDO
SDIN_
TDI
DOUT10 DOUT11
F
AGC
RSV
AGND
PLL_
GND
CORE_
GND
CORE_
VDD
CS_
TMS
SCLK_
TCK
DOUT8
DOUT9
G
AGC
AGND
RECLK_
EN
CORE_
GND
CORE_
GND
CORE_
VDD
656_
BYPASS
ASI
IO_GND
IO_VDD
H
BUFF_
VDD
BUFF_
GND
AUDIO_
EN
WCLK
861_EN
XTAL_
OUT
20BIT/
10BIT
PROC_
EN
DOUT6
DOUT7
J
SDO
SDO_EN AOUT1/2
ACLK
AOUT5/6
XTAL2
IO_GND
DOUT1
DOUT4
DOUT5
K
SDO
MCLK
AOUT7/8
XTAL1
IO_VDD
DOUT0
DOUT2
DOUT3
STAND
BY
AOUT3/4
9
10
DOUT18 DOUT17
DOUT12 DOUT14 DOUT13
IO_VDD
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Type
A1
VBG
Analog Input
Band Gap voltage filter connection.
A2
LF
Analog Input
Loop Filter component connection.
A3
LB_CONT
Analog Input
Connection for loop bandwidth control resistor.
GV7601
Final Data Sheet
GENDOC-052155
Description
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
A4
VCO_VDD
Input Power
Description
POWER pin for the VCO. Connect to 1.2V DC analog through an RC filter
(see 5. References & Relevant Standards). VCO_VDD is nominally 0.7V (Do not
connect directly to 0.7V).
MULTI-FUNCTIONAL OUTPUT PORT.
Signal levels are LVCMOS/LVTTL compatible.
Each of the STAT[5:0] pins can be configured individually to output one of the
following signals:
A5, A6, B5,
B6, C5, C6
STAT[0:5]
Output
A7, D10,
G10, K7
IO_VDD
Input Power
Signal
Default
H/HSYNC
V/VSYNC
F/DE
LOCKED
Y/1ANC
C/2ANC
DATA_ERROR
VIDEO_ERROR
AUDIO_ERROR
EDH_DETECTED
CARRIER_DETECT
RATE_DET0
RATE_DET1
STAT0
STAT1
STAT2
STAT3
STAT4
−
STAT5
−
−
−
−
−
−
POWER connection for digital I/O. Connect to 3.3V or 1.8V DC digital.
PARALLEL DATA BUS CLOCK - Signal levels are LVCMOS/LVTTL compatible.
A8
GV7601
Final Data Sheet
GENDOC-052155
PCLK
Full HD 10-bit or 20-bit mode
PCLK @ 148.5 or 148.5/1.001MHz
HD 10-bit mode
PCLK @ 148.5 or 148.5/1.001MHz
HD 20-bit mode
PCLK @ 74.25 or 74.25/1.001MHz
SD 10-bit mode
PCLK @ 27MHz
SD 20-bit mode
PCLK @ 13.5MHz
Output
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
Description
PARALLEL DATA BUS - Signal levels are LVCMOS/LVTTL compatible.
Video mode
(656_BYPASS = HIGH and ASI = LOW):
Luma data output for SD and HD data rates;
Data Stream 1 for Full HD at 148.5MHz
20-bit mode
20BIT/10BIT = HIGH
ASI mode
(656_BYPASS = LOW and ASI = HIGH):
Not defined
Data-Through mode
(656_BYPASS = LOW and ASI = LOW):
Data output
B8, A9, A10,
B9, B10,C9,
C10, C8, E10,
E9
DOUT[19:10]
Output
Video mode
(656_BYPASS = HIGH and ASI = LOW):
Multiplexed Luma/Chroma data output for SD
and HD data rates; Multiplexed Data Stream
1/2 for Full HD at 148.5MHz
10-bit mode
20BIT/10BIT = LOW
ASI mode
(656_BYPASS = LOW and ASI = HIGH):
8b/10b decoded transport stream data
Data-Through mode
(656_BYPASS = LOW and ASI = LOW):
Data output
Video mode
(656_BYPASS = HIGH and
ASI = LOW)
Luma data output for SD and HD data rates;
Data Stream 1 for Full HD at 148.5MHz (20-bit
mode)
ASI mode
(656_BYPASS = LOW and
ASI = HIGH)
Transport stream output
Data-Through mode
(656_BYPASS = LOW and
ASI = LOW)
Data output
B1
AVDD
Input Power
POWER pin for analog circuitry. Connect to 3.3V DC analog.
B2, C3, C4
PLL_VDD
Input Power
POWER pins for the Reclocker PLL. Connect to 1.2V DC analog.
B3, F2
RSV
B4
VCO_GND
Input Power
GND pin for the VCO. Connect to analog GND.
B7, D9, G9,
J7
IO_GND
Input Power
GND connection for digital I/O. Connect to digital GND.
C1, D1
SDI, SDI
Analog Input
Serial Digital Differential Input.
C2, D2, D3,
E3, F3, G2
AGND
Input Power
GND pins for sensitive analog circuitry. Connect to analog GND.
GV7601
Final Data Sheet
GENDOC-052155
These pins must be left unconnected.
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to reset
the JTAG sequence.
Normal mode (JTAG_EN = LOW):
C7
RESET
Input
When LOW, all functional blocks are set to default conditions and all digital
output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG_EN = HIGH):
When LOW, all functional blocks are set to default and the JTAG test sequence
is reset.
When HIGH, normal operation of the JTAG test sequence resumes.
D4, E4, F4
PLL_GND
Input Power
GND pins for the Reclocker PLL. Connect to analog GND.
D5, E5, F5,
G4, G5
CORE_GND
Input Power
GND connection for device core. Connect to digital GND.
D6, E6, F6,
G6
CORE_VDD
Input Power
POWER connection for device core. Connect to 1.2V DC digital.
D7
RSV
Input
Connect to core ground.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
D8
JTAG_EN
Input
Used to select JTAG test mode or host interface mode.
When JTAG_EN is HIGH, the host interface port is configured for JTAG test.
When JTAG_EN is LOW, normal operation of the host interface port resumes.
E1
EQ_VDD
Input Power
POWER pin for SDI input. Connect to 3.3V DC analog.
E2
EQ_GND
Input Power
GND pin for SDI input. Connect to analog GND.
COMMUNICATION SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
GSPI serial data output/test data out.
E7
SDOUT_TDO
Output
In JTAG mode (JTAG_EN = HIGH), this pin is used to shift test results from the
device.
In host interface mode, this pin is used to read status and configuration data
from the device.
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
GSPI serial data in/test data in.
E8
SDIN_TDI
Input
In JTAG mode (JTAG_EN = HIGH), this pin is used to shift test data into the
device.
In host interface mode, this pin is used to write address and configuration data
words into the device.
F1, G1
GV7601
Final Data Sheet
GENDOC-052155
AGC, AGC
Automatic Gain Control. Attach the AGC capacitor across these pins.
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
Description
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip select / test mode start.
F7
CS_TMS
Input
In JTAG mode (JTAG_EN = HIGH), this pin is Test Mode Start, used to control the
operation of the JTAG test.
In host interface mode (JTAG_EN = LOW), this pin operates as the host
interface chip select and is active LOW.
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial data clock signal.
F8
SCLK_TCK
Input
In JTAG mode (JTAG_EN = HIGH), this pin is the JTAG clock.
In host interface mode (JTAG_EN = LOW), this pin is the host interface serial bit
clock.
All JTAG/host interface addresses and data are shifted into/out of the device
synchronously with this clock.
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
F10, F9, H10,
H9, J10, J9,
K10, K9, J8,
K8
Video mode
(656_BYPASS = HIGH and ASI = LOW):
Chroma data output for SD and HD data rates;
Data Stream 2 for Full HD at 148.5MHz
DOUT[9:0]
Output
20-bit mode
20BIT/10BIT = HIGH
ASI mode
(656_BYPASS = LOW and ASI = HIGH):
Not defined
Data-Through mode
(656_BYPASS = LOW and ASI = LOW):
Data output
10-bit mode
20BIT/10BIT = LOW
Forced LOW
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
G3
GV7601
Final Data Sheet
GENDOC-052155
RECLK_EN
Input
When this pin is LOW, the serial digital output is the buffered version of the
input serial data. When this pin is HIGH, the serial digital output is the
reclocked version of the input serial data.
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
Description
CONTROL SIGNAL INPUT/OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Indicates the presence or valid video data.
When the AUTO/MAN bit in the host interface register is HIGH (Default), this
pin is an OUTPUT. 656_BYPASS is HIGH when the device locks to a ITU-R BT.656
or BT.1120 compliant input. 656_BYPASS is LOW under all other conditions.
G7
656_BYPASS
Input/Output
When the AUTO/MAN bit in the host interface register is LOW, this pin is an
INPUT.
No video data descrambling takes place, and none of the video processing
features of the device are available when 656_BYPASS is set LOW.
When 656_BYPASS is set HIGH, the device carries out descrambling and video
processing.
When 656_BYPASS and ASI are both set LOW, the device operates in
Data-Through mode.
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS/LVTTL compatible.
Used to enable/disable ASI data extraction in manual mode.
G8
ASI
Input/Output
When the AUTO/MAN bit in the host interface is LOW, this pin is an input, and
when the ASI pin is set HIGH the device carries out ASI data extraction and
processing. The 656_BYPASS pin must be set LOW. When 656_BYPASS and ASI
are both set LOW, the device operates in Data-Through mode.
When the AUTO/MAN bit in the host interface is HIGH (Default), ASI input is not
supported.
H1
BUFF_VDD
Input Power
POWER pin for the serial digital output 50Ω buffer. Connect to 3.3V DC analog.
H2
BUFF_GND
Input Power
GND pin for the cable driver buffer. Connect to analog GND.
H3
AUDIO_EN
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Enables or disables audio extraction.
H4
WCLK
Output
48kHz word clock for Audio.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
H5
861_EN
Input
Used to select CEA-861 timing mode.
When 861_EN is HIGH, the device outputs CEA-861 timing signals
(HSYNC/VSYNC/DE) instead of H:V:F digital timing signals.
H6
XTAL_OUT
Digital
Output
Buffered 27MHz crystal output. Can be used to cascade the crystal signal.
CONTROL SIGNAL INPUT
Levels are LVCMOS/LVTTL compatible.
H7
20BIT/10BIT
Input
Used to select the output bus width.
HIGH = 20-bit
LOW = 10-bit
GV7601
Final Data Sheet
GENDOC-052155
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Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Type
Description
CONTROL SIGNAL INPUT
Levels are LVCMOS/LVTTL compatible.
H8
PROC_EN
Input
Used to enable or disable audio and video processing features. When
PROC_EN is HIGH, the audio and video processing features of the device are
enabled. When PROC_EN is LOW, the processing features of the device are
disabled, and the device is in a low-latency operating mode.
Serial Data Output Signal.
J1, K1
SDO, SDO
Output
50Ω CML buffer for interfacing to an external cable driver.
Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable/disable the serial digital output stage.
J2
SDO_EN
Input
When SDO_EN is LOW, the serial digital output signals, SDO and SDO, are both
pulled HIGH.
When SDO_EN is HIGH, the serial digital output signals, SDO and SDO, are
enabled.
J3
AOUT1/2
Output
Serial Audio Output; Channels 1 and 2.
J4
ACLK
Output
64fs sample clock for audio.
J5
AOUT5/6
Output
Serial Audio Output; Channels 5 and 6.
J6, K6
XTAL2, XTAL1
Analog Input
Input connection for 27MHz crystal.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
K2
STANDBY
Input
When this pin is set HIGH, the device is placed in a power-saving mode. No
data processing occurs, and the digital I/Os are powered down.
In this mode, the serial digital output signals, SDO and SDO, are both pulled
HIGH.
K3
AOUT3/4
Output
Serial Audio Output; Channels 3 and 4.
K4
MCLK
Output
Oversampled master clock for audio (128fs, 256fs, 512fs selectable).
K5
AOUT7/8
Output
Serial Audio Output; Channels 7 and 8.
GV7601
Final Data Sheet
GENDOC-052155
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings
Parameter
Value/Units
Supply Voltage, Digital Core (CORE_VDD)
-0.3V to +1.5V
Supply Voltage, Digital I/O (IO_VDD)
-0.3V to +4.0V
Supply Voltage, Analog 1.2V (PD_VDD, VCO_VDD)
-0.3V to +1.5V
Supply Voltage, Analog 3.3V (EQ_VDD, BUFF_VDD,
AVDD)
-0.3V to +4.0V
Input Voltage Range (SDI, SDI, LB_CONT)
-0.3V to (EQ_VDD + 0.3)V
Input Voltage Range (VBG)
-0.3V to (AVDD + 0.3)V
Input Voltage Range (LF)
-0.3V to (PLL_VDD + 0.3)V
Input Voltage Range (digital inputs)
-2.0V to +5.25V
Ambient Operating Temperature (TA)
-40°C to 95°C
Storage Temperature (TSTG)
-40°C to 125°C
Peak Reflow Temperature (JEDEC J-STD-020C)
260°C
ESD Sensitivity, HBM (JESD22-A114)
2kV
Note:
Absolute Maximum Ratings are those values beyond which damage may occur. Functional
operation under these conditions or at any other condition beyond those indicated in the
AC/DC Electrical Characteristics sections is not implied.
2.2 Recommended Operating Conditions
Table 2-2: Recommended Operating Conditions
Parameter
Symbol
Operating Temperature Range,
Ambient
Supply Voltage, Digital Core
Supply Voltage, Digital I/O
Supply Voltage, PLL
GV7601
Final Data Sheet
GENDOC-052155
Conditions
Min
Typ
Max
Units
Notes
TA
–
-20
−
85
°C
−
CORE_VDD
–
1.14
1.2
1.26
V
−
1.8V mode
1.71
1.8
1.89
V
−
3.3V mode
3.13
3.3
3.47
V
−
–
1.14
1.2
1.26
V
–
IO_VDD
PLL_VDD
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Table 2-2: Recommended Operating Conditions (Continued)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Supply Voltage, VCO
VCO_VDD
–
−
0.7
−
V
1
AVDD
–
3.13
3.3
3.47
V
2
EQ_VDD
–
3.13
3.3
3.47
V
–
BUFF_VDD
–
3.13
3.3
3.47
V
2
Supply Voltage, Analog
Supply Voltage, Serial Digital Input
Supply Voltage, CD Buffer
Notes:
1. This is 0.7V rather than 1.2V because there is a voltage drop across an external 105Ω resistor.
2. The 3.3V supplies must track the 3.3V supply of an external cable driver.
2.3 DC Electrical Characteristics
Table 2-3: DC Electrical Characteristics
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
10-bit Full HD
−
220
265
mA
−
20-bit Full HD
−
210
265
mA
−
10/20-bit HD
−
170
220
mA
−
10/20-bit SD
−
140
185
mA
−
ASI
−
130
170
mA
−
10-bit Full HD
−
37
45
mA
−
20-bit Full HD
−
16
20
mA
−
10/20-bit HD
−
15
21
mA
−
10/20-bit SD
−
4
7
mA
−
ASI
−
4
6
mA
−
10-bit Full HD
−
150
180
mA
−
20-bit Full HD
−
115
130
mA
−
10/20-bit HD
−
110
135
mA
−
10/20-bit SD
−
90
100
mA
−
ASI
−
90
95
mA
−
System
+1.2V Supply Current
+1.8V Supply Current
+3.3V Supply Current
GV7601
Final Data Sheet
GENDOC-052155
I1V2
I1V8
I3V3
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Table 2-3: DC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Total Device Power
(IO_VDD = 1.8V)
Total Device Power
(IO_VDD = 3.3V)
P1D8
P3D3
Conditions
Min
Typ
Max
Units
Notes
10-bit Full HD
−
560
680
mW
−
20-bit Full HD
−
525
640
mW
−
10/20-bit HD
−
480
590
mW
−
10/20-bit SD
−
420
520
mW
−
ASI
−
410
500
mW
−
Reset
−
390
−
mW
−
Standby
−
23
45
mW
−
10-bit Full HD
−
750
930
mW
−
20-bit Full HD
−
620
760
mW
−
10/20-bit HD
−
570
830
mW
−
10/20-bit SD
−
460
560
mW
−
ASI
−
440
540
mW
−
Reset
−
410
−
mW
−
Standby
−
23
45
mW
−
Digital I/O
Input Logic LOW
VIL
3.3V or 1.8V operation
IO_GND
- 0.3
–
0.3 x
IO_VDD
V
–
Input Logic HIGH
VIH
3.3V or 1.8V operation
0.7 x
IO_GND
–
IO_VDD
+ 0.3
V
–
–
0.2
V
–
VOL
IOL = 5mA, 1.8V operation
–
Output Logic LOW
IOL = 8mA, 3.3V operation
–
–
0.4
V
–
IOH = 5mA, 1.8V operation
1.4
–
–
V
–
IOH = 8mA, 3.3V operation
2.4
–
–
V
–
Output Logic HIGH
Output Drive Strength
VOH
−
−
−
−
−
−
1
−
75Ω load
−
2.2
−
V
–
−
50Ω load
BUFF_VDD
- (0.6 / 2)
BUFF_VDD
- (0.45 / 2)
BUFF_VDD
- (0.35 / 2)
V
−
Serial Input
Serial Input Common
Mode Voltage
Serial Output
Serial Output
Common Mode
Voltage
Notes:
1. The output drive strength of the digital outputs can be programmed through the host interface. Please see Table 4-33: Video Core Configuration
and Status Registers, register 06Dh for details.
GV7601
Final Data Sheet
GENDOC-052155
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2.4 AC Electrical Characteristics
Table 2-4: AC Electrical Characteristics
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
treset
–
1
–
–
ms
–
Full HD (Audio Enabled)
–
PCLK = 148.5MHz
79
–
83
PCLK
1
HD (Audio Enabled)
–
PCLK = 74.25MHz
79
–
83
PCLK
1
SD (Audio Enabled)
–
PCLK = 27MHz
50
–
59
PCLK
1
Full HD (Audio Disabled)
–
PCLK = 148.5MHz
44
–
48
PCLK
2
HD (Audio Disabled)
–
PCLK = 74.25MHz
44
–
48
PCLK
2
SD (Audio Disabled)
–
PCLK = 27MHz
44
–
53
PCLK
2
ASI Mode
–
PCLK = 27MHz
12
–
16
PCLK
3
System
Reset Pulse Width
Device Latency
Parallel Output
Parallel Clock Frequency
fPCLK
–
13.5
–
148.5
MHz
–
Parallel Clock Duty Cycle
DCPCLK
–
40
–
60
%
–
GV7601
Final Data Sheet
GENDOC-052155
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Full HD
10-bit
Full HD
20-bit
Output Data Hold Time (1.8V)
toh
Min
Typ
Max
Units
Notes
SPI
1.5
–
–
ns
4
Audio
Outputs
1.5
–
–
ns
4
Video
Data Bus
0.4
–
–
ns
4
STAT
Pins
0.45
–
–
ns
4
Video
Data Bus
1.0
–
–
ns
4
STAT
Pins
1.0
–
–
ns
4
Video
Data Bus
1.0
–
–
ns
4
STAT
Pins
1.0
–
–
ns
4
Video
Data Bus
1.0
–
–
ns
4
STAT
Pins
1.0
–
–
ns
4
Video
Data Bus
19.4
–
–
ns
4
STAT
Pins
19.4
−
–
ns
4
Video
Data Bus
38.0
−
–
ns
4
STAT
Pins
38.0
−
–
ns
4
HD 10-bit
HD 20-bit
SD 10-bit
SD 20-bit
GV7601
Final Data Sheet
GENDOC-052155
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Full HD
10-bit
Full HD
20-bit
Output Data Hold Time (3.3V)
toh
Min
Typ
Max
Units
Notes
SPI
1.5
–
–
ns
5
Audio
Outputs
1.5
–
–
ns
5
Video
Data Bus
0.45
–
–
ns
5
STAT
Pins
0.45
–
–
ns
5
Video
Data Bus
1.0
–
–
ns
5
STAT
Pins
1.0
–
–
ns
5
Video
Data Bus
1.0
–
–
ns
5
STAT
Pins
1.0
–
–
ns
5
Video
Data Bus
1.0
–
–
ns
5
STAT
Pins
1.0
–
–
ns
5
Video
Data Bus
19.4
–
–
ns
5
STAT
Pins
19.4
–
–
ns
5
Video
Data Bus
38.0
–
–
ns
5
STAT
Pins
38.0
–
–
ns
5
HD 10-bit
HD 20-bit
SD 10-bit
SD 20-bit
GV7601
Final Data Sheet
GENDOC-052155
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Full HD
10-bit
Full HD
20-bit
Output Data Delay Time (1.8V)
tod
Min
Typ
Max
Units
Notes
SPI
–
–
14.0
ns
6
Audio
Outputs
–
–
7.0
ns
6
Video
Data Bus
–
–
1.8
ns
6
STAT
Pins
–
–
2.5
ns
6
Video
Data Bus
–
–
3.7
ns
6
STAT
Pins
–
–
4.4
ns
6
Video
Data Bus
–
–
3.7
ns
6
STAT
Pins
–
–
4.4
ns
6
Video
Data Bus
–
–
3.7
ns
6
STAT
Pins
–
–
4.4
ns
6
Video
Data Bus
–
–
22.2
ns
6
STAT
Pins
–
–
22.2
ns
6
Video
Data Bus
–
–
41.0
ns
6
STAT
Pins
–
–
41.0
ns
6
HD 10-bit
HD 20-bit
SD 10-bit
SD 20-bit
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Full HD
10-bit
Full HD
20-bit
Output Data Delay Time (3.3V)
tod
Min
Typ
Max
Units
Notes
SPI
–
–
14.0
ns
7
Audio
Outputs
–
–
7.0
ns
7
Video
Data Bus
–
–
1.9
ns
7
STAT
Pins
–
–
2.2
ns
7
Video
Data Bus
–
–
3.7
ns
7
STAT
Pins
–
–
4.1
ns
7
Video
Data Bus
–
–
3.7
ns
7
STAT
Pins
–
–
4.1
ns
7
Video
Data Bus
–
–
3.7
ns
7
STAT
Pins
–
–
4.1
ns
7
Video
Data Bus
–
–
22.2
ns
7
STAT
Pins
–
–
22.2
ns
7
Video
Data Bus
–
–
41.0
ns
7
STAT
Pins
–
–
41.0
ns
7
HD 10-bit
HD 20-bit
SD 10-bit
SD 20-bit
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Full HD
10-bit
6pF load
All other
modes
6pF load
Output Data Rise/Fall Time (1.8V)
All other
modes
15pF load
Full HD
10-bit
6pF load
Max
Units
Notes
Video
Data Bus
0.4
–
–
ns
4
STAT
Pins
0.3
–
–
ns
4
Audio
Outputs
0.6
–
–
ns
4
Video
Data Bus
0.4
–
–
ns
4
STAT
Pins
0.4
–
–
ns
4
Audio
Outputs
0.6
–
–
ns
4
Video
Data Bus
–
–
1.5
ns
6
STAT
Pins
–
–
1.1
ns
6
Audio
Outputs
–
–
2.3
ns
6
Video
Data Bus
–
–
1.5
ns
6
STAT
Pins
–
–
1.4
ns
6
Audio
Outputs
–
–
2.3
ns
6
Video
Data Bus
0.5
–
–
ns
5
STAT
Pins
0.4
–
–
ns
5
Audio
Outputs
0.6
–
–
ns
5
Video
Data Bus
0.5
–
–
ns
5
STAT
Pins
0.4
–
–
ns
5
Audio
Outputs
0.6
–
–
ns
5
tr/tf
All other
modes
6pF load
GV7601
Final Data Sheet
GENDOC-052155
Typ
tr/tf
Full HD
10-bit
15pF load
Output Data Rise/Fall Time (3.3V)
Min
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Notes
Video
Data Bus
–
–
1.6
ns
7
STAT
Pins
–
–
1.5
ns
7
Audio
Outputs
–
–
2.2
ns
7
Video
Data Bus
–
–
1.6
ns
7
STAT
Pins
–
–
1.4
ns
7
Audio
Outputs
–
–
2.2
ns
7
–
0.27
–
2.97
Gb/s
–
TA=25°C, differential,
270Mb/s & 1.485Gb/s
720
800
950
mVp-p
9
TA=25°C, differential,
2.97Gb/s
720
800
880
mVp-p
9
Belden
1694A
cable
–
150
–
m
–
Belden
RG59
cable
–
100
–
m
–
Belden
1694A
cable
–
230
–
m
–
Belden
RG59
cable
–
160
–
m
–
Belden
1694A
cable
–
460
–
m
–
Belden
RG59
cable
–
330
–
m
–
Full HD
10-bit
15pF load
Output Data Rise/Fall Time (3.3V)
tr/tf
All other
modes
15pF load
Serial Digital Input
Serial Input Data Rate
Serial Input Swing
DRSDI
ΔVSDI
Full HD
Achievable Cable Length
–
HD
SD
Input Return Loss
–
single-ended
15
21
–
dB
10
Input Resistance
–
single-ended
–
1.52
–
kΩ
–
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
Input Capacitance
–
Conditions
single-ended
Min
Typ
Max
Units
Notes
–
1
–
pF
–
Serial Digital Output
Serial Output Data Rate
DRSDO
−
0.27
−
2.97
Gb/s
−
Serial Output Swing
ΔVSDO
Differential
with 100Ω
load
320
−
600
mVp-p
–
Serial Output Rise Time
20% ~ 80%
trSDO
–
–
–
180
ps
–
Serial Output Fall Time
20% ~ 80%
tfSDO
–
–
–
180
ps
–
Full HD
colour bar
signal
–
–
100
ps
–
HD colour
bar signal
–
–
100
ps
–
SD colour
bar signal
–
–
470
ps
–
Full HD
–
10
–
ps
–
HD
–
10
–
ps
–
SD
–
20
–
ps
–
Serial Output Intrinsic Jitter
Serial Output Duty Cycle
Distortion
tOJ
DCDSDD
Synchronous lock time
–
–
−
–
25
μs
−
Asynchronous lock time
–
–
100
–
825
μs
–
Lock time from standby
de-asserted
–
–
–
–
10
ms
–
–
–
–
–
100
ms
–
–
After 20
minutes at
-20°C
–
325
ms
–
–
–
60
MHz
8
40
50
60
%
8
1.5
–
–
ns
8
1.5
–
–
ns
8
1.5
–
–
ns
8
Lock time from power-up
GSPI
GSPI Input Clock Frequency
fSCLK
GSPI Input Clock Duty Cycle
DCSCLK
GSPI Input Data Setup Time
–
GSPI Input Data Hold Time
–
GSPI Output Data Hold Time
–
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3.3V or 1.8V
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–
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Table 2-4: AC Electrical Characteristics (Continued)
Guaranteed over recommended operating conditions unless otherwise noted.
Parameter
Symbol
CS low before SCLK rising edge
t0
Time between end of command
word (or data in Auto-Increment
mode) and the first SCLK of the
following data word - write cycle
Conditions
Min
Typ
Max
Units
Notes
50% levels
3.3V or 1.8V
operation
1.5
–
–
ns
8
t4
50% levels
3.3V or 1.8V
operation
37.1
–
–
ns
8
Time between end of command
word (or data in Auto-Increment
mode) and the first SCLK of the
following data word - read cycle
t5
50% levels
3.3V or 1.8V
operation
148.4
–
–
ns
8
CS high after SCLK rising edge
t7
50% levels
3.3V or 1.8V
operation
37.1
–
–
ns
8
Notes:
1. 656_BYPASS = 1, PROC_EN = 1, AUDIO_EN = 1, ASI = 0
2. 656_BYPASS = 1, PROC_EN = 1, AUDIO_EN = 0, ASI = 0
3. ASI = 1
4. 1.89V and 0ºC.
5. 3.47V and 0ºC.
6. 1.71V and 125ºC
7. 3.13V and 125ºC
8. For GSPI timing parameters, refer to Figure 4-62 and Figure 4-63 in Section 4.18.3, as appropriate.
9. 0m cable length.
10. Tested on GV7601 board from 5MHz to 3GHz.
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3. Input/Output Circuits
IO_VDD
200Ω
Input Pin
Figure 3-1: Digital Input Pin with Schmitt Trigger (20BIT/10BIT, AUDIO_EN,
CS_TMS, PROC_EN, JTAG_EN, RECLK_EN, RESET, SCLK_TCK, SDIN_TDI, SDO_EN,
STANDBY, 861_EN)
IO_VDD
200Ω
Output Pin
Figure 3-2: Bidirectional Digital Input/Output Pin - Configured to Output unless in
Reset Mode. (ACLK, MCLK, AOUT1/2, AOUT3/4, AOUT5/6, AOUT7/8, ASI,
656_BYPASS, WCLK)
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IO_VDD
200Ω
Output Pin
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive
strength.
These pins in Figure 3-3 are configured to output unless in Reset Mode; in which case
they are high-impedance. The drive strength can be set by writing to address 06Dh in
the host interface register. (DOUT0, DOUT1, DOUT2, DOUT3, DOUT4, DOUT5, DOUT6,
DOUT7, DOUT8, DOUT9, SDOUT_TDO, STAT0, STAT1, STAT2, STAT3, STAT4, STAT5,
XTAL_OUT, DOUT10, DOUT11, DOUT12, DOUT13, DOUT14, DOUT15, DOUT16, DOUT17,
DOUT18, DOUT19, PCLK)
XTAL1
XTAL2
XTAL_OUT
Figure 3-4: XTAL1/XTAL2/XTAL_OUT
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AVDD
2kΩ
VBG
50Ω
Figure 3-5: VBG
SDI_VDD
Out
LB_CONT
Out
Figure 3-6: LB_CONT
PLL_VDD
25Ω
LF
25Ω
Figure 3-7: Loop Filter (LF)
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4k
4k
SDI
SDI
RC
6k
6k
Figure 3-8: Serial Input Equivalent Circuit
BUFF_VDD
50Ω
50Ω
SDO
SDO
Figure 3-9: SDO/SDO
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4. Detailed Description
4.1 Functional Overview
The GV7601 is a multi-rate, multi-standard Aviia receiver with an integrated audio
de-embedder, providing a complete Aviia receive solution that supports full bandwidth
1080p video at 50/60Hz can be realized.
The GV7601 includes an integrated cable equalizer, reclocker, serial data loop through
output, robust serial-to-parallel conversion and additional processing functions such as
audio extraction, ancillary data extraction, and ASI decoding.
The device supports four distinct modes of operation that can be set through external
device pins or by programming internal registers through the host interface; Video
mode, Data-Through mode, ASI mode and Standby mode.
In Video mode, all video processing features, ancillary data extraction, and audio
de-embedding features are enabled by default.
In ASI mode, the GV7601 carries out 8b/10b decoding and outputs IEC 13818-1
compliant stream data.
In Data-Through mode, the device operates as a simple serial to parallel converter. No
additional processing features are enabled.
Standby mode is the low power consumption mode of the device. In this mode, the
internal reclocker unlocks, and the internal configuration registers are not accessible
through the host interface.
The GV7601 includes a JTAG interface for boundary scan testing.
4.2 Serial Digital Input
The GV7601 can accept serial digital inputs compliant with ITU-R BT.656, and BT.1120.
The GV7601 integrates Gennum’s next-generation state-of-the-art adaptive equalizer
technology.
Table 4-1: Typical Cable Length Performance
Data Rate
RG6 (m) or equivalent
RG59 (m) or equivalent
Full HD @ 2.97Gb/s
150
100
HD @ 1.485Gb/s
230
160
SD @ 270Mb/s
460
330
The cable equalizer can be bypassed by programming register 073h through the GSPI
interface.
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The Serial Data Signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is recommended,
as the SDI and SDI inputs are internally biased at approximately 1.8V.
4.3 Serial Digital Output
The GV7601 contains a 100Ω differential serial output buffer which can be configured
to output either a retimed or a buffered version of the serial digital input. The SDO and
SDO outputs of this buffer can interface directly to GV8500 cable driver.
When the RECLK_EN pin is set HIGH, the serial digital output is the re-timed version of
the serial input.
When the RECLK_EN pin is set LOW, the serial digital output is simply the buffered
version of the serial input, bypassing the internal reclocker.
The output may be disabled by setting the SDO_EN pin LOW. The output is also disabled
when STANDBY pin is asserted HIGH. When disabled, both SDO and SDO pins go to VDD
and remain static.
The SDO output is muted when RECLK_EN pin is set HIGH and the PLL is unlocked
(LOCKED pin is LOW). When muted, the output is held static in 0 or 1.
Table 4-2: Serial Digital Output
SDO_EN
RECLK_EN
SDO/SDO
0
X
Disabled
1
1
Re-timed
1
0
Buffered (not re-timed)
Note: The serial digital output is muted when the GV7601 is unlocked.
4.4 Serial Digital Reclocker
The GV7601 includes both a PLL stage and a sampling stage.
The PLL is comprised of two distinct loops:
•
A coarse frequency acquisition loop sets the centre frequency of the integrated
Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock
•
A fine frequency and phase locked loop aligns the VCO’s phase and frequency to
the input serial digital stream
The frequency lock loop results in very fast lock time.
The sampling stage re-times the serial digital input with the locked VCO clock. This
generates a clean serial digital stream, which may be output on the SDO/SDO output
pins and converted to parallel data for further processing.
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4.4.1 Reclocker PLL Loop Bandwidth
The fine frequency and phase lock loop in the GV7601 reclocker is non-linear. The PLL
loop bandwidth scales with the jitter amplitude of the input data stream; automatically
reduces bandwidth in response to higher jitter. This allows the PLL to reject more of the
jitter in the input data stream and produce a very clean reclocked output.
The loop bandwidth of the GV7601 PLL is defined with 0.2UI input jitter. The bandwidth
is controlled through the LB_CONT pin of the device. Under nominal conditions, with
the LB_CONT pin floating and 0.2UI input jitter applied, the loop bandwidth is set to
1/1000 of the frequency of the input data stream. Connecting the LB_CONT pin to 3.3V
reduces the bandwidth to half of the nominal setting. Connecting the LB_CONT pin to
GND increases the bandwidth to double the nominal setting. Table 4-3 below
summarizes this information.
Table 4-3: PLL Loop Bandwidth
Input Data Rate
SD
HD
Full HD
LB_CONT Pin Connection
Loop Bandwidth (MHz)1
3.3V
0.135
Floating
0.27
0V
0.54
3.3V
0.75
Floating
1.5
0V
3.0
3.3V
1.5
Floating
3.0
0V
6.0
1Measured with 0.2UI input jitter applied
4.5 External Crystal/Reference Clock
The GV7601 requires an external 27MHz reference clock for correct operation. This
reference clock is generated by connecting a crystal to the XTAL1 and XTAL2 pins of the
device.
Alternately, a 27MHz external clock source can be connected to the XTAL1 pin of the
device, as shown in Figure 4-1. The frequency variation of the crystal including aging,
supply and temperature variation, should be less than +/-100ppm.
The equivalent series resistance (or motional resistance) should be a maximum of 50Ω.
The external crystal is used in the frequency acquisition process. It has no impact on the
output jitter performance of the part when the part is locked to incoming data. Because
of this, the only key parameter is the frequency variation of the crystal that is stated
above.
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External Crystal Connection
16pF
K6 XTAL1
External Clock Source Connection
K6 XTAL1
External
Clock
J6
XTAL2
NC
J6
XTAL2
16pF
Notes: 1. Capacitor values listed represent the total capacitance,
including discrete capacitance and parasitic board capacitance.
2. XTAL1 serves as an input, which may alternatively accept a
27MHz clock source.
Figure 4-1: 27MHz Clock Sources
Table 4-4: Input Clock Requirements
Parameter
Min
Typ
Max
UOM
XTAL1 Low Level Input Voltage
(Vil)
−
−
20% of VDD_IO
V
XTAL1 High Level Input Voltage
(Vih)
80% of VDDIO
−
−
V
2
−
−
V/ns
XTAL1 to XOUT Prop. Delay
(High to Low)
1.3
1.5
2.3
ns
XTAL1 to XOUT Prop. Delay
(Low to High)
1.3
1.6
2.3
ns
XTAL1 Input Slew Rate
Notes
Note:
1. Valid when the cell is used to buffer an external clock source which is connected to the XTAL1 pin, then nothing should be connected to the XTAL2
pin.
4.6 Lock Detect
The LOCKED output signal is available by default on the STAT3 output pin, but may be
programmed to be output through any one of the six programmable multi-functional
pins of the device; STAT[5:0].
The LOCKED output signal sets HIGH by the Lock Detect block under the following
conditions:
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Table 4-5: Lock Detect Conditions
Mode of Operation
Mode Setting
Condition for Locked
Data-Through Mode
656_BYPASS = LOW
ASI = LOW
Reclocker PLL is locked.
Video Mode
656_BYPASS = HIGH
ASI = LOW
Reclocker PLL is locked
2 consecutive TRS words in 2 lines are
detected.
ASI Mode
656_BYPASS = LOW
ASI = HIGH
AUTO/MAN = LOW
Reclocker PLL is locked
32 consecutive ASI words with no
errors are detected within a 128-word
window.
All other combinations result in the LOCKED signal being LOW.
Note: In Standby mode, the reclocker PLL unlocks. However, the LOCKED signal retains
whatever status it previously held. So, if before Standby assertion, the LOCKED signal is
HIGH, then during standby, it remains HIGH regardless of the status of the PLL.
4.6.1 Asynchronous Lock
The lock detection algorithm is a continuous process, beginning at device power-up or
after a system reset. It continues until the device is powered down or held in reset.
The device first determines if a valid serial digital input signal has been presented to the
device. If no valid serial data stream has been detected, the serial data into the device is
considered invalid, and the LOCKED signal is LOW.
Once a valid input signal has been detected, the asynchronous lock algorithm enters a
“hunt” phase, in which the device attempts to detect the presence of either TRS words
or ASI sync words.
By default, the device powers up in auto mode (the AUTO/MAN bit in the host interface
is set HIGH). In this mode, the device operating frequency toggles between Full HD, HD
and SD rates as it attempts to lock to the incoming data rate. The PCLK output continues
to operate, and the frequency may switch between 148.5MHz, 74.25MHz, 27MHz and
13.5MHz.
When the device is operating in manual mode (AUTO/MAN bit in the host interface is
LOW), the operating frequency needs to be set through the host interface using the
RATE_DET[1:0] bits. In this mode, the asynchronous lock algorithm does not toggle the
operating rate of the device and attempts to lock within a single standard. Lock is
achieved within three lines of the selected standard.
4.6.2 Signal Interruption
The device tolerates a signal interruption of up to 10μs as long as no TRS words are
deleted by this interruption.
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4.7 Video Functionality
4.7.1 Standard Definition Video Output Formats
ITU-R BT.656 (formally CCIR-656) defines an 8-bit or 10-bit parallel interface for
transmitting 4:2:2 YCbCr digital video. To reduce the number of wires required for the
interface, timing codes are embedded in the video stream to provide information
traditionally transmitted by dedicated HSYNC, VSYNC, and BLANK signals. Ancillary
digital data such as audio and closed captioning may be transmitted during blanking
intervals (see Figure 4-2 and Figure 4-4). Figure 4-3 shows the multiplexed 10-bit 4:2:2
YCbCr data for 525 line video at 60Hz. Figure 4-5 shows the multiplexed 10-bit 4:2:2
YCbCr data for 625 line video at 50Hz. The start of active video and the end of active
video are marked by the SAV and EAV codes, respectively. The values of these codes are
reserved for this purpose and should not occur elsewhere in the video raster. F, V, H
timing information is stored in the 10-bit XYZ word as follows:
•
Bit 8 - (F-bit) 0 for field one; and 1 for field two
•
Bit 7 - (V-bit) 1 in vertical blanking interval; and 0 during active video lines
•
Bit 6 - (H-bit) 1 indicates the EAV sequence; and 0 indicates the SAV sequence
The two LSB's of the XYZ word are set to zero for compatibility with 8-bit systems.
Table 4-6: 525/60Hz Format
Line Number
F
V
H (EAV)
H (SAV)
1-3
1
1
1
0
4-20
0
1
1
0
21-263
0
0
1
0
264-265
0
1
1
0
266-282
1
1
1
0
283-525
1
0
1
0
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LINE
1
V=1
LINE 4
BLANKING
21
V=0
FIELD 1
(F=0) ODD
FIELD 1
ACTIVE VIDEO
V=1
LINE 266
264
BLANKING
V=0
283
FIELD 2
(F=1) EVEN
FIELD 2
ACTIVE VIDEO
525
V=0
LINE 3
H=1
EAV
H=0
SAV
Figure 4-2: Data transmitting with blanking, 525/60Hz
H CONTROL SIGNAL
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
EAV CODE
3
F
F
0
0
0
0
0
0
BLANKING
X
Y
Z
4
2
0
0
0
4
0
2
0
0
0
4
0
268
CO-SITED
SAV CODE
2
0
0
0
4
0
3
F
F
0
0
0
0
0
0
4
X
Y
Z
C
B
Y
C
R
NEXT LINE
CO-SITED
Y
C
B
Y
C
R
Y
C
R
Y
3
F
F
DIGITAL
VIDEO
STREAM
1440
1716
Figure 4-3: Multiplexing 10-bit 4:2:2 YCbCr data for 525 lines at 60Hz
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Table 4-7: 625/50Hz Format
Line Number
F
V
H (EAV)
H (SAV)
1-22
0
1
1
0
23-310
0
0
1
0
311-312
0
1
1
0
313-335
1
1
1
0
336-623
1
0
1
0
624-625
1
1
1
0
LINE 1
LINE
1
V=1
BLANKING
23
V=0
FIELD 1
(F=0) ODD
FIELD 1
ACTIVE VIDEO
V=1
311
LINE 313
BLANKING
V=0
336
FIELD 2
(F=1) EVEN
FIELD 2
ACTIVE VIDEO
624
V=1
BLANKING
LINE 625
625
V=1
H=1
EAV
H=0
SAV
Figure 4-4: Data transmitting with blanking, 625/50Hz
H CONTROL SIGNAL
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
EAV CODE
3
F
F
0
0
0
0
0
0
BLANKING
X
Y
Z
4
2
0
0
0
4
0
2
0
0
0
4
0
280
CO-SITED
SAV CODE
2
0
0
0
4
0
3
F
F
0
0
0
0
0
0
4
X
Y
Z
C
B
Y
C
R
NEXT LINE
CO-SITED
Y
C
B
Y
C
R
Y
C
R
Y
3
F
F
DIGITAL
VIDEO
STREAM
1440
1728
Figure 4-5: Multiplexing 10-bit 4:2:2 YCbCr data for 625 lines at 50Hz
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4.7.2 High Definition Video Output Formats
ITU-R BT.1120 describes the serial and parallel format for 1080-line interlaced and
progressive digital video. As with ITU-R BT.656, the field/frame blanking period (V), the
line blanking period (H), and the field identification (F), are embedded as digital timing
codes (TRS) within the video. After deserialization, a single 10-bit bus carrying the C‘B, Y‘,
C‘R, Y‘, etc. data pattern is demultiplexed into two 10-bit buses. This 20-bit parallel data
interface carries 10 bits of luma data (Y‘) and 10 bits of colour difference data (C‘B, C‘R),
operating at a clock of 74.25MHz or 74.25/1.001 MHz.
The following figures show horizontal and vertical timing for 1080-line interlaced
systems.
LINE
1
V=1
BLANKING
20
21
V=0
FIELD 1
(F=0) ODD
FIELD 1
ACTIVE VIDEO
560
561
V=1
BLANKING
563
564
BLANKING
583
584
V=0
FIELD 2
(F=1) EVEN
FIELD 2
ACTIVE VIDEO
1123
1124
V=1
BLANKING
1125
H=1
EAV
H=0
SAV
Figure 4-6: Field Timing Relationship for 1080-line Interlaced Systems
START OF DIGITAL LINE
BLANKING
NEXT LINE
3FF
3FF
CBD959
YD1918
CRD959
YD1919
3FF
3FF
000
000
000
000
XYZ
XYZ
CBD0
YD0
CRD0
YD1
CBD1
YD2
SAV CODE
CA(n-1)
YA(n-1)
3FF
3FF
000
000
000
000
XYZ
XYZ
LN0
LN0
LN1
LN1
CCR0
YCR0
CCR1
YCR1
CA0
YA0
CA1
YA1
CA2
YA2
EAV CODE
START OF DIGITAL ACTIVE LINE
MULTIPLEXED
STREAM
Figure 4-7: Multiplexed Luma and Chroma Over One Video Line - 1080i
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H CONTROL SIGNAL
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
H1
3FF
YD1919
YD1918
YD7
YD6
YD5
YD4
YD3
YD2
YD1
XYZ
YD0
000
3FF
000
SAV CODE
YA(n-1)
YA2
YA1
YA0
YCR1
LN1
YCR0
LN0
000
BLANKING
XYZ
3FF
000
EAV CODE
NEXT LINE
Y STREAM
1920
H2
Figure 4-8: Luma Stream Over One Video Line - 1080i
H CONTROL SIGNAL
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
H1
3FF
CBD959
CBD959
CBD3
CBD3
CBD2
CBD2
CBD1
CBD0
CBD1
XYZ
CBD0
000
000
3FF
SAV CODE
CA(n-1)
CA2
CA1
CA0
CCR1
CCR0
LN1
LN0
BLANKING
XYZ
000
3FF
000
EAV CODE
NEXT LINE
CB/CR STREAM
1920
H2
Figure 4-9: Chroma Stream Over One Video Line - 1080i
Table 4-8: 1080-line Interlaced Horizontal Timing
Interlaced
60 or 60/1.001 Hz
50Hz
H1
280
720
H2
2200
2640
4.7.2.1 High Definition 1080p Output Formats
ITU-R BT.1120 also includes progressive scan formats with 1080 active lines, with Y'C'BC'R
4:2:2 sampling at pixel rates of 74.25MHz or 74.25/1.001 MHz. The following diagrams
show horizontal and vertical timing for 1080-line progressive systems.
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LINE
1
V=1
BLANKING
41
V=0
42
ACTIVE VIDEO
(F=0)
1121
V=1
1122
BLANKING
1125
H=1
EAV
H=0
SAV
Figure 4-10: Frame Timing Relationship For 1080-line Progressive Systems
START OF DIGITAL LINE
START OF DIGITAL ACTIVE LINE
BLANKING
3FF
3FF
CBD959
YD1918
CRD959
YD1919
3FF
3FF
000
000
000
000
XYZ
XYZ
CBD0
YD0
CRD0
YD1
CBD1
YD2
CA(n-1)
YA(n-1)
SAV CODE
3FF
3FF
000
000
000
000
XYZ
XYZ
LN0
LN0
LN1
LN1
CCR0
YCR0
CCR1
YCR1
CA0
YA0
CA1
YA1
CA2
YA2
EAV CODE
NEXT LINE
MULTIPLEXED
STREAM
Figure 4-11: Multiplexed Luma and Chroma Over One Video Line - 1080p
H CONTROL SIGNAL
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
H1
3FF
YD1919
YD1918
YD7
YD6
YD5
YD4
YD3
YD2
YD1
XYZ
YD0
000
3FF
000
SAV CODE
YA(n-1)
YA2
YA1
YA0
YCR1
LN1
YCR0
LN0
000
BLANKING
XYZ
000
3FF
EAV CODE
NEXT LINE
Y STREAM
1920
H2
Figure 4-12: Luma Stream Over One Video Line - 1080p
H CONTROL SIGNAL
START OF DIGITAL ACTIVE LINE
START OF DIGITAL LINE
H1
3FF
CBD959
CBD959
CBD3
CBD3
CBD2
CBD2
CBD1
CBD0
CBD1
XYZ
CBD0
000
000
3FF
SAV CODE
CA(n-1)
CA2
CA1
CA0
CCR1
CCR0
LN1
LN0
BLANKING
XYZ
000
000
3FF
EAV CODE
NEXT LINE
CB/CR STREAM
1920
H2
Figure 4-13: Chroma Stream Over One Video Line - 1080p
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Table 4-9: 1080-line Progressive Horizontal Timing
Progressive
30 or 30/1.001 Hz
25Hz
24 or 24/1.001 Hz
H1
280
720
830
H2
2200
2640
2750
4.7.2.2 High Definition 720p Output Formats
The Society of Motion Picture and Television Engineers (SMPTE) defines the standard for
progressive scan 720-line HD image formats. SMPTE ST 296-2001 specifies the
representation for 720p digital Y'C'BC'R 4:2:2 signals at pixel rates of 74.25MHz or
74.25/1.001 MHz.
LINE
1
V=1
BLANKING
25
V=0
26
ACTIVE VIDEO
(F=0)
745
V=1
746
BLANKING
750
H=1
EAV
H=0
SAV
Figure 4-14: 720p Digital Vertical Timing
The frame rate determines the horizontal timing, which is shown in Table 4-10.
Table 4-10: 720p Horizontal Timing
Frame Rate
H = 1 Sample Number
H = 0 Sample Number
24 or 24/1.001
1283
4124
25
1283
3959
30 or 30/1.001
1283
3299
50
1283
1979
60 or 60/1.001
1283
1649
4.7.2.3 Full HD Output Formats
High definition formats that require the Aviia serial data rate to operate at 2.97Gb/s are
defined as Full HD formats. These formats are generally 1080-line based, operating at 50
or 60Hz progressive frame rate. However, the sampling structure and bit-depth of HD
formats may also increase the payload rate at the digital input of the GV7601. There are
also 720-line Full HD formats with 4:4:4 sampling.
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The GV7601 can support the progressive scan Full HD formats shown in Table 4-11.
Table 4-11: Full HD 1080-line and 720-line Progressive Image Formats
Active Image
Format
Total Pixels x Lines
Sampling Structure
Pixel Depth
4:2:2 (Y'C'BC'R)
8 or 10-bit
2640 x 1125
60 or 60/1.001
2750 x 1125
24 or 24/1.001
4:4:4 (R'G'B' or Y'C'BC'R)
8 or 10-bit
25
2200 x 1125
30 or 30/1.001
2750 x 1125
24 or 24/1.001
2640 x 1125
4:4:4 (R'G'B' or Y'C'BC'R)
12-bit
25
2200 x 1125
30 or 30/1.001
2750 x 1125
24 or 24/1.001
2640 x 1125
4:2:2 (Y'C'BC'R)
12-bit
25
2200 x 1125
30 or 30/1.001
4125 x 750
24 or 24/1.001
3960 x 750
25
3300 x 750
1280 x 720
50
2200 x 1125
2640 x 1125
1920 x 1080
Frame Rate (Hz)
4:4:4 (R'G'B' or Y'C'BC'R)
8 or 10-bit
30 or 30/1.001
1980 x 750
50
1650 x 750
60 or 60/1.001
Full HD formats must be output to the GV7601 using a 20-bit input bus format at a clock
rate of 148.5 MHz. The 20-bit output format consists of two 10-bit data streams, Data
Stream 1 (DS1) and Data Stream 2 (DS2). The following diagrams show how the Full HD
image formats should be multiplexed into DS1 and DS2, at the output of the GV7601.
The GV7601 also supports a 10-bit DDR output mode, where DS1 and DS2 are word
multiplexed.
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Y’ 3
Y’ 2
C’B 1
Y’ 1
Y’ 2
C’R 0
C’B 1
Y’ 3
Y’ 0
C’B 0
C’R 1
SAV (XYZ)
SAV (XYZ)
C’R 0
SAV (000h)
SAV (000h)
C’R 1
Y’ 1
Y’ 0
C’B 0
Y’ n last sample
Y’ (n-1)
C’B n
last sample
Y’ (n-2)
C’R (n-1)
SAV (3FFh)
SAV (000h)
CRC1
CRC1
SAV (3FFh)
CRC0
CRC0
Replaced by Timing Reference Signal
SAV (000h)
LN1
LN1
C’R 963
LN0
LN0
Optional ancillary data space
C’R n
last Sample
C’B (n-1)
Y’ (n-3)
Y’ 1927
Y’ 1926
C’B 963
Y’ 1925
Y’ 1924
EAV (XYZ)
EAV (XYZ)
C’R 962
C’B 962
Y’ 1923
Y’ 1922
C’B 961
EAV (000h)
EAV (000h)
C’R 961
Y’ 1921
Y’ 1920
C’B 960
EAV (3FFh)
EAV (000h)
EAV (3FFh)
Y’ 1919
Optional ancillary data space
EAV (000h)
Y’ 1918
Data Stream 2
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
C’B 959
C’R 960
Y’ 1919
Data Stream 1
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
C’R 959
C’R Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
C’B 959
C’B Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
C’R 959
Y’ Data
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
Y’ 1918
For 60 or 60/1.001, n=2199
For 50, n=2639
Replaced by Timing Reference Signal
Replaced by Line Number
Replaced by Line CRC
Figure 4-15: Aviia 20-bit Mapping Structure for 1920 x 1080 50/60Hz Progressive
4:2:0 & 4:2:2 (Y‘C‘BC‘R) 8/10-bit Signals
Table 4-12: 1080p Y'C'BC'R 4:2:0 & 4:2:2 10-bit Bit Structure Mapping
Bit Number
Data Stream
9
8
7
6
5
4
DS1
Y'[9:0]
DS2
C'BC'R[9:0]
3
2
1
0
Note: For 8-bit systems, the data should be justified to the most significant bit (Y'9 and
C'BC'R9), with the two least significant bits (Y'[1:0] and C'BC'R[1:0]) set to zero.
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G’ 1
G’ 1
A’ 1
R’ 1
R’ 0
B’ 0
B’ 1
G’ 0
A’ 0
R’ 1
B’ 1
G’ 0
B’ 0
SAV (XYZ)
SAV (XYZ)
R’ 0
R’ n
last sample
SAV (000h)
SAV (000h)
R’ (n-1)
CRC1
CRC1
SAV (000h)
CRC0
CRC0
SAV (3FFh)
LN1
LN1
SAV (3FFh)
LN0
LN0
Replaced by Timing Reference Signal
SAV (000h)
EAV (XYZ)
EAV (XYZ)
Optional ancillary data space
G’ n
last sample
B’ n
last sample
G’ (n-1)
B’ (n-1)
B’ 1923
R’ 1923
EAV (000h)
EAV (000h)
R’ 1922
R’ 1921
B’ 1922
G’ 1923
G’ 1922
G’ 1921
B’ 1921
G’ 1920
B’ 1920
R’ 1920
EAV (3FFh)
EAV (000h)
R’ 1919
B’ 1919
EAV (3FFh)
G’ 1919
Data Stream 2
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
Optional ancillary data space
EAV (000h)
Data Stream 1
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
A’ 1919
R` or C’R Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
B’ 1919
B` or C’B Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
R’ 1919
G` or Y’ Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
G’ 1919
For 30 or 30/1.001, n=2199
For 24 or 24/1.001, n=2749
For 25, n=2639
Replaced by Timing Reference Signal
Replaced by Line Number
Replaced by Line CRC
Figure 4-16: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz
Progressive 4:4:4 (R‘G‘B‘) 8/10-bit Signals
Table 4-13: 1080p R'G'B' or Y'C'BC'R 4:4:4 10-bit Bit Structure Mapping
Bit Number
Data Stream
9
8
7
6
5
4
DS1 First Word
G'[9:0] or Y'[9:0]
DS1 Second Word
R'[9:0] or C'R[9:0]
DS2 First Word
A'[9:0]
DS2 Second Word
B'[9:0] or C'B[9:0]
3
2
1
0
Note 1: The 10-bit 'A' data in Figure 4-16 is used to pad DS2 and should be set to the
value 040h.
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Note 2: For 8-bit systems, the data should be justified to the most significant bit (R'/C'R9,
G'/Y'9 and B'/C'B9), with the two least significant bits (R'/C'R[1:0], G'/Y'[1:0] and
B'/C'B[1:0]) set to zero.
R`G’B` 0[11:9]
R`G’B` 0[5:3]
R`G’B` 1[11:9]
R`G’B` 1[5:3]
R`G’B` 0[8:6]
R`G’B` 0[2:0]
R`G’B` 1[8:6]
R`G’B` 1[2:0]
R’ 1
B’ 1
G’ 1
G’ 0
SAV (XYZ)
R’ 0
SAV (000h)
CRC1
CRC1
SAV (XYZ)
CRC0
CRC0
SAV (000h)
LN1
LN1
B’ 0
G’ n
last sample
R’ n
last sample
B’ (n-1)
LN0
LN0
R’ (n-1)
EAV (XYZ)
EAV (XYZ)
SAV (3FFh)
EAV (000h)
EAV (000h)
SAV (000h)
EAV (000h)
EAV (000h)
SAV (3FFh)
EAV (3FFh)
EAV (3FFh)
Optional ancillary data space
SAV (000h)
R`G’B` 1919[5:3]
Data Stream 2
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
Replaced by Timing Reference Signal
B’ n
last sample
G’ (n-1)
G’ 1923
R’ 1923
B’ 1922
R`G’B` 1919[11:9]
Optional ancillary data space
R`G’B` 1919[2:0]
R’ 1922
B’ 1923
G’ 1922
G’ 1921
R’ 1921
Data Stream 1
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
R`G’B` 1919[8:6]
12-bit R` or C’R Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
B’ 1921
G’ 1920
R’ 1919
12-bit B` or C’B Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
R’ 1920
B’ 1919
12-bit G` or Y’ Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
B’ 1920
G’ 1919
For 30 or 30/1.001, n=2199
For 24 or 24/1.001, n=2749
For 25, n=2639
Replaced by Timing Reference Signal
Replaced by Line Number
Replaced by Line CRC
Figure 4-17: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz
Progressive 4:4:4 (R‘G‘B‘ or Y‘C‘BC‘R) 12-bit Signals
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Table 4-14: 1080p R'G'B' or Y'C'BC'R 4:4:4 12-bit Bit Structure Mapping
Bit Number
Data Stream
9
8
7
6
5
4
3
2
1
0
DS1 First Word
B8
R'[11:9] or C'R[11:9]
G'[11:9] or Y'[11:9]
B'[11:9] or C'B[11:9]
DS1 Second Word
B8
R'[5:3] or C'R[5:3]
G'[5:3] or Y'[5:3]
B'[5:3] or C'B[5:3]
DS2 First Word
B8
R'[8:6] or C'R[8:6]
G'[8:6] or Y'[8:6]
B'[8:6] or C'B[8:6]
DS2 Second Word
B8
R'[2:0] or C'R[2:0]
G'[2:0] or Y'[2:0]
B'[2:0] or C'B[2:0]
Y’ 1
Y’ 0
C’B 0
SAV (000h)
SAV (000h)
SAV (XYZ)
Y` 0[11:6]
Y` 0[5:0]
Y` 1[11:6]
Y` 1[5:0]
SAV (000h)
SAV (XYZ)
C`B 0[11:6]
C`B 0[5:0]
C`R 1[11:6]
C`R 1[5:0]
C’R 0
C’R n
last Sample
SAV (3FFh)
SAV (3FFh)
Optional ancillary
data space
SAV (000h)
CRC1
EAV (XYZ)
EAV (XYZ)
CRC0
EAV (000h)
EAV (000h)
CRC1
EAV (000h)
EAV (000h)
CRC0
EAV (3FFh)
EAV (3FFh)
Y’ n
last sample
C’B n
last sample
Y’ (n-1)
Y’ 1923
Y’ 1922
C’B 961
Y` 1919[5:0]
C`R 959[5:0]
LN1
Y` 1919[11:6]
C`R 959[11:6]
LN0
Y` 1918[5:0]
C`B 959[5:0]
Optional ancillary
data space
LN1
Y` 1918[11:6]
Data Stream 2
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
LN0
Data Stream 1
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
C`B 959[11:6]
12-bit C’R Data
(Interface clock frequency=
37.125 MHz or 37.125/1.001 MHz)
C’R 961
C’B 960
C’R 960
C’R 959
12-bit C’B Data
(Interface clock frequency=
37.125 MHz or 37.125/1.001 MHz)
Y’ 1921
Y’ 1920
Y’ 1919
C’B 959
12-bit Y’ Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
Y’ 1918
For 30 or 30/1.001, n=2199
For 24 or 24/1.001, n=2749
For 25, n=2639
Replaced by Timing
Reference Signal
Replaced by Timing Reference Signal
Replaced by Line Number
Replaced by Line CRC
Figure 4-18: Aviia 20-bit Mapping Structure for 1920 x 1080 24/25/30Hz
Progressive 4:2:2 (Y‘C‘BC‘R) 12-bit Signals
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Table 4-15: 1080p Y'C'BC'R 4:2:2 12-bit Bit Structure Mapping
Bit Number
Data Stream
9
8
7
6
5
4
3
2
DS1 First Word
1
0
0
0
Y'[11:6]
DS1 Second Word
1
0
0
0
Y'[5:0]
DS2 First Word
1
0
0
0
C'B[11:6]
DS2 Second Word
1
0
0
0
C'B[5:0]
DS2 Third Word
1
0
0
0
C'R[11:6]
DS2 Fourth Word
1
0
0
0
C'R[5:0]
1
0
G’ 1
G’ 0
R’ 0
G’ 1
R’ 1
A’ 0
B’ 0
A` 1
B’ 1
R’ 1
B’ 1
G’ 0
B’ 0
SAV (XYZ)
SAV (XYZ)
R’ 0
G’ n
last sample
R’ n
last sample
SAV (000h)
SAV (000h)
R’ (n-1)
CRC1
CRC1
SAV (3FFh)
CRC0
CRC0
SAV (000h)
LN1
LN1
SAV (3FFh)
LN0
LN0
SAV (000h)
EAV (XYZ)
EAV (XYZ)
Optional ancillary data space
Replaced by Timing Reference Signal
B’ n
last sample
G’ (n-1)
B’ (n-1)
B’ 1283
R’ 1283
EAV (000h)
EAV (000h)
R’ 1281
R’ 1282
B’ 1282
G’ 1283
G’ 1282
G’ 1281
B’ 1281
G’ 1280
B’ 1280
R’ 1280
EAV (3FFh)
EAV (000h)
R’ 1279
B’ 1279
EAV (3FFh)
G’ 1279
Data Stream 2
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
Optional ancillary data space
EAV (000h)
Data Stream 1
(Interface clock frequency=
148.5 MHz or 148.5/1.001 MHz)
A’ 1279
R` or C’R Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
B’ 1279
B` or C’B Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
R’ 1279
G` or Y’ Data
(Interface clock frequency=
74.25 MHz or 74.25/1.001 MHz)
G’ 1279
For 60 or 60/1.001, n=1649
For 30 or 30/1.001, n=3299
For 24 or 24/1.001, n=4124
For 50, n=1979
For 25, n=3959
Replaced by Timing Reference Signal
Replaced by Line Number
Replaced by Line CRC
Figure 4-19: Aviia 20-bit Mapping Structure for 1280 x 720 24/25/30/25/60Hz
Progressive 4:4:4 (R‘G‘B‘ or Y‘C‘BC‘R) 8/10-bit Signals
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Table 4-16: 720p R'G'B' or Y'C'BC'R 4:4:4 10-bit Bit Structure Mapping
Bit Number
Data Stream
9
8
7
6
5
4
DS1 First Word
G'[9:0] or Y'[9:0]
DS1 Second Word
R'[9:0] or C'R[9:0]
DS2 First Word
A'[9:0]
DS2 Second Word
B'[9:0] or C'B[9:0]
3
2
1
0
Note 1: The 10-bit 'A' data in Figure 4-19 is used to pad DS2 and should be set to 040h.
Note 2: For 8-bit systems, the data should be justified to the most significant bit (R'/C'R9,
G'/Y'9 and B'/C'B9), with the two least significant bits (R'/C'R[1:0], G'/Y'[1:0] and
B'/C'B[1:0]) set to zero.
4.7.3 Descrambling and Word Alignment
The GV7601 performs NRZI to NRZ decoding and data descrambling according to ITU-R
BT.656 and BT.1120, and word aligns the data to TRS sync words.
When operating in manual mode (AUTO/MAN = LOW), the device only carries out video
decoding, descrambling and word alignment when the 656_BYPASS pin is set HIGH and
the ASI pin is set LOW.
When operating in Auto mode (AUTO/MAN = HIGH), the GV7601 carries out
descrambling and word alignment to enable the detection of TRS sync words. When
two consecutive valid TRS words (SAV and EAV), with the same bit alignment have been
detected, the device word-aligns the data to the TRS ID words.
TRS ID word detection is a continuous process. The device remains in video mode until
TRS ID words fail to be detected.
Note: Both 8-bit and 10-bit TRS headers are identified by the device.
4.8 Parallel Video Data Outputs DOUT[19:0] and DOUT[9:0]
The parallel data outputs are aligned to the rising edge of the PCLK.
4.8.1 Parallel Data Bus Buffers
The parallel data bus, status signal outputs and control signal input pins are all
connected to high-impedance buffers.
The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and
IO_GND pins.
All output buffers (including the PCLK output) are set to high-impedance in Reset mode
(RESET = LOW).
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I/O Timing Specs:
10-bit SDR Mode:
6.734ns (HD 10-bit)
37.037ns (SD 10-bit)
DOUT[19:10]
Y0
Cr0
80%
Y1
Cb1
80%
PCLK_OUT
20%
t oh
20%
tf
tr
t od
10-bit HD Mode
1.8V
3.3V
t
tr
(min)
tf
oh
dbus
1.000ns
0.400ns
stat
1.000ns
0.500ns
t od
Cload
6pF
tr
(max)
tf
3.700ns
1.400ns
4.100ns
1.600ns
Cload
15pF
t
oh
tr
(min)
tf
1.000ns
0.400ns
1.000ns
0.400ns
Cload
6pF
tr
(max)
tf
t od
3.700ns
1.400ns
4.400ns
1.500ns
Cload
15pF
10-bit SD Mode
1.8V
3.3V
t oh
tr
(min)
tf
dbus
19.400ns
0.400ns
stat
19.400ns
0.500ns
Cload
6pF
t od
tr
(max)
tf
22.200ns
1.400ns
22.200ns
1.600ns
Cload
15pF
t oh
tr
(min)
tf
19.400ns
0.400ns
19.400ns
0.400ns
Cload
6pF
tr
(max)
tf
t od
22.200ns
1.400ns
22.200ns
1.500ns
Cload
15pF
Figure 4-20: PCLK to Data and Control Signal Output Timing - SDR Mode 1
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I/O Timing Specs:
6.734ns (Full HD 20-bit)
13.468ns (HD 20-bit)
74.047ns (SD 20-bit)
20-bit SDR Mode:
DOUT[19:10]
Y0
Y1
Y2
Y3
DOUT[9:0]
Cb0
Cr0
Cb1
Cr1
80%
80%
PCLK
20%
t oh
20%
tr
t od
tf
20-bit HD Mode
1.8V
3.3V
tr
(min)
tf
t oh
dbus
1.000ns
0.400ns
stat
1.000ns
0.500ns
t od
Cload
6pF
tr
(max)
tf
3.700ns
1.400ns
4.100ns
1.600ns
Cload
15pF
t
oh
tr
(min)
tf
1.000ns
0.400ns
1.000ns
0.400ns
Cload
tr
(max)
tf
Cload
1.400ns
1.500ns
15pF
t od
tr
(max)
tf
Cload
41.000ns
1.400ns
41.000ns
1.500ns
t od
3.700ns
6pF
4.400ns
20-bit SD Mode
1.8V
3.3V
oh
tr
(min)
tf
dbus
38.000ns
0.400ns
stat
38.000ns
0.500ns
t
Cload
6pF
t od
tr
(max)
tf
41.000ns
1.400ns
41.000ns
1.600ns
Cload
15pF
oh
tr
(min)
tf
38.000ns
0.400ns
38.000ns
0.400ns
t
Cload
6pF
15pF
Figure 4-21: PCLK to Data and Control Signal Output Timing - SDR Mode 2
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I/O Timing Specs:
DDR Mode:
6.734ns
3.367ns
DOUT[19:10]
Y0
Cr0
Y1
80%
Cb1
Y2
Cr1
Y3
80%
PCLK
20%
t oh
t oh
t od
20%
tr
tf
t od
10-bit Full HD Mode
1.8V
3.3V
t oh
tr
(min)
tf
dbus
0.450ns
0.400ns
stat
0.450ns
0.500ns
Cload
6pF
t od
tr
(max)
tf
1.900ns
1.500ns
2.200ns
1.600ns
Cload
15pF
t
oh
tr
(min)
tf
0.400ns
0.300ns
0.450ns
0.400ns
Cload
6pF
t od
1.800ns
2.500ns
tr
(max)
tf
Cload
1.100ns
1.500ns
15pF
Figure 4-22: PCLK to Data and Control Signal Output Timing - DDR Mode
Table 4-17: GV7601 Output Video Data Format Selections
Pin/Register Bit Settings
Output Data Format
DOUT[9:0]
DOUT[19:10]
LOW
Chroma
Luma
LOW
LOW
DATA
DATA
X
HIGH
LOW
Chroma
Luma
HIGH
X
LOW
LOW
DATA
DATA
LOW
LOW
HIGH
HIGH
LOW
Driven LOW
DS1 / DS2
LOW
LOW
LOW
HIGH
LOW
Driven LOW
Luma / Chroma
20BIT
/10BIT
RATE_
SEL0
RATE_
SEL1
656_
BYPASS
ASI
20-bit demultiplexed HD
format
HIGH
LOW
LOW
HIGH
20-bit data output HD
format
HIGH
LOW
LOW
20-bit demultiplexed SD
format
HIGH
HIGH
20-bit data output SD
format
HIGH
10-bit multiplexed Full HD
DDR format
10-bit multiplexed HD
format
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Table 4-17: GV7601 Output Video Data Format Selections (Continued)
Pin/Register Bit Settings
Output Data Format
DOUT[9:0]
DOUT[19:10]
LOW
Driven LOW
DATA
HIGH
LOW
Driven LOW
Luma / Chroma
X
LOW
LOW
Driven LOW
DATA
HIGH
HIGH
LOW
DS2
DS1
20BIT
/10BIT
RATE_
SEL0
RATE_
SEL1
656_
BYPASS
ASI
10-bit data output HD
format
LOW
LOW
LOW
LOW
10-bit multiplexed SD
format
LOW
HIGH
X
10-bit data output SD
format
LOW
HIGH
20-bit demultiplexed Full
HD format
HIGH
LOW
Transport stream
LOW
HIGH
X
−
HIGH
DOUT19 = WORD_ERR
DOUT18 = SYNC_OUT
DOUT17 = H_OUT
DOUT16 = G_OUT
DOUT15 = F_OUT
DOUT14 = E_OUT
DOUT13 = D_OUT
DOUT12 = C_OUT
DOUT11 = B_OUT
DOUT10 = A_OUT
4.8.2 Parallel Output in Video Mode
When the device is operating in video mode (656_BYPASS = HIGH and ASI = LOW), data
is output in either Multiplexed or Demultiplexed form depending on the setting of the
20BIT/10BIT pin.
When operating in 20-bit mode (20BIT/10BIT = HIGH), the output data is demultiplexed
Luma and Chroma data for SD and HD data rates, and DS1 and DS2 for the Full HD data.
When operating in 10-bit mode (20BIT/10BIT = LOW), the output data is multiplexed
Luma and Chroma data for SD and HD data rates, and multiplexed DS1 and DS2 for the
Full HD data. In this mode, the data is presented on the DOUT[19:10] pins, with
DOUT[9:0] being forced LOW.
4.8.3 Parallel Output in ASI Mode
In ASI mode, the 20BIT/10BIT pin must be set LOW to configure the output parallel bus
for 10-bit operation.
ASI mode is enabled when the AUTO/MAN bit is LOW, 656_BYPASS pin is LOW and the
ASI pin is HIGH.
The extracted 8-bit transport stream data is presented on DOUT[17:10] such that
DOUT[17:10] = HOUT ~ AOUT, where AOUT is the least significant bit of the decoded
transport stream data.
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In addition, the DOUT19 and DOUT18 pins are configured as ASI status signals
WORDERR and SYNCOUT respectively.
SYNCOUT is HIGH whenever a K28.5 sync character is output from the device.
WORDERR is HIGH whenever the device has detected a running disparity error or illegal
code word.
4.8.4 Parallel Output In Data-Through Mode
This mode is enabled when the 656_BYPASS and ASI pins are LOW.
In this mode, data is passed to the output bus without any decoding, descrambling or
word-alignment.
The output data width (10-bit or 20-bit) is controlled by the setting of the 20BIT/10BIT
pin.
4.8.5 Parallel Output Clock (PCLK)
The frequency of the PCLK output signal of the GV7601 is determined by the output
data format. Table 4-18 lists the output signal formats according to the data format
selected in Manual mode (AUTO/MAN bit in the host interface is set LOW), or detected
in Auto mode (AUTO/MAN bit in the host interface is set HIGH).
Table 4-18: GV7601 PCLK Output Rates
Pin/Control Bit Settings
Output Data
Format
PCLK Rate
20BIT/
10BIT
RATE_DET0
RATE_DET1
656_
BYPASS
ASI
20-bit demultiplexed
HD format
HIGH
LOW
LOW
HIGH
LOW
74.25 or
74.25/1.001MHz
20-bit data output
HD format
HIGH
LOW
LOW
LOW
LOW
74.25 or
74.25/1.001MHz
20-bit demultiplexed
SD format
HIGH
HIGH
X
HIGH
LOW
13.5MHz
20-bit data output
SD format
HIGH
HIGH
X
LOW
LOW
13.5MHz
20-bit demultiplexed
Full HD format
HIGH
LOW
HIGH
HIGH
LOW
148.5 or
148.5/1.001MHz
10-bit multiplexed
Full HD DDR format
LOW
LOW
HIGH
HIGH
LOW
148.5 or
148.5/1.001MHz
10-bit multiplexed
HD format
LOW
LOW
LOW
HIGH
LOW
148.5 or
148.5/1.001MHz
10-bit data output
HD format
LOW
LOW
LOW
LOW
LOW
148.5 or
148.5/1.001MHz
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Table 4-18: GV7601 PCLK Output Rates (Continued)
Pin/Control Bit Settings
Output Data
Format
PCLK Rate
20BIT/
10BIT
RATE_DET0
RATE_DET1
656_
BYPASS
ASI
10-bit multiplexed
SD format
LOW
HIGH
X
HIGH
LOW
27MHz
10-bit data output
SD format
LOW
HIGH
X
LOW
LOW
27MHz
10-bit transport
stream output
LOW
HIGH
X
LOW
HIGH
27MHz
4.8.6 DDR Parallel Clock Timing
The GV7601 has the ability to transmit 10-bit parallel video data with a DDR (Dual Data
Rate) pixel clock over a single-ended interface. DDR Mode can be enabled when the
input data rate is 2.97Gb/s. In this case, the 10-bit parallel data rate is 297Mb/s, and the
frequency of the DDR clock is 148.5MHz (10-bit output in Full HD mode).
The DDR pixel clock avoids the need to operate a high-drive pixel clock at 297MHz. This
reduces power consumption, clock drive strength, and noise generation, and precludes
from generating excessive EMI had PCLK on the board have to run at 297MHz. It also
enables easier board routing and avoids the need to use the higher-speed I/Os on
FPGAs, which may require more expensive speed grades.
Figure 4-23 shows how the DDR interface operates. The pixel clock is transmitted at half
the data rate, and the interleaved data is sampled at the receiver on both clock edges.
20-bit video data bus
(transition rate = 74.25MHz)
10-bit video data bus
(transition rate = 148.5MHz)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb
0
Y0
Cr
0
Y1
Cb
1
Y2
Cr
1
Y3
Cb
2
Y4
Cr
2
Y5
Cb
3
Y6
Cr
3
Y7
Cb
4
Y8
Cr
4
Y9
PCLK
(148.5MHz)
Figure 4-23: DDR Video Interface
The GV7601 has the ability to shift the Setup/Hold window on the receive interface, by
using an on-chip delay line to shift the phase of PCLK with respect to the data bus.
The timing of the PCLK output, relative to the data, can be adjusted through the host
interface registers. Address 06Ch contains the delay line controls:
Bit[5] (DEL_LINE_CLK_SEL) is a coarse delay adjustment that selects between the
default (nominal) PCLK phase and a quadrature phase, for a 90º phase shift.
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Bits[4:0] (DEL_LINE_OFFSET) comprise a fine delay adjustment to shift the PCLK in
40ps increments (typical conditions). The maximum fine delay adjustment is
approximately 1.2ns under nominal conditions.
An example delay adjustment over min/typ/max conditions is illustrated in Figure 4-24.
The target delay is 0.84 ns under typical conditions (approximately 45º PCLK phase
shift), and requires a control word setting of 0x0014 for address 0x006C.
90º phase shift
6.734ns
3.367ns
1.684ns
PCLK
0.842ns
offset [5] = 1 (90º phase shift)
Typical 45º phase shift
6.734ns
3.367ns
Ranges:
1.684ns
PCLK
(MIN)
0.58ns
delay
PCLK
(TYP)
0.84ns
delay
PCLK
(MAX)
1.38ns
delay
Figure 4-24: Delay Adjustment Ranges
4.9 Timing Signal Generator
The GV7601 has an internal timing signal generator which is used to generate digital
FVH timing reference signals, to detect and correct certain error conditions and
automatic video standard detection.
The timing signal generator is only operational in video mode (656_BYPASS = HIGH).
The timing signal generator consists of a number of counters and comparators
operating at video pixel and video line rates. These counters maintain information
about the total line length, active line length, total number of lines per field/frame and
total active lines per field/frame for the received video standard.
The timing signal generator 'learns' the video standard by timing the horizontal and
vertical reference information contained in the TRS IDs of the received video data
(specifically, the XYZ word). It therefore takes one video frame to obtain full
synchronization to the received video standard.
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Note: Both 8-bit and 10-bit TRS words are identified by the device. Once
synchronization has been achieved, the timing signal generator continues to monitor
the received TRS timing information to maintain synchronization.
The timing signal generator re-synchronizes all pixel and line based counters on every
received TRS ID.
4.10 Programmable Multi-function Outputs
The GV7601 has 6 multi-function output pins, STAT [5:0], which are programmable via
the host interface to output one of the following signals:
Table 4-19: Output Signals Available on Programmable Multi-Function Pins
Status Signal
Selection Code
Default Output Pin
H/HSYNC (according to 861_EN Pin) Section 4.11
0000
STAT 0
V/VSYNC (according to 861_EN Pin) Section 4.11
0001
STAT 1
F/DE (according to 861_EN Pin) Section 4.11
0010
STAT 2
LOCKED Section 4.6
0011
STAT 3
Y/1ANC Section 4.15
0100
STAT 4
C/2ANC Section 4.15
0101
−
DATA_ERROR Section 4.14
0110
STAT 5
VIDEO_ERROR
0111
−
AUDIO_ERROR
1000
−
EDH_DETECTED
1001
−
CARRIER_DETECT
1010
−
RATE_DET0
1011
−
RATE_DET1
1100
−
Each of the STAT[5:0] pins are configurable individually using the register bits in the
host interface; STAT[5:0]_CONFIG (008h/009h).
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4.11 H:V:F Timing Signal Generation
The GV7601 extracts critical timing parameters from the received TRS words.
Horizontal blanking (H), Vertical blanking (V), and Field odd/even (F) timing are output
on the STAT[2:0] pins by default.
Using the H_CONFIG bit in the host interface, the H signal timing can be selected as one
of the following:
1. Active line blanking (H_CONFIG = LOW) - the H output is HIGH for the horizontal
blanking period, including the EAV TRS words.
2. TRS based blanking (H_CONFIG = HIGH) - the H output is set HIGH for the entire
horizontal blanking period as indicated by the H bit in the received TRS signals.
The timing of these signals is shown in Figure 4-25, Figure 4-26, Figure 4-27, Figure 4-28
and Figure 4-29.
Note: Both 8-bit and 10-bit TRS words are identified by the device.
PCLK
DS1
DS2
H
V
F
3FF
000
000
XYZ (EAV)
3FF
000
000
XYZ (SAV)
3FF
000
000
XYZ (EAV)
3FF
000
000
XYZ (SAV)
Figure 4-25: H:V:F Output Timing - Full HD 20-bit Output Mode
PC LK
L U M A D A T A OU T
C H R O M A D A T A OU T
H
V
F
3FF
000
000
X Y Z (EAV)
3FF
000
000
X Y Z (SAV)
3FF
000
000
X Y Z (EAV)
3FF
000
000
X Y Z (SAV)
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-26: H:V:F Output Timing - HD 20-bit Output Mode
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PCLK (Full HD DDR)
PCLK (HD)
MULTIPLEXED Y’CbCr DATA (HD)
MULTIPLEXED DS1/DS2 DATA (Full HD)
H
V
F
3FF
3FF
000
000
000
000
XYZ (EAV) XYZ (EAV)
H VF T IM IN G A T E A V
PCLK (Full HD DDR)
PCLK (HD)
MULTIPLEXED Y’CbCr DATA (HD)
MULTIPLEXED DS1/DS2 DATA (Full HD)
3FF
3FF
000
000
000
000
XYZ (SAV) XYZ (SAV)
H
V
F
H VF T IM IN G A T S A V
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-27: H:V:F Output Timing - HD & Full HD 10-bit Output Mode
P C LK
C H R O M A D A T A OU T
L U M A D A T A OU T
H
V
F
3FF
000
3FF
000
000
X Y Z (EAV)
000
X Y Z (SAV)
H S IG N A L T IM IN G :
H _ C O N F IG = L O W
H _ C O N F IG = H IG H
Figure 4-28: H:V:F Output Timing - SD 20-bit Output Mode
PC LK
M U X Y 'C b C r D A T A O U T
H
V
F
3FF
H S IG N A L T IM IN G :
000
000
X Y Z (EAV)
H _ C O N F IG = L O W
3FF
000
000
X Y Z (SAV)
H _ C O N F IG = H IG H
Figure 4-29: H:V:F Output Timing - SD 10-bit Output Mode
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4.11.1 CEA-861 Timing Generation
The GV7601 is capable of generating CEA 861 timing instead of HVF timing for all of the
supported video formats.
This mode is selected when the 861_EN pin is HIGH.
Horizontal sync (HSYNC), Vertical sync (VSYNC), and Data Enable (DE) timing are output
on the STAT[2:0] pins by default.
Table 4-20 shows the CEA-861 formats supported by the GV7601:
Table 4-20: Supported CEA-861 Formats
Format
CEA-861 Format
VD_STD[5:0]
720(1440) x 480i @ 59.94/60Hz
6&7
16h, 17h, 19h, 1Bh
720(1440) x 576i @ 50Hz
21 & 22
18h, 1Ah
1280 x 720p @ 59.94/60Hz
4
20h, 00h
1280 x 720p @ 50Hz
19
24h, 04h
1920 x 1080i @ 59.94/60Hz
5
2Ah, 0Ah
1920 x 1080i @ 50Hz
20
2Ch, 0Ch
1920 x 1080p @ 29.97/30Hz
341
2Bh, 0Bh
1920 x 1080p @ 25Hz
332
2Dh, 0Dh
1920 x 1080p @ 23.98/24Hz
32
30h, 10h
1920 x 1080p @ 59.94/60Hz
161
2Bh
1920 x 1080p @ 50Hz
312
2Dh
Notes:
1,2: Timing is identical for the corresponding formats.
4.11.1.1 Vertical Timing
When CEA-861 timing is selected, the device outputs standards compliant CEA-861
timing signals as shown in the figures below.
The digital representation of 525 video, commonly referred to as D1, contains 487 lines
of active video. However, the CEA-861 standard is defined as 525 video having 480
active lines. When the TRS_861 host interface bit is set LOW, the DE output signal will be
set HIGH for 480 lines. When the TRS_861 bit is set HIGH, the DE signal will be set HIGH
for 487 lines.
The timing of these signals is shown in the CEA-861 specifications. For information, they
are included in the following diagrams. These diagrams may not be comprehensive.
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1650 Total Horizontal Clocks per line
Data
Enable
370
1280 Clocks for Active Video
40
110
220 clocks
HSYNC
~
~
~
720 Active Vertical Lines
~
Progressive Frame: 30 Vertical Blanking Lines
~
~
~
~
Data
Enable
1650 clocks
260
110
745 746 747 748
749
750 1
2
3
4
5
6
7
25
26
~
~
~
~
HSYNC
745 746
750
VSYNC
Figure 4-30: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4)
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2200 Total Horizontal Clocks per line
Data
Enable
280
44
1920 Clocks for Active Video
88
148 clocks
HSYNC
~
~
~
~
540 Active Vertical Lines per field
Field 1: 22 Vertical Blanking Lines
~
~
Data
Enable
2200 clocks
88
192
~
~
HSYNC
1123 1124 1125 1
2
3
4
5
6
7
8
19
20
21
560 561 562
VSYNC
~
~
~
~
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
Data
Enable
2200 clocks
1100
88
192
~
~
HSYNC
560
561
562 563 564 565 566 567 568
569 570
582
583
584
1123 1124 1125
VSYNC
Figure 4-31: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5)
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1716 Total Horizontal Clocks per line
Data
Enable
276
124
38
1440 Clocks for Active Video
114 clocks
HSYNC
1716 clocks
~
238
~
~
38
~
~
~
Data
Enable
~
240 Active Vertical Lines per field
~
Field 1: 22 Vertical Blanking Lines
HSYNC
524 525
1
2
3
4
5
6
7
8
9
21
22
261 262 263
VSYNC
~
858
238
~
1716 clocks
~
~
38
~
~
~
Data
Enable
~
240 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
HSYNC
261 262 263 264 265 266 267 268 269 270 271
284 285
524 525
1
VSYNC
Figure 4-32: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6 & 7)
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1980 Total Horizontal Clocks per line
Data
Enable
700
40
440
1280 Clocks for Active Video
220 clocks
HSYNC
~
1980 clocks
745 746 747
748 749
750
1
2
3
4
5
6
7
25
26
~
~
~
~
HSYNC
~
260
~
440
~
~
~
~
Data
Enable
~
720 Active Vertical Lines
Progressive Frame: 30 Vertical Blanking Lines
745 746
750
VSYNC
Figure 4-33: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19)
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2640 Total Horizontal Clocks per line
Data
Enable
720
44
1920 Clocks for Active Video
148 clocks
528
HSYNC
~
~
~
~
540 Active Vertical Lines per field
Field 1: 22 Vertical Blanking Lines
~
~
Data
Enable
2640 clocks
528
192
~
~
HSYNC
1123 1124 1125 1
2
3
4
5
6
7
8
19
20
21
560 561 562
VSYNC
~
~
~
~
540 Active Vertical Lines per field
Field 2: 23 Vertical Blanking Lines
~
~
Data
Enable
2640 clocks
1320
528
192
~
~
HSYNC
560
561
562 563 564 565 566 567 568
569 570
582
583
584
1123 1124 1125
VSYNC
Figure 4-34: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20)
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1728 Total Horizontal Clocks per line
Data
Enable
288
126
24
1440 Clocks for Active Video
138 clocks
HSYNC
~
1728 clocks
~
264
~
~
24
~
~
~
Data
Enable
~
288 Active Vertical Lines per field
Field 1: 24 Vertical Blanking Lines
HSYNC
623 624 625
1
2
3
4
5
6
7
22
23
310 311 312
VSYNC
~
264
~
1728 clocks
864
~
~
24
~
~
~
Data
Enable
~
288 Active Vertical Lines per field
Field 2: 25 Vertical Blanking Lines
HSYNC
310 311 312
313 314 315 316 317 318 319 320
335 336
623 624 625
VSYNC
Figure 4-35: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22)
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2200 Total Horizontal Clocks per line
Data
Enable
88
280
1920 Clocks for Active Video
44
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
Data
Enable
2200 clocks
1
2
3
4
5
6
7
41
42
~
~
~
HSYNC
~
192
88
1121 1122 1123 1124 1125
~
~
1080 Active Vertical Lines
1121 1122 1123 1124 1125
VSYNC
Figure 4-36: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16)
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2640 Total Horizontal Clocks per line
Data
Enable
720
44
528
1920 Clocks for Active Video
148 clocks
HSYNC
~
~
~
Data
Enable
~
1080 Active Vertical Lines
Progressive Frame: 45 Vertical Blanking Lines
2640 clocks
~
~
HSYNC
1121 1122 1123 1124 1125
1
2
3
4
5
6
7
41
42
~
192
~
528
1121 1122 1123 1124 1125
VSYNC
Figure 4-37: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31)
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2750 Total Horizontal Clocks per line
Data
Enable
830
44
638
1920 Clocks for Active Video
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
Data
Enable
~
~
1080 Active Vertical Lines
2750 clocks
~
~
HSYNC
1121 1122 1123 1124 1125
1
2
3
4
5
6
7
41
42
~
192
~
638
1121 1122 1123 1124 1125
VSYNC
Figure 4-38: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32)
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2640 Total Horizontal Clocks per line
Data
Enable
720
44
528
1920 Clocks for Active Video
148 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines
~
~
Data
Enable
~
~
1080 Active Vertical Lines
2640 clocks
~
~
HSYNC
1121 1122 1123 1124 1125
1
2
3
4
5
6
7
41
42
~
192
~
528
1121 1122 1123 1124 1125
VSYNC
Figure 4-39: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33)
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2200 Total Horizontal Clocks per line
Data
Enable
280
44
88
1920 Clocks for Active Video
148 clocks
HSYNC
~
2220 clocks
~
~
HSYNC
1121 1122 1123 1124 1125
1
2
3
4
5
6
7
41
42
~
192
~
88
~
~
Data
Enable
~
1080 Active Vertical Lines
Progressive Frame: 45 Vertical Blanking Lines
1121 1122 1123 1124 1125
VSYNC
Figure 4-40: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34)
4.12 Automatic Video Standards Detection
Using the timing extracted from the received TRS signals, the GV7601 is able to identify
the received video standard.
For inputs operating at 2.97Gb/s, the GV7601 measures the timing parameters of one of
the two identical data streams. The Rate Selection/Indication bits and the VD_STD code
may be used in combination to determine the video standard.
The total samples per line, active samples per line, total lines per field/frame and active
lines per field/frame are all measured.
Four registers are provided to allow the system to read the video standard information
from the device.
The raster structure registers also contain three status bits: STD_LOCK, INT/PROG and M.
The STD_LOCK bit is set HIGH whenever the timing signal generator is fully
synchronized to the incoming standard, and detects it as one of the supported formats.
The INT/PROG bit is set HIGH if the detected video standard is interlaced and LOW if the
detected video standard is progressive. M is set HIGH if the clock frequency includes the
“1000/1001” factor denoting a 23.98, 29.97 or 59.94Hz frame rate.
The video standard code is reported in the VD_STD bits of the host interface register.
Table 4-21 describes the 5-bit codes for the recognized video standards.
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Table 4-21: Supported Video Standard Codes
Active Video Area
RATE_
DET[1]
HD/Full
HD
RATE_
DET[0]
SD/HD
Lines per
Field
Active
Lines per
Field
Words
per
Active
Line
Words per
Line
VD_STD
[5:0]
1920x1080/60 (1:1)
1
0
1125
1080
1920
2200
2Bh
1920x1080/50 (1:1)
1
0
1125
1080
1920
2640
2Dh
1920x1080/60 (2:1)
1
0
1125
1080
3840
4400
2Ah
1920x1080/50 (2:1)
1
0
1250
1080
3840
5280
2Ch
1280x720/60 (1:1)
1
0
750
720
2560
3300
20h
1280x720/50 (1:1)
1
0
750
720
2560
3960
24h
1920x1080/30 (1:1)
1
0
1125
1080
3840
4400
2Bh
1920x1080/25 (1:1)
1
0
1125
1080
3840
5280
2Dh
1280x720/25 (1:1)
1
0
750
720
2560
7920
26h
1920x1080/24 (1:1)
1
0
1125
1080
3840
5500
30h
1280x720/24 (1:1)
1
0
750
720
2560
8250
28h
1920x1035/60 (2:1)
0
0
1125
1035
1920
2200
15h
1920x1080/50 (2:1)
0
0
1250
1080
1920
2376
14h
1920x1080/60 (2:1)
0
0
1125
1080
1920
2200
0Ah
1920x1080/50 (2:1)
0
0
1250
1080
1920
2640
0Ch
1920x1080/30 (1:1)
0
0
1125
1080
1920
2200
0Bh
1920x1080/25 (1:1)
0
0
1125
1080
1920
2640
0Dh
1920x1080/24 (1:1)
0
0
1125
1080
1920
2750
10h
1920x1080/25 (1:1) –
0
0
1125
1080
2304
2640
0Eh
1920x1080/24 (1:1) –
0
0
1125
1080
2400
2750
12h
1280x720/30 (1:1)
0
0
750
720
1280
3300
02h
1280x720/30 (1:1) – EM
0
0
750
720
2880
3300
03h
1280x720/50 (1:1)
0
0
750
720
1280
1980
04h
1280x720/50 (1:1) – EM
0
0
750
720
1728
1980
05h
1280x720/25 (1:1)
0
0
750
720
1280
3960
06h
1280x720/25 (1:1) – EM
0
0
750
720
3456
3960
07h
1280x720/24 (1:1)
0
0
750
720
1280
4125
08h
1280x720/24 (1:1) – EM
0
0
750
720
3600
4125
09h
1280x720/60 (1:1)
0
0
750
720
1280
1650
00h
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Table 4-21: Supported Video Standard Codes (Continued)
Active Video Area
RATE_
DET[1]
HD/Full
HD
RATE_
DET[0]
SD/HD
Lines per
Field
Active
Lines per
Field
Words
per
Active
Line
Words per
Line
VD_STD
[5:0]
1280x720/60 (1:1) – EM
0
0
750
720
1440
1650
01h
1440x487/60 (2:1)
x
1
525
244 or 243
1440
1716
16h
1440x507/60
x
1
525
254 or 253
1440
1716
17h
525-line 487 generic
x
1
525
−
−
1716
19h
525-line 507 generic
x
1
525
−
−
1716
1Bh
1440x576/50 (2:1) Or
dual link progressive)
x
1
625
−
1440
1728
18h
625-line generic
x
1
625
−
−
1728
1Ah
SD/HD = 0
0
0
−
−
−
−
1Dh
SD/HD = 1
x
1
−
−
−
−
1Eh
SD/HD = 0
1
0
−
−
−
−
3Ch
Note: Other values of VD_STD[5:0] not listed in Table 4-21 may be reported in the host
interface (0Fh, 11h, 13h, 1Dh, 1Eh, 3Ch). These values denote “unknown video format”.
The device will lock to the unknown format and output valid data. It is the responsibility
of the user to determine any unknown video formats.
By default (after power up or after systems reset), the four RASTER_STRUCTURE,
VD_STD, STD_LOCK and INT/PROG bits are set to zero. These registers are also cleared
when the 656_BYPASS pin is LOW.
4.13 EDH Detection
The Error Detection and Handling (EDH) concept is based on making Cyclic Redundancy
Check (CRC) calculations for each field of component digital video prior to transmission
over a serial digital interface, such as Aviia. Separate CRC values are calculated for the
entire video field, including blanking, and the active picture region. The calculated CRC
values, along with status flags, are sent with the video data over the Aviia link.
The Aviia receiver also performs the same CRC calculations and compares the values to
those sent across the link. If the CRC values are not identical to the transmitted values,
an error can be indicated by the receive equipment. This allows the onset of errors,
systematic of faulty or poor cable and connectors, to be detected and flagged.
EDH is fully defined by a recommended practice, RP 165, from the Society of Motion
Pictures and Television Engineers (SMPTE). RP 165 defines the CRC calculation ranges,
error status flag handling, and format and position of the EDH packet to be embedded
in the video.
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The GV7601 can be configured to automatically detect EDH packets, re-calculate CRC
values and compare them with the values in the received EDH packets. Status flags are
also extracted and can be accessed via the host interface.
4.13.1 EDH Packet Detection
The GV7601 determines if EDH packets are present in the incoming video data and
asserts the EDH_DETECT status flag.
EDH_DETECT is set HIGH when EDH packets have been detected and remains HIGH until
EDH packets are no longer present. It is set LOW at the end of the vertical blanking
(falling edge of V) if an EDH packet has not been detected during vertical blanking.
EDH_DETECT can be programmed to be output on the multi-function output port pins.
The EDH_DETECT bit is also available in the host interface.
4.13.2 EDH Flag Detection
The EDH flags for ancillary data, active picture, and full field areas are extracted from the
detected EDH packets and placed in the EDH_FLAG_IN register.
When the EDH_FLAG_UPDATE_MASK bit in the host interface is set HIGH, the GV7601
updates the Ancillary Data, Full Field, and Active Picture EDH flags according to SMPTE
RP165. The updated EDH flags are available in the EDH_FLAG_OUT register. The EDH
packet output from the device contains these updated flags.
One set of flags is provided for both fields 1 and 2. The field 1 flag data is overwritten by
the field 2 flag data.
When EDH packets are not detected, the UES flags in the EDH_FLAG_OUT register are
set HIGH to signify that the received signal does not support Error Detection and
Handling. In addition, the EDH_DETECT bit is set LOW. These flags are set regardless of
the setting of the EDH_FLAG_UPDATE_MASK bit.
EDH_FLAG_OUT and EDH_FLAG_IN may be read via the host interface at any time
during the received frame except on the lines defined in SMPTE RP165, when these flags
are updated.
The GV7601 indicates the CRC validity for both active picture and full field CRCs. The
AP_CRC_V bit in the host interface indicates the active picture CRC validity, and the
FF_CRC_V bit indicates the full field CRC validity. When EDH_DETECT = LOW, these bits
are cleared.
The EDH_FLAG_OUT and EDH_FLAG_IN register values remain set until overwritten by
the decoded flags in the next received EDH packet. When an EDH packet is not detected
during vertical blanking, the flag registers are cleared at the end of the vertical blanking
period.
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4.14 Video Signal Error Detection & Indication
The GV7601 includes a number of video signal error detection functions. These are
provided to enhance operation of the device when operating in video mode
(656_BYPASS = HIGH). These features are not available in the other operating modes of
the device (i.e. when 656_BYPASS = LOW).
Signal errors that can be detected include:
1. TRS errors.
2. HD line based CRC errors.
3. EDH errors.
4. HD line number errors.
The device maintains an ERROR_STAT register. Each error condition has a specific flag in
the ERROR_STAT register, which is set HIGH whenever an error condition is detected.
An ERROR_MASK register is also provided, allowing the user to select which error
conditions to be reported. Each bit of the ERROR_MASK register corresponds to a
unique error type.
Separate SD_AUDIO_ERROR_MASK and HD_AUDIO_ERROR_MASK registers for SD and
HD audio are also provided, allowing select error conditions to be reported. Each bit of
each ERROR_MASK register corresponds to a unique error type.
By default (at power up or after system reset), all bits of the ERROR_MASK registers are
zero, enabling all errors to be reported. Individual error detection may be disabled by
setting the corresponding bit HIGH in the mask registers.
Error conditions are indicated by a VIDEO _ERROR signal and an AUDIO_ERROR signal,
which are available for output on the multifunction I/O output pins. The two signals are
also combined into a summary DATA_ERROR signal, which is also available on the
multifunction I/O pins. These signals are normally HIGH, but are set LOW by the device
when an error condition has been detected.
These signals are a logical 'NOR' of the appropriate error status flags stored in the
ERROR_STATUS register, which are gated by the bit settings in the ERROR_MASK
registers. When an error status bit is HIGH and the corresponding error mask bit is LOW,
the corresponding DATA_ERROR signal is set LOW by the device.
The ERROR_STATUS registers, and correspondingly the DATA_ERROR, VIDEO_ERROR,
and AUDIO_ERROR signals, are cleared at the start of the next video field or when read
via the host interface, which ever condition occurs first.
All bits of the ERROR_STATUS registers are also cleared under any of the following
conditions:
1. LOCKED signal = LOW.
2. 656_BYPASS = LOW.
3. When a change in video standard has been detected.
4. RESET = LOW
Table 4-22 shows the VIDEO_ERROR_STATUS register and VIDEO_ERROR_MASK bits.
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Note: Since the error indication registers are cleared once per field, if an external host
micro is polling the error registers periodically, an error flag may be missed if it is
intermittent, and the polling frequency is less than the field rate.
Table 4-22: Video Error Status Register and Error Disable Mask Bits
Video Error Stat Register
Video Error Mask Register
SAV_ERR (02h, 03h)
SAV_ERR_MASK (037h, 038h)
EAV_ERR (02h, 03h)
EAV_ERR_MASK (037h, 038h)
YCRC_ERR (02h, 03h)
YCRC_ERR_MASK (037h, 038h)
CCRC_ERR (02h, 03h)
CCRC_ERR_MASK (037h, 038h)
LNUM_ERR (02h, 03h)
LNUM_ERR_MASK (037h, 038h)
YCS_ERR (02h, 03h)
YCS_ERR_MASK (037h, 038h)
CCS_ERR (02h, 03h)
CCS_ERR_MASK (037h, 038h)
AP_CRC_ERR (02h)
AP_CRC_ERR_MASK (037h)
FF_CRC_ERR (02h)
FF_CRC_ERR_MASK (037h)
Note: See Section 4.17 for Audio Error Status.
4.14.1 TRS Error Detection
TRS error flags are generated by the GV7601 under the following two conditions:
1. A phase shift in received TRS timing is observed.
2. The received TRS Hamming codes are incorrect.
Both SAV and EAV TRS words are checked for timing and data integrity errors.
For HD mode, only the Y channel TRS codes are checked for errors.
For full HD signals, only DS1 TRS codes are checked for errors.
Both 8-bit and 10-bit TRS code words are checked for errors.
The SAV_ERR bit of the ERROR_STAT register is set HIGH when an SAV TRS error is
detected.
The EAV_ERR bit of the ERROR_STAT register is set HIGH when an EAV TRS error is
detected.
4.14.2 Line Based CRC Error Detection
The GV7601 calculates line based CRCs for HD video signals. CRC calculations are done
for each 10-bit channel (Y and C, DS1 and DS2).
These calculated CRC values are compared with the received CRC values.
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If a mismatch in the calculated and received CRC values is detected for the Y channel
data, the YCRC_ERR bit in the ERROR_STAT register is set HIGH.
If a mismatch in the calculated and received CRC values is detected for the C channel
data, the CCRC_ERR bit in the ERROR_STAT register is set HIGH.
Y or C CRC errors are also generated if CRC values are not received.
Line based CRC errors are only generated when the device is operating in HD mode.
Note: By default, 8-bit to 10-bit TRS remapping is enabled. If an 8-bit input is used, the
HD CRC check is based on the 10-bit remapped value, not the 8-bit value, so the CRC
Error Flag is incorrectly asserted and should be ignored. If 8-bit to 10-bit remapping is
enabled, then CRC correction and insertion should be enabled by setting the
CRC_INS_MASK bit in the PROC_DISABLE register LOW. This ensures that the CRC values
are updated.
4.14.3 EDH CRC Error Detection
The GV7601 also calculates Full Field (FF) and Active Picture (AP) CRC's according to
SMPTE RP165 in support of Error Detection and Handling packets in SD signals.
These calculated CRC values are compared with the received CRC values.
Error flags for AP and FF CRC errors are provided and are shared between the field 1 and
field 2 error conditions.
The AP_CRC_ERR bit in the VIDEO_ERROR_STATUS register is set HIGH when an Active
Picture CRC mismatch has been detected in field 1 or 2.
The FF_CRC_ERR bit in the VIDEO_ERROR_STATUS register is set HIGH when a Full Field
CRC mismatch has been detected in field 1 or 2.
EDH CRC errors are only indicated when the device is operating in SD mode and when
the device has correctly received EDH packets.
4.14.4 HD Line Number Error Detection
If a mismatch in the calculated and received line numbers is detected, the LNUM_ERR
bit in the VIDEO_ERROR_STATUS register is set HIGH.
4.15 Ancillary Data Detection & Indication
The horizontal and vertical blanking regions of a digital video signal may be used to
carry ancillary data packets. The payload of the ancillary data packet can be used to carry
user-defined or proprietary data, which can be sent between an Aviia transmitter and
receiver.
The ancillary data packet must be formatted according to Figure 4-41. The packet must
always begin with the Ancillary Data Flag (ADF), defined as the following 10-bit word
sequence: 000h, 3FFh, 3FFh.
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Type 1 Ancillary Data Packet
MSB
Not b8
Parity bit
UDW252
UDW253
UDW254
UDW255
CS
UDW252
UDW253
UDW254
UDW255
CS
UDW3
UDW2
UDW1
UDW0
DC
DBN
DID
ADF
LSB
User Data Words
Type 2 Ancillary Data Packet
MSB
Not b8
Parity bit
UDW3
UDW2
UDW1
UDW0
DC
SDID
DID
ADF
LSB
User Data Words
Figure 4-41: Ancillary Data Packets
The next data word is the 8-bit Data ID (DID), used to define the contents of the packet.
For example, a unique DID can be used to denote alarm data, with another DID to
denote status data. After the DID, there are two possible options, as shown in
Figure 4-41.
A Type 1 packet defines an 8-bit Data Block Number (DBN) sequence, used to
distinguish successive packets with the same DID. The DBN simply increments with each
packet of the same DID, between 0 and 255.
For a Type 2 packet, an 8-bit Secondary Data ID (SDID) word is defined, which can be
used to denote variants of payloads with the same DID. For example, packets with a DID
to denote error data may distinguish different error types using unique SDID's.
After the DBN or SDID, the next data work is the 8-bit Data Count (DC). This word must
be set to the number of user data words (UDW) that follow the DC, and must not exceed
255 (maximum payload size).
The final word of the ancillary data packet is the 9-bit Checksum (CS). The CS value must
be equal to the nine least significant bits of the sum of the nine least significant bits of
the DID, the DBN or the SDID, the DC and all user data words (UDW) in the packet.
The GV7601 detects ancillary data in both the vertical and horizontal ancillary data
spaces. Status signal outputs Y/1ANC and C/2ANC are provided to indicate the position
of ancillary data in the output data streams. These signals may be programmed for
output on the multi-function I/O port pins (STAT[5:0]).
The GV7601 indicates the presence of all types of ancillary data by simply detecting the
000h, 3FFh, 3FFh (00h, FFh, FFh for 8-bit video) ancillary data preamble.
Note: Both 8 and 10-bit ancillary data preambles are detected by the device.
By default (at power up or after system reset) the GV7601 indicates all types of ancillary
data. Up to 5 types of ancillary data can be specifically programmed for recognition.
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For HD video signals, ancillary data may be placed in both the Y and Cb/Cr video data
streams separately. For SD video signals, the ancillary data is multiplexed and combined
into the YCbCr data space.
For Full HD signals, ancillary data may be placed in either or both of the data streams.
Both data streams are examined for ancillary data.
When operating in HD mode, the Y/1ANC signal is HIGH whenever ancillary data is
detected in the Luma data stream, and C/2ANC is HIGH whenever ancillary data is
detected in the Chroma data stream. The signals are asserted HIGH at the start of the
ancillary data preamble, and remain HIGH until after the ancillary data checksum.
When detecting ancillary data in Full HD data, the Y/1ANC status output is HIGH
whenever DS1 ancillary data is detected and the C/2ANC status output is HIGH
whenever DS2 ancillary data is detected.
When operating in SD mode, the Y/1ANC and C/2ANC signals depend on the output
data format. For 20-bit demultiplexed data, the Y/1ANC and C/2ANC signals operate
independently to indicate the first and last ancillary Data Word position in the Luma
and/or Chroma data streams. For 10-bit multiplexed data, the Y/1ANC signal is HIGH
whenever ancillary data is detected, and the C/2ANC signal is always LOW.
When operating in Full HD mode, the Y/1ANC and C/2ANC flags are both zero if 10-bit
multiplexed output format is selected.
These status signal outputs are synchronous with PCLK and may be used as
clock-enables for external logic, or as write-enables for an external FIFO or other
memory devices.
The operation of the Y/1ANC and C/2ANC signals is shown in Figure 4-42, Figure 4-43,
Figure 4-44 and Figure 4-45.
Note: When I/O processing is disabled, the Y/1ANC and C/2ANC flags may toggle, but
they are invalid and should be ignored.
PC LK
LU M A D ATA O U T
000
3FF
3FF
D ID
DBN
DC
ANC DATA
CHRO M A DATA O UT
000
3FF
3FF
D ID
DBN
DC
ANC DATA ANC DATA ANC DATA
CSUM
BLANK
BLAN K
CSUM
Y/1ANC
C/2ANC
Figure 4-42: Y/1ANC and C/2ANC Signal Timing - HD 20-bit
PC LK
M U L T IP L E X E D Y ’ C b C r
000
000
3FF
3FF
3FF
3FF
Y D ID
CANC
YCSUM
CCSUM
Y/1ANC
C/2ANC
Figure 4-43: Y/1ANC and C/2ANC Signal Timing - HD 10-bit
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PC LK
LU M A D ATA O U T
BLAN K
3FF
D ID
000
3FF
DBN
CHRO M A DATA O UT
ANC DATA ANC DATA
ANC DATA
CSUM
ANC DATA ANC DATA ANC DATA
DC
ANC DATA
BLAN K
BLAN K
BLAN K
CSUM
BLANK
Y/1ANC
C/2ANC
Figure 4-44: Y/1ANC and C/2ANC Signal Timing - SD 20-bit
PC LK
M U L T IP L E X E D Y ’ C b C r
000
3FF
3FF
D ID
DBN
DC
ANC DATA ANC DATA
Y/1ANC
Figure 4-45: Y/1ANC and C/2ANC Signal Timing - SD 10-bit
4.15.1 Programmable Ancillary Data Detection
As described above in Section 4.15, the GV7601 detects and indicates all ancillary data
types by default.
It is possible to program which ancillary data types are to be detected and indicated. Up
to 5 different ancillary data types may be programmed for detection by the GV7601 in
the ANC_TYPE_DS1 registers for SD and HD data.
When so programmed, the GV7601 only indicates the presence of the specified ancillary
data types, ignoring all other ancillary data. For each data type to be detected, the user
must program the DID and/or SDID of that ancillary data type. In the case where no DID
or SDID values are programmed, the GV7601 indicates the presence of all ancillary data.
In the case where one or more, DID and/or SDID values have been programmed, then
only those matching data types are detected and indicated.
The timing of the Y/1ANC and C/2ANC signals in this case is as shown in Figure 4-42,
Figure 4-43, Figure 4-44 and Figure 4-45.
The GV7601 compares the received DID and/or SDID with the programmed values. If a
match is found, ancillary data is indicated.
For any DID or SDID value set to zero, no comparison or match is made. For example, if
the DID is programmed and the SDID is not programmed, the GV7601 only detects a
match to the DID value.
If both DID and SDID values are non-zero, then the received ancillary data type must
match both the DID and SDID before Y/1ANC and/or C/2ANC is set HIGH.
4.15.2 Ancillary Data Checksum Error
The GV7601 calculates checksums for all received ancillary data.
These calculated checksums are compared with the received ancillary data checksum
words.
If a mismatch in the calculated and received checksums is detected, then a checksum
error is indicated.
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When operating in HD mode, the device makes comparisons on both the Y and C
channels separately. If an error condition in the Y channel is detected, the YCS_ERR bit
in the VIDEO_ERROR_STATUS register is set HIGH. If an error condition in the C channel
is detected, the CCS_ERR bit in the VIDEO_ERROR_STATUS register is set HIGH.
When operating in Full HD mode, the device makes comparisons on both the Y (DS1)
and C (DS2) channels separately. If an error condition in the Y channel is detected, the
YCS_ERR bit in the VIDEO_ERROR_STATUS register is set HIGH. If an error condition in
the C channel is detected, the CCS_ERR bit in the VIDEO_ERROR_STATUS register is set
HIGH.
When operating in SD mode, only the YCS_ERR bit is set HIGH when checksum errors are
detected.
4.15.2.1 Programmable Ancillary Data Checksum Calculation
As described above, the GV7601 calculates and compares checksum values for all
ancillary data types by default. It is possible to program which ancillary data types are
checked as described in Section 4.15.1.
When so programmed, the GV7601 only checks ancillary data checksums for the
specified data types, ignoring all other ancillary data.
The YCS_ERR and/or CCS_ERR bits in the VIDEO_ERROR_STATUS register are only set
HIGH if an error condition is detected for the programmed ancillary data types.
4.16 Video Error Correction
In addition to error detection and indication, the GV7601 can also correct errors,
inserting corrected code words, checksums and CRC values into the data stream.
The following processing can be performed by the GV7601:
1. TRS error correction and insertion.
2. HD line based CRC correction and insertion.
3. EDH CRC error correction and insertion.
4. HD line number error correction and insertion.
5. Illegal code re-mapping.
6. Ancillary data checksum error correction and insertion.
All of the above features are only available in video mode (656_BYPASS = HIGH).
To enable these features, the PROC_EN pin must be set HIGH, and the individual feature
must be enabled via bits in the PROC_DISABLE register.
The PROC_DISABLE register contains one bit for each processing feature allowing each
one to be enabled/disabled individually.
By default (at power up or after system reset), all of the PROC_DISABLE register bits are
LOW, enabling all of the processing features.
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To disable an individual processing feature, set the corresponding PROC_DISABLE bit
HIGH in the PROC_DISABLE register.
Table 4-23: PROC_DISABLE Register Bits
Processing Feature
PROC_DISABLE Register Bit
TRS error correction and insertion
TRS_INS
Y and C line based CRC error correction
CRC_INS
Y and C line number error correction
LNUM_INS
Ancillary data check sum correction
ANC_CHECKSUM_INSERTION
EDH CRC error correction
EDH_CRC_INS
Illegal code re-mapping
ILLEGAL_WORD_REMAP
H timing signal configuration
H_CONFIG
Update EDH Flags
EDH_FLAG_UPDATE
Audio Data Extraction
AUDIO_SEL
Ancillary Data Extraction
ANC_DATA_EXT
Audio Extraction
AUD_EXT
4.16.1 TRS Correction & Insertion
When TRS Error Correction and Insertion is enabled, the GV7601 generates and
overwrites TRS code words as required.
TRS Word Generation and Insertion is performed using the timing generated by the
Timing Signal Generator, providing an element of noise immunity over using just the
received TRS information.
This feature is enabled when the PROC_EN pin is HIGH and the TRS_INS bit in the
PROC_DISABLE register is set LOW.
Note: Inserted TRS code words will always be 10-bit compliant, irrespective of the bit
depth of the incoming video stream.
4.16.2 Line Based CRC Correction & Insertion
When CRC Error Correction and Insertion is enabled, the GV7601 generates and inserts
line based CRC words into both the Y and C channels of the data stream.
Line based CRC word generation and insertion only occur in HD mode, and is enabled
in when the PROC_EN pin is HIGH and the CRC_INS bit in the PROC_DISABLE register is
set LOW.
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4.16.3 Line Number Error Correction & Insertion
When Line Number Error Correction and Insertion is enabled, the GV7601 calculates and
inserts line numbers into the output data stream. Re-calculated line numbers are
inserted into both the Y and C channels.
Line number generation is in accordance with the relevant HD or Full HD video standard
as determined by the Automatic Standards Detection block.
This feature is enabled when the device is operating in HD mode, the PROC_EN pin is
HIGH and the LNUM_INS bit in the PROC_DISABLE register is set LOW.
4.16.4 Ancillary Data Checksum Error Correction & Insertion
When ancillary data Checksum Error Correction and Insertion is enabled, the GV7601
generates and inserts ancillary data checksums for all ancillary data words by default.
Where user specified ancillary data has been programmed (see Section 4.15.1), only the
checksums for the programmed ancillary data are corrected.
This feature is enabled when the PROC_EN pin is HIGH and the ANC_CSUM_INS bit in
the PROC_DISABLE register is set LOW.
4.16.5 EDH CRC Correction & Insertion
When EDH CRC Error Correction and Insertion is enabled, the GV7601 generates and
overwrites full field and active picture CRC check-words.
Additionally, the device sets the active picture and full field CRC 'V' bits HIGH in the EDH
packet. The AP_CRC_V and FF_CRC_V register bits only report the received EDH validity
flags.
EDH FF and AP CRC's are only inserted when the device is operating in SD mode, and if
the EDH data packet is detected in the received video data.
Although the GV7601 modifies and inserts EDH CRC's and EDH packet checksums, EDH
error flags are only updated when the EDH_FLAG_UPDATE bit is LOW.
This feature is enabled in SD mode, when the PROC_EN pin is HIGH and the
EDH_CRC_INS bit in the PROC_DISABLE register is set LOW.
4.16.6 Illegal Word Remapping
All words within the active picture (outside the horizontal and vertical blanking periods),
between the values of 3FCh and 3FFh are re-mapped to 3FBh. All words within the
active picture area between the values of 000h and 003h are remapped to 004h.
This feature is enabled when the PROC_EN pin is HIGH and the ILLEGAL_WORD_REMAP
bit in the PROC_DISABLE register is set LOW.
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4.16.7 TRS and Ancillary Data Preamble Remapping
8-bit TRS and ancillary data preambles are re-mapped to 10-bit values. 8-bit to 10-bit
mapping of TRS headers is only supported if the TRS values are 3FC 000 000. Other
values such as 3FD, 3FE, 001, and 003 are not supported. This feature is enabled by
default, and cannot be disabled via the PROC_DISABLE register.
4.16.8 Ancillary Data Extraction
Ancillary data may be extracted externally from the GV7601 output stream using the
Y/1ANC and C/2ANC signals, and external logic.
As an alternative, the GV7601 includes a memory block, which extracts ancillary data
using read access via the host interface to ease system implementation. The memory
block stores up to 2048 x 16 bit words of ancillary data in two separate 1024 word
memory banks. Data is accessed from both memory banks using the same host interface
addresses, 800h to BFFh (see Table 4-36: Ancillary Data Extraction Memory Access
Registers).
The device writes the contents of ANC packets into memory, starting with the first
Ancillary Data Flag (ADF), followed by up to 1024 words.
All Data Identification (DID), Secondary Data Identification (SDID), Data Count (DC), user
data, and checksum words are written into the device memory.
The device detects ancillary data packet DID's placed anywhere in the video data
stream, including the active picture area.
In HD and full HD modes, ancillary data from the Y channel or DS1 is placed in the Least
Significant Word (LSW) of the memory, allocated to the lower 8 bits of each memory
address.
Ancillary data from the C channel or DS2 is placed in the Most Significant Word (MSW)
(upper 8 bits) of each memory address.
In SD mode, ancillary data is placed in the LSW of the memory. The MSW is set to zero.
If the ANC_TYPE registers are all set to zero, the device extracts all types of ancillary data.
If programmable ancillary data extraction is required, then up to five types of ancillary
data to be extracted can be programmed in the ANC_TYPE registers (see Section 4.15.1).
Additionally, the lines from which the packets are to be extracted can be programmed
into the ANC_LINEA[10:0] and ANC_LINEB[10:0] registers, allowing ancillary data from a
maximum of two lines per frame to be extracted. If only one line number register is
programmed (with the other set to zero), ancillary data packets are extracted from one
line per frame only. When both registers are set to zero, the device extracts packets from
all lines.
To start Ancillary Data Extraction, the ANC_DATA_EXT_MASK bit of the host interface
must be set LOW. Ancillary Data Packet Extraction begins in the following frame (see
Figure 4-46: Ancillary Data Extraction - Step A).
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Bank B
Bank A
Application Layer
Read Pointer
0
ANC DATA
800h
0
800h
BFFh
1023
BFFh
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
Internal Write
Pointer
1023
ANC_DATA_SWITCH = LOW
Figure 4-46: Ancillary Data Extraction - Step A
Ancillary data is written into Bank A until full. The Y/1ANC and C/2ANC output flags can
be used to determine the length of the ancillary data extracted and when to begin
reading the extracted data from memory.
While the ANC_DATA_EXT_MASK bit is set LOW, the ANC_DATA_SWITCH bit can be set
HIGH during or after reading the extracted data. New data is then written into Bank B (up
to 1024 x 16-bit words), at the same host interface addresses (see Figure 4-47: Ancillary
Data Extraction - Step B).
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Bank B
Bank A
0
ANC DATA
800h
Internal Write
Pointer
0
800h
1023
BFFh
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
Application Layer
Read Pointer
ANC DATA
ANC DATA
1023
BFFh
ANC_DATA_SWITCH = HIGH
Figure 4-47: Ancillary Data Extraction - Step B
To read the new data, toggle the ANC_DATA_SWITCH bit LOW. The old data in Bank A is
cleared to zero and extraction continues in Bank B (see Figure 4-48: Ancillary Data
Extraction - Step C).
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Bank B
Bank A
0
Application Layer
800h
Read Pointer
0
ANC DATA
800h
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
Internal Write
Pointer
1023
BFFh
1023
BFFh
ANC_DATA_SWITCH = LOW
Figure 4-48: Ancillary Data Extraction - Step C
If the ANC_DATA_SWITCH bit is not toggled, extracted data is written into Bank B until
full. To continue extraction in Bank A, the ANC_DATA_SWITCH bit must be toggled HIGH
(see Figure 4-49: Ancillary Data Extraction - Step D).
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Bank B
Bank A
Internal Write
Pointer
0
800h
0
ANC DATA
800h
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
ANC DATA
Application Layer
Read Pointer
ANC DATA
ANC DATA
1023
BFFh
1023
BFFh
ANC_DATA_SWITCH = HIGH
Figure 4-49: Ancillary Data Extraction - Step D
Toggling the ANC_DATA_SWITCH bit LOW returns the process to step A (Figure 4-46).
Note: Toggling the ANC_DATA_SWITCH must occur at a time when no extraction is
taking place, i.e. when the both the Y/1ANC and C/2ANC signals are LOW.
To turn extraction off, the ANC_DATA_EXT_MASK bit must be set HIGH.
In HD mode, the device can detect ancillary data packets in the Luma video data only,
Chroma video data only, or both. By default (at power-up or after a system reset) the
device extracts ancillary data packets from the luma channel only.
In Full HD mode, the device can detect ancillary data packets in Luma video (DS1) only,
Chroma video (DS2) only, or both. By default (at power-up or after a system reset) the
device extracts ancillary data packets from DS1 only.
To extract packets from the Chroma/DS2 channel only, the HD_ANC_C/2 bit of the host
interface must be set HIGH. To extract packets from both Luma/DS1 and Chroma/DS2
video data, the HD_ANC_Y/1_C/2 bit must be set HIGH (the setting of the HD_ANC_C/2
bit is ignored).
The default setting of both the HD_ANC_C/2 and HD_ANC_Y/1_C/2 is LOW. The setting
of these bits is ignored when the device is configured for SD video standards.
Ancillary data packet extraction and deletion is disabled when the PROC_EN pin is set
LOW.
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After extraction, the ancillary data may be deleted from the video stream by setting the
ANC_DATA_DELETE bit of the host interface HIGH. When set HIGH, all existing ancillary
data is removed and replaced with blanking values. If any of the ANC_TYPE registers are
programmed with a DID and/or DID and SDID, only the ancillary data packets with the
matching ID's are deleted from the video stream.
Note1: After the ancillary data determined by the ANC_TYPE registers has been deleted,
other existing ancillary data may not be contiguous. The device does not concatenate
the remaining ancillary data.
Note2: Reading extracted ancillary data from the host interface must be performed
while there is a valid video signal present at the serial input and the device is locked
(LOCKED signal is HIGH).
4.17 Audio De-embedder
The GV7601 includes an integrated audio de-embedder which is enabled by default in
video mode. It can be disabled by setting the AUDIO_EN pin LOW, or by setting the host
interface AUD_EXT_MASK bit to HIGH, or by keeping PROC_EN pin LOW. In non-video
modes, the audio de-embedder is not active.
Up to eight channels of audio may be extracted from the received serial digital video
stream. The output signal formats supported by the device include AES/EBU or S/PDIF,
I2S (default) and industry standard serial digital formats.
16, 20 and 24-bit audio bit depths are supported for 48kHz synchronous audio for SD.
16, 20 and 24-bit, 48kHz, synchronous or asynchronous audio bit depths are supported
for HD mode.
Additional audio processing features include audio mute on loss of lock, de-embed and
delete, group selection, audio output re-mapping, ECC error detection and correction
(HD mode only), and audio channel status extraction.
4.17.1 Serial Audio Data I/O Signals
The Serial Audio Data I/O pins are listed in Table 4-24: Serial Audio Pin Descriptions.
Table 4-24: Serial Audio Pin Descriptions
Audio
Pin Name
AUDIO_EN
Description
Enable Input for Audio Processing
AOUT1/2
Serial Audio Output; Channels 1 and 2
AOUT3/4
Serial Audio Output; Channels 3 and 4
AOUT5/6
Serial Audio Output; Channels 5 and 6
AOUT7/8
Serial Audio Output; Channels 7 and 8
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Table 4-24: Serial Audio Pin Descriptions (Continued)
Audio
Pin Name
Description
ACLK
64fs clock
WCLK
Word clock
MCLK
Audio Master Clock, selectable 128fs, 256fs, or 512fs
The timing of the serial audio output signals, the WCLK output signal, and the ACLK
output signal is as shown in Figure 4-50: ACLK to Data and WCLK Signal Output Timing.
Audio I/O Timing Specs:
Audio Outputs:
128fs = 162.76ns (AES/EBU)
64fs = 32.52ns (other modes)
AOUT*
A0
A1
80%
A2
A3
80%
ACLK
20%
t oh
20%
tf
tr
t od
Audio Outputs
1.8V
3.3V
AOUT
t oh
tr
(min)
tf
Cload
1.500ns
0.600ns
6pF
t od
tr
(max)
tf
Cload
7.000ns
2.200ns
15pF
t oh
tr
(min)
tf
Cload
1.500ns
0.600ns
6pF
t od
7.000ns
tr
(max)
tf
Cload
2.300ns
15pF
Figure 4-50: ACLK to Data and WCLK Signal Output Timing
When AUDIO_EN is set HIGH, audio extraction is enabled and the audio output signals
are extracted from the video data stream. When set LOW, the serial audio outputs, ACLK
and WCLK outputs are set LOW.
In addition, all functional logic associated with audio extraction is disabled to reduce
power consumption.
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4.17.2 Serial Audio Data Format Support
The GV7601 supports the following serial audio data formats:
•
I2S (default)
•
AES/EBU or S/PDIF
•
Serial Audio Left Justified, MSB First
•
Serial Audio Left Justified, LSB First
•
Serial Audio Right Justified, MSB First
•
Serial Audio Right Justified, LSB First (this mode is not supported in SD)
By default (at power up or after system reset) I2S is selected. The other data formats are
selectable via the host interface using the AMA/AMB[1:0] bits.
Table 4-25: Audio Output Formats
AMA/AMB[1:0]
Audio Output Format
00
AES/EBU or S/PDIF audio output
01
Serial audio output: Left Justified; MSB first
10
Serial audio output: Right Justified; MSB first
11
I2S (Default)
The serial audio output formats may use LSB first according to the settings of the control
bits LSB_FIRSTA, LSB_FIRSTB, LSB_FIRSTC, and LSB_FIRSTD. When in I2S mode, these
control bits must all be set LOW (default).
When I2S format is desired, both groups must be set to I2S (i.e. AMA = AMB = 11). This is
because they share the same WCLK.
Channel A (Left)
WCLK
Channel B (Right)
ACLK
AOUT
23 22
MSB
6
5
4
3
2
1
23 22
MSB
0
LSB
6
5
4
3
2
1
0
LSB
Figure 4-51: I2S Audio Output Format
WCLK
Channel A (Left)
Channel B (Right)
ACLK
AOUT
0
1
2
Preamble
3
4
5
6
AUX
7
8
LSB
27
28
MSB V
29 30
31
U
P
C
0
1
2
3
Preamble
4
5
6
AUX
7
8
LSB
27
28 29
MSB V
U
30
31
C
P
Figure 4-52: AES/EBU or S/PDIF Audio Output Format
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WCLK
Channel A (Left)
Channel B (Right)
ACLK
AOUT
23 22 21
MSB
6
5
4
3
2
1
0
LSB
23 22 21
MSB
6
5
4
3
2
1
0
LSB
Figure 4-53: Serial Audio, Left Justified, MSB First
WCLK
Channel A (Left)
Channel B (Right)
ACLK
AOUT
0 1
LSB
2
17 18 19 20 21 22 23
MSB
0
1
LSB
2
17 18 19 20 21 22 23
MSB
Figure 4-54: Serial Audio, Left Justified, LSB First
Channel A (Left)
WCLK
Channel B (Right)
ACLK
23 22 21 20 19 18 17
MSB
AOUT
2
1
0
LSB
23 22 21 20 19 18 17
MSB
2
1
0
LSB
Figure 4-55: Serial Audio, Right Justified, MSB First
Channel A (Left)
WCLK
Channel B (Right)
ACLK
AOUT
0 1
LSB
2
36 4
5
21 22 23
MSB
0 1
LSB
2
36 4
5
21 22 23
MSB
Figure 4-56: Serial Audio, Right Justified, LSB First
4.17.2.1 AES/EBU or S/PDIF Mode
In AES/EBU or S/PDIF output mode, the audio de-embedder uses a 128fs (6.144MHz
audio bit clock) clock as shown in Figure 4-57.
6.144MHz
AMCLK
(128fs)
AOUT1/2, AOUT3/4
AOUT5/6, AOUT7/8
Figure 4-57: AES/EBU or S/PDIF Audio Output to Bit Clock Timing
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4.17.2.2 Audio Data Packet Extraction Block
The audio de-embedder looks for audio data packets on every line of the incoming
video.
The audio data must be embedded by Aviia compliant transmitter, such as the GV7600.
For Full HD formats, the audio data words must be embedded only in DS2.
The Audio Group Detect registers are set HIGH when audio data packets with a
corresponding group DID are detected in the input video stream. The host interface
reports the individual audio groups detected.
Table 4-26: Audio Data Packet Detect Register
Name
Description
Default
ADPG4_DET
Audio Group Four Data Packet Detection (1: Detected)
0
ADPG3_DET
Audio Group Three Data Packet Detection (1: Detected)
0
ADPG2_DET
Audio Group Two Data Packet Detection (1: Detected)
0
ADPG1_DET
Audio Group One Data Packet Detection (1: Detected)
0
When an audio data packet with a DID set in IDA[1:0] and IDB[1:0] is detected, the audio
sample information is extracted and written into the audio FIFO.
The embedded audio group selected by IDA[1:0] is described henceforth in this
document as Group A or Primary Group. The embedded audio group selected by
IDB[1:0] is described henceforth in this document as Group B or Secondary Group.
Due to the large size of the horizontal ancillary data space in 720p/24, 720p/25 and
720p/30 video standards, the maximum number of ancillary data words the audio
de-embedder can process is limited to 1024 when receiving these standards.
4.17.2.3 Audio Control Packets
Audio control packers carry additional information about the embedded audio sample
data, such as audio sample rate, audio validity, audio synchronization, and
audio-to-video timing relationship (delay). For both SD and HD formats, an Aviia
transmitter, such as the GV7600, embeds audio control packets, formatted according to
the following Society of Motion Pictures and Television Engineers (SMPTE) standards:
SMPTE ST 272-2004 for SD video and SMPTE ST 299-2004 for HD video formats.
The GV7601 automatically detects the presence of audio control packets in the video
stream. When audio control packets for audio Group A are detected, the CTRA_DET bit
of the host interface is set HIGH. When audio control packets for audio Group B are
detected, the CTRB_DET bit of the host interface is set HIGH.
The audio control packet data is accessible via the host interface.
Note: In SD, the control packet host interface registers are updated with new control
packet values, after the CTRA_DET/CTRB_DET flags are cleared. In HD, the update
happens automatically.
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4.17.2.4 Setting Packet DID
Table 4-27 below, shows the 2-bit host interface setting for the audio group DID's.
For 24-bit audio support in SD mode, extended audio packets for Group A must have the
same group DID set in IDA[1:0] of the host interface. Extended audio packets for Group
B must have the same group DID set in IDB[1:0] of the host interface.
The audio de-embedder automatically detects the presence of extended audio packets.
When detected, the audio output format is set to 24-bit audio sample word length.
The audio de-embedder defaults to audio Groups One and Two, where Group A is
extracted from packets with audio Group One DID, and Group B from packets with audio
Group Two DID.
Table 4-27: Audio Group DID Host Interface Settings
Audio
Group
SD Data
DID
SD Extended
DID
HD Data
DID
SD Control
DID
HD Control
DID
Host Interface Register Setting
(2-bit)
1
2FFh
1FEh
2E7h
1EFh
1E3h
00b
2
1FDh
2FCh
1E6h
2EEh
2E2h
01b
3
1FBh
2FAh
1E5h
2EDh
2E1h
10b
4
2F9h
1F8h
2E4h
1ECh
1E0h
11b
Table 4-28: Audio Data and Control Packet DID Setting Register
Name
Description
Default
IDA[1-0]
Group A Audio data and control packet DID setting
00b
IDB[1-0]
Group B Audio data and control packet DID setting
01b
4.17.2.5 Audio Packet Delete Block
To delete all ancillary data with a group DID shown in Table 4-27, the ALL_DEL bit in the
host interface must be set HIGH.
4.17.2.6 ECC Error Detection & Correction Block (HD Mode Only)
For HD video formats, the embedded audio sample data is protected for bit errors using
error correction codes (ECC). The error correction codes are carried in the same packet
as the audio sample data, to allow error detection and correction at the Aviia receiver.
The GV7601 performs BCH(31,25) forward error detection and correction. The error
correction for all embedded audio data packets is activated when the host interface
ECC_OFF bit is set LOW (default LOW). The audio de-embedder corrects any errors in
both the audio output and the embedded packet.
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When a one-bit error is detected in a bit array of the ECC protected region of the audio
data packet with audio group DID set in IDA[1:0], the ECCA_ERROR flag is set HIGH.
When a one-bit error is detected in the ECC protected region of the audio data packet
with audio group DID set in IDB[1:0], the ECCB_ERROR flag is set HIGH.
Figure 4-58 shows examples of error correction and detection. Up to 8 bits in error can
be corrected, providing each bit error is in a different bit array (shown below). When
there are two or more bits in error in the same 24-bit array, the errors are detected, but
not corrected.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
24-bit array
ADF ADF ADF DID DBN DC
CLK CLK CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors corrected
ADF ADF ADF DID DBN DC
CLK CLK
CH1 CH1 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH4 CH4 CH4 CH4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Errors detected but not corrected
Figure 4-58: ECC 24-bit Array and Examples
4.17.3 Audio Processing
4.17.3.1 Audio Clock Generation
For SD and HD audio, a single set of audio frequencies is generated for all audio
channels, using a Direct Digital Period Synthesizer (DDPS) to minimize jitter.
In HD modes, the input control for the DDPS is derived from the two embedded audio
clock phase words in the audio data packet corresponding to Group A. The audio clock
phase information used is taken from the first embedded audio packet in the HANC
space.
The audio de-embedder also includes a Flywheel block to overcome any inconsistencies
in the embedded audio clock phase information.
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4.17.3.2 Audio Crosspoint Block
The Audio Crosspoint is used for audio output channel re-mapping. This feature allows
any of the selected audio channels in Group A or Group B to be output on any of the
eight output channels. The default setting is for one to one mapping, where AOUT1/2 is
extracted from Group A CH1 and CH2, AOUT3/4 is extracted from Group A CH3 and CH4,
and so on.
Note: If audio samples from embedded audio packets with the group set in IDA[1:0] are
to be paired with samples from the group set in IDB[1:0], all of the channels must have
been derived from the same Word Clock and must be synchronous.
The output channel is set in the OPn_SRC[2:0] host interface registers. Table 4-29 lists
the 3-bit address for audio channel mapping.
Table 4-29: Audio Channel Mapping Codes
Audio Output Channel
3-bit Host Interface Source Address
1
000
2
001
3
010
4
011
5
100
6
101
7
110
8
111
4.17.3.3 Serial Audio Output Word Length
The audio output, in serial modes, has a selectable 24, 20 or 16-bit sample word length.
The ASWL[1:0] host interface register is used to configure the audio output sample word
length. Figure 4-30 shows the host interface 2-bit code for setting the audio sample
word length. When the presence of extended audio packets is detected in SD mode, the
GV7601 defaults to 24-bit audio sample word length.
Table 4-30: Audio Sample Word Lengths
ASWL[1:0]
Audio Sample Word Length
(SD)
Audio Sample Word Length
(HD)
00
24-bit
24-bit
01
20-bit
20-bit
10
16-bit
16-bit
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Table 4-30: Audio Sample Word Lengths (Continued)
ASWL[1:0]
Audio Sample Word Length
(SD)
Audio Sample Word Length
(HD)
11
Auto 24/20-bit (Default)
Reserved (Default)
Note: By default, at power-up, the word length is set to 12 bits. The desired word length
should be programmed through the host interface.
4.17.3.4 Audio Channel Status
The GV7601 detects the AES/EBU or S/PDIF Audio Channel Status (ACS) block
information for each of the selected channel pairs.
ACS data detection is indicated by corresponding ACS_DET flag bits in the host
interface. The flag is cleared by writing to the same location.
4.17.3.4.1 Audio Channel Status Read
ACS data is available separately for each of the channels in a stereo pair. The GV7601
defaults to reading the first channel of each pair. There are 184 bits in each ACS packet,
which are written to twelve 16-bit right-justified registers in the host interface.
The ACS_USE_SECOND bit (default LOW) selects the second channel in each audio pair
when set HIGH.
Once all of the ACS data for a channel has been acquired, the corresponding ACS_DET
bit is set, and acquisition stops. The ACS data is overwritten with new data when the
ACS_DET bit is cleared in the system.
4.17.3.4.2 Audio Channel Status Regeneration
When the ACS_REGEN bit in the host interface is set HIGH, the audio de-embedder
embeds the 24 bytes of the Audio Channel Status information programmed in the
ACSR[183:0] registers into the 'C' bit of the AES/EBU or S/PDIF outputs. The same Audio
Channel Status information is used for all output channels.
In order to apply ACSR data;
•
Set the ACS_REGEN bit to logic HIGH
•
Write the desired ACSR data to the ACSR registers
•
Set the ACS_APPLY bit to HIGH
At the next status boundary, the device outputs the contents of the ACSR registers as
ACS data. This event may occur at a different time for each of the output channels. While
waiting for the status boundary, the device sets the appropriate ACS_APPLY_WAIT[A:D]
flag.
Table 4-31 shows the host interface default settings for the Audio Channel Status block.
The audio de-embedder automatically generates the CRC word.
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Table 4-31: Audio Channel Status Information Registers
Name
Description
Default
ACSR[7-0]
Audio channel status block byte 0 set. Used when ACS_REGEN is set HIGH
85h
ACSR[15-8]
Audio channel status block byte 1 set. Used when ACS_REGEN is set HIGH
08h
ACSR[23-16]
Audio channel status block byte 2 set. Used when ACS_REGEN is set HIGH
28h (SD) 2Ch (HD)
ACSR[31-24]:
ACSR[183-176]
Audio channel status block data for bytes 3 to 22. Used when ACS_REGEN is set HIGH
00h
ACS_REGEN
Audio channel status regenerate
0
ACS_APPLY
Apply new ACSR data
0
Waiting to apply new ACSR data
0
ACS_APPLY_W
AIT[A:D]
ACS[7-0]:
Audio channel status block data for bytes 0 to 22
ACS[183-176]
00h: 00h
Table 4-31: Audio Channel Status Block for Regenerate Mode Default Settings
Name
Byte
Bit
Default
Mode
PRO
0
0
1b
Professional use of channel status block
Emphasis
0
2-4
100b
100b None. Rec. manual override disabled
Sample Frequency
0
6-7
01b
48kHz. Manual override or auto disabled
Channel Mode
1
0-3
0001b
Two channels. Manual override disabled
000b
SD Modes: Maximum audio word length is 20 bits
AUX
2
0-2
001b
HD Mode: Maximum audio word length is 24 bits
Source Word Length
2
3-5
101b
Maximum word length (based on AUX setting).
24-bit for HD Modes; 20-bit for SD Modes
All other bits set to zero
4.17.3.5 Audio Mute
When the MUTE bits in the host interface are set HIGH, the audio outputs are muted (all
audio sample bits are set to zero). To set all the audio output channels to mute, set the
host interface MUTE_ALL bit HIGH.
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Table 4-32: Audio Mute Control Bits
Name
MUTE_ALL
Description
Default
Ch1-8 audio mute enable (1: Enabled)
0
MUTE8
Ch8 audio mute enable (1: Enabled)
0
MUTE7
Ch7 audio mute enable (1: Enabled)
0
MUTE6
Ch6 audio mute enable (1: Enabled)
0
MUTE5
Ch5 audio mute enable (1: Enabled)
0
MUTE4
Ch4 audio mute enable (1: Enabled)
0
MUTE3
Ch3 audio mute enable (1: Enabled)
0
MUTE2
Ch2 audio mute enable (1: Enabled)
0
MUTE1
Ch1 audio mute enable (1: Enabled)
0
4.17.3.5.1 Mute On Loss Of Lock
When the GV7601 loses lock (LOCKED signal is LOW), the device sets all audio outputs
LOW (no audio formatting is performed). The ACLK, WCLK and MCLK outputs are also
forced LOW.
4.17.4 Error Reporting
4.17.4.1 Data Block Number Error
When the 1-255 count sequence in the Data Block Number (DBN) word of Group A audio
data packets is discontinuous, the DBNA_ERR bit in the host interface is set HIGH. When
the 1-255 count sequence in the DBN word of Group B audio data packets is
discontinuous, the DBNB_ERR bit is set HIGH. The DBNx_ERR flags are in register 401h
for SD, and register 201h for HD.
The DBNA_ERR and DBNB_ERR flags also have associated error interrupt mask register
flags for configuration of error reporting in the Receiver. The interrupt mask flags for SD
are in register 407h, and register 207h for HD. The DBNA_ERR and DBNB_ERR flags
remains set until cleared by writing to these locations.
4.17.4.2 ECC Error
The GV7601 monitors the ECC error status of the two selected audio groups, as
described in Section 4.17.2.6 on page 95.
The ECC[N]_ERROR flags also have an associated error interrupt mask register flag for
configuration of error reporting. The ECC[N]_ERROR flags remain set until read via the
host interface. The ECC error flags are in register 203h with associated error mask flags
in register 207h.
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4.18 Gennum Serial Peripheral Interface
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow
the system to access additional status and control information through configuration
registers in the GV7601.
The GSPI is comprised of a Serial Data Input signal (SDIN), Serial Data Output signal
(SDOUT), an active low Chip Select (CS), and a Burst Clock (SCLK).
Because these pins are shared with the JTAG interface port, an additional control signal
pin JTAG_EN is provided.
When JTAG_EN is LOW, the GSPI interface is enabled. When JTAG_EN is HIGH, the JTAG
interface is enabled.
When operating in GSPI mode, the SCLK, SDIN, and CS signals must be provided by the
system. The SDOUT pin is a non-clocked loop-through of SDIN and may be connected
to the SDIN of another device, allowing multiple devices to be connected to the GSPI
chain. See Section 4.18.2 for details. The interface is illustrated in the Figure 4-59.
Application Host
GV7601
SCLK
CS
SDIN
SDOUT
SCLK
CS1
SDOUT
GV7601
SCLK
CS2
CS
SDIN
SDOUT
SDIN
Figure 4-59: GSPI Application Interface Connection
All read or write access to the GV7601 is initiated and terminated by the system host
processor. Each access always begins with a Command/Address Word, followed by a
data write to, or data read from, the GV7601.
4.18.1 Command Word Description
The Command Word consists of a 16-bit word transmitted MSB first and contains a
read/write bit, an Auto-Increment bit and a 12-bit address.
MSB
R/W
LSB
RSV
RSV
AutoInc
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Figure 4-60: Command Word Format
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Command Words are clocked into the GV7601 on the rising edge of the Serial Clock
SCLK, which operates in a burst fashion. The chip select (CS) signal must be set low a
minimum of 1.5ns (t0 in Figure 4-62) before the first clock edge to ensure proper
operation.
When the Auto-Increment bit is set LOW, each Command Word must be followed by
only one Data Word to ensure proper operation.
If the Auto-Increment bit is set HIGH, the following Data Word is written into the address
specified in the Command Word, and subsequent Data Words is written into
incremental addresses from the first Data Word. This facilitates multiple address writes
without sending a Command Word for each Data Word.
4.18.2 Data Read or Write Access
During a read sequence (Command Word R/W bit set HIGH) serial data is transmitted or
received MSB first, synchronous with the rising edge of the serial clock SCLK. The Chip
Select (CS) signal must be set low a minimum of 1.5ns (t0 in Figure 4-62) before the first
clock edge to ensure proper operation. The first bit (MSB) of the Serial Output (SDOUT)
is available (t5 in Figure 4-63) following the last falling SCLK edge of the read Command
Word, the remaining bits are clocked out on the negative edges of SCLK.
Note: When several devices are connected to the GSPI chain, only one CS may be
asserted during a read sequence.
During a write sequence (Command Word R/W bit set LOW), a wait state of 37.1ns (t4 in
Figure 4-62) is required between the Command Word and the following Data Word. This
wait state must also be maintained between successive Command Word/Data Word
write sequences. When Auto Increment mode is selected (AutoInc = 1), the wait state
must be maintained between successive Data Words after the initial Command
Word/Data Word sequence.
During the write sequence, all Command and following Data Words input at the SDIN
pin are output at the SDOUT pin unchanged. When several devices are connected to the
GSPI chain, data can be written simultaneously to all the devices which have CS set LOW.
MSB
D15
LSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4-61: Data Word Format
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R/W
SDOUT
RSV
RSV
0
RSV
RSV
3
t
A11
A11
Auto
_Inc
Auto
_Inc
1
t
R/W
SDOUT
RSV
RSV
RSV
RSV
A11
A11
Auto
_Inc
Auto
_Inc
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Figure 4-63: Read Mode
R/W
SDIN
CS
SCLK
Figure 4-62: Write Mode
R/W
SDIN
CS
SCLK
t
2
A10
A10
A10
A10
t
A9
A9
A9
A9
A8
A8
A8
A8
A7
A7
A7
8
A7
t
A6
A6
A6
A6
A5
A5
Write and Read Mode timing for the GSPI interface;
4.18.3 GSPI Timing
A5
A5
A4
A4
A4
A4
A3
A3
A3
A3
A2
A2
A1
A1
A0
A0
A0
A0
t
5
4
D15
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A2
A2
A1
A1
t
D14
D15
D15
6
D13
t
D14
D14
D12
D13
D13
D11
D12
D12
D10
D11
D11
D9
D10
D10
D9
D9
D8
D8
D8
D7
D7
D7
D6
D6
D6
D5
D5
D5
D3
D3
D3
D2
D2
D2
D0
D0
D0
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D1
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D4
D4
D4
t
4.18.3.1 GSPI Timing Delays
SDIN to SDOUT combinational path for daisy chain connection of multiple GV7601.
t DELAY
SDIN
data_0
50%
SDOUT
data_0
50%
Figure 4-64: GV7601 GSPI Timing Delays
Table 4-34: GV7601 GSPI Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input data delay time
tDELAY
50% levels;
1.8V operation
−
−
13.1
ns
Input data delay time
tDELAY
50% levels;
3.3V operation
−
−
9.7
ns
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4.19 Host Interface Register Maps
Note: The GV7601 only accepts write/read commands to/from the Audio Register Maps
when the audio de-embedder is locked to the incoming video data rate. The Video
Register Map is always active, whether valid serial input data is present or not.
Note: ROCW denotes register bits which are Read Only, but which must be cleared by
writing a one to the same bit location (Read Only Clear on Write).
4.19.1 Video Core Registers
Table 4-33: Video Core Configuration and Status Registers
Address
Register Name
Bit
Description
R/W
Default
RSVD
15
Reserved.
R
0
TRS_WORD_REMAP
_DISABLE_MASK
14
Disables 8-bit TRS word remapping.
R/W
0
RSVD
13
Reserved.
R/W
0
EDH_FLAG_UPDATE
_MASK
12
Disables updating of EDH error flags.
R/W
0
EDH_CRC_INS_MASK
11
Disables EDH_CRC error correction and insertion.
R/W
0
R/W
0
Selects the H blanking indication:
H_CONFIG
10
HIGH = TRS based blanking - the H output is set HIGH
for the entire horizontal blanking period as indicated
by the H bit in the received TRS signals.
LOW = Active line blanking - the H output is HIGH for
all the horizontal blanking period, including the EAV
and SAV TRS words.
This signal is only valid when 861_EN is set to '0'.
000h
ANC_DATA_EXT_MASK
9
Disables ancillary data extraction.
R/W
0
AUD_EXT_MASK
8
Disables audio extraction block.
R/W
0
861_EN_PIN_DISABLE
7
Disable 861_EN pin control when set to '1', and use
TIMING_861 bit instead.
R/W
0
TIMING_861
6
HIGH = CEA-861 timing output.
LOW = Digital FVH timing output.
R/W
0
RSVD
5
Reserved.
R/W
0
ILLEGAL_WORD_REMAP
_MASK
4
Disables illegal word remapping.
R/W
0
ANC_CHECKSUM
_INSERTION_MASK
3
Disables insertion of ancillary data checksums.
R/W
0
CRC_INS_MASK
2
Disables insertion of HD CRC words.
R/W
0
LNUM_INS_MASK
1
Disables insertion of line numbers.
R/W
0
TRS_INS_MASK
0
Disables insertion of TRS words.
R/W
0
Selects the output timing reference format:
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
001h
Register Name
Bit
Description
R/W
Default
RSVD
15-0
Reserved.
R/W
256
RSVD
15-11
Reserved.
ROCW
0
VD_STD_ERR
10
Video Standard Error indication.
ROCW
0
FF_CRC_ERR
9
EDH Full Frame CRC error indication.
ROCW
0
AP_CRC_ERR
8
EDH Active Picture CRC error indication.
ROCW
0
RSVD
7
Reserved.
ROCW
0
CCS_ERR
6
Chroma ancillary data checksum error indication.
ROCW
0
YCS_ERR
5
Luma ancillary data checksum error indication.
ROCW
0
CCRC_ERR
4
Chroma CRC error indication.
ROCW
0
YCRC_ERR
3
Luma CRC error indication.
ROCW
0
LNUM_ERR
2
Line number error indication.
ROCW
0
SAV_ERR
1
SAV error indication.
ROCW
0
EAV_ERR
0
EAV error indication.
ROCW
0
Reserved.
ROCW
0
002h
003h
004h
RSVD
15-0
EDH_DETECT
15
Embedded EDH packet detected.
R
0
ANC_UES_IN
14
Ancillary data – unknown error status flag.
R
0
ANC_IDA_IN
13
Ancillary data – internal error detected already flag.
R
0
ANC_IDH_IN
12
Ancillary data – internal error detected here flag
R
0
ANC_EDA_IN
11
Ancillary data – error detected already flag.
R
0
ANC_EDH_IN
10
Ancillary data – error detected here flag.
R
0
FF_UES_IN
9
EDH Full Field – unknown error status flag.
R
0
FF_IDA_IN
8
EDH Full Field – internal error detected already flag.
R
0
FF_IDH_IN
7
EDH Full Field – internal error detected here flag.
R
0
FF_EDA_IN
6
EDH Full Field – error detected already flag.
R
0
FF_EDH_IN
5
EDH Full Field – error detected here flag.
R
0
AP_UES_IN
4
EDH Active Picture – unknown error status flag.
R
0
AP_IDA_IN
3
EDH Active Picture – internal error detected already
flag.
R
0
AP_IDH_IN
2
EDH Active Picture – internal error detected here flag.
R
0
AP_EDA_IN
1
EDH Active Picture – error detected already flag.
R
0
AP_EDH_IN
0
EDH Active Picture – error detected here flag.
R
0
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
005h
Register Name
Bit
Description
R/W
Default
RSVD
15
Reserved.
R
0
ANC_UES
14
Ancillary data – Unknown Error Status flag.
R
1
ANC_IDA
13
Ancillary data – Internal error Detected Already flag.
R
0
ANC_IDH
12
Ancillary data – Internal error Detected Here flag.
R
0
ANC_EDA
11
Ancillary data – Error Detected Already flag.
R
0
ANC_EDH
10
Ancillary data – Error Detected Here flag.
R
0
FF_UES
9
EDH Full Field – Unknown Error Status flag.
R
1
FF_IDA
8
EDH Full Field – Internal error Detected Already flag.
R
0
FF_IDH
7
EDH Full Field – Internal error Detected Here flag.
R
0
FF_EDA
6
EDH Full Field – Error Detected Already flag.
R
0
FF_EDH
5
EDH Full Field – Error Detected Here flag.
R
0
AP_UES
4
EDH Active Picture – Unknown Error Status flag.
R
1
AP_IDA
3
EDH Active Picture – Internal error Detected Already
flag.
R
0
AP_IDH
2
EDH Active Picture – Internal error Detected Here flag.
R
0
AP_EDA
1
EDH Active Picture – Error Detected Already flag.
R
0
AP_EDH
0
EDH Active Picture – Error Detected Here flag.
R
0
FF_CRC_V
15
EDH Full Field CRC Validity bit.
R
0
AP_CRC_V
14
EDH Active Picture CRC Validity bit.
R
0
006h
007h
VD_STD
13-8
Detected Video Standard.
R
29
RSVD
7-0
Reserved.
R
255
RSVD
15-0
Reserved.
R
0
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
RSVD
15
Reserved.
R/W
Default
RW
0
RW
2
Configure STAT2 output pin:
00000 = H Blanking when 861_EN = 0; HSYNC when
861_EN = 1
00001 = V Blanking when 861_EN = 0; VSYNC when
861_EN = 1
00010 = F bit when 861_EN = 0; Data Enable (DE) when
861_EN = 1
00011 = LOCKED
00100 = Y/1ANC: ANC indication (SD), Luma ANC
indication (HD), DS1 ANC data indication (Full HD)
STAT2_CONFIG
14-10
008h
00101 = C/2ANC: Chroma ANC indication (HD) or DS2
ANC data indication (Full HD)
00110 = Data Error
00111 = Video Error
01000 = Audio Error
01001 = EDH Detected
01010 = Carrier Detect
01011 = RATE_DET0
01100 = RATE_DET1
01101 to 11111 = Reserved
STAT1_CONFIG
9-5
Configure STAT1 output pin. (Refer to above for
decoding)
RW
1
STAT0_CONFIG
4-0
Configure STAT0 output pin. (Refer to above for
decoding)
RW
0
RSVD
15
Reserved.
RW
0
STAT5_CONFIG
14-10
Configure STAT5 output pin. (Refer to above for
decoding)
RW
6
STAT4_CONFIG
9-5
Configure STAT4 output pin. (Refer to above for
decoding)
RW
4
STAT3_CONFIG
4-0
Configure STAT3 output pin. (Refer to above for
decoding)
RW
3
009h
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-4
Reserved.
RW
0
ANC_DATA_SWITCH
3
Switches between ancillary data memory banks.
RW
0
ANC_DATA_DEL
2
Remove Ancillary Data from output video stream, set
to Luma and Chroma blanking values.
RW
0
RW
0
RW
0
00Ah
HD_ANC_Y1_C2
1
HD_ANC_C2
0
Extract Ancillary data from Luma and Chroma
channels (HD inputs)
Extract Ancillary data from DS1 and DS2 (Full HD
inputs)
Extract Ancillary data only from Chroma channel (HD
inputs)
Extract Ancillary data only from DS2 (Full HD inputs)
RSVD
15-11
Reserved.
R/W
0
ANC_LINE_A
10-0
Video Line to extract Ancillary data from.
R/W
0
RSVD
15-11
Reserved.
R/W
0
ANC_LINE_B
10-0
Second video Line to extract Ancillary data from.
R/W
0
00Dh
RSVD
15-0
Reserved.
R
0
00Eh
RSVD
15-0
Reserved.
R
0
00Fh
ANC_TYPE1
15-0
Programmable DID/SDID pair #1 to extract.
R/W
0
010h
ANC_TYPE2
15-0
Programmable DID/SDID pair #2 to extract.
R/W
0
011h
ANC_TYPE3
15-0
Programmable DID/SDID pair #3 to extract.
R/W
0
012h
ANC_TYPE4
15-0
Programmable DID/SDID pair #4 to extract.
R/W
0
013h
ANC_TYPE5
15-0
Programmable DID/SDID pair #5 to extract.
R/W
0
00Bh
00Ch
014h to
01Eh
RSVD
–
Reserved.
R/W
0
RSVD
15-14
Reserved.
R
0
WORDS_PER_ACTLINE
13-0
Words Per Active Line.
R
0
RSVD
15-14
Reserved.
R
0
WORDS_PER_LINE
13-0
Total Words Per Line.
R
0
RSVD
15-11
Reserved.
R
0
LINES_PER_FRAME
10-0
Total Lines Per Frame.
R
0
01Fh
020h
021h
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
R
0
R
0
Read back detected data rate:
RATE_SEL_READBACK
15-14
0 = HD
1 & 3 =SD
2 = Full HD
Specifies detected M value
022h
M
13
0 = 1.000
1 = 1.001
023h
STD_LOCK
12
Video standard lock.
R
0
INT_PROG
11
Interlaced or progressive.
R
0
ACTLINE_PER_FIELD
10-0
Active lines per frame.
R
0
RSVD
15-2
Reserved.
R
0
V_LOCK
1
Indicates that the timing signal generator is locked to
vertical timing.
R
0
H_LOCK
0
Indicates that the timing signal generator is locked to
horizontal timing.
R
0
Reserved.
R
0
R/W
1
R/W
0
Reserved.
R
0
6
Indicates standard is not recognized for CEA 861
conversion.
R
1
FORMAT_ID_861
5-0
CEA-861 format ID of input video stream. Refer to
Table 4-20: Supported CEA-861 Formats.
R
0
RSVD
15-3
Reserved.
R
0
RSVD
AUTO/MAN
15-3
2
024h
Detect data rate automatically (1) or program
manually (0).
Programmable rate select in manual (slave) mode:
RATE_SEL_TOP
1-0
0 = HD
1 & 3 = SD
2 = Full HD
RSVD
025h
FORMAT_ERR
15-7
VSYNC_INVERT
2
Invert output VSYNC pulse.
R/W
0
HSYNC_INVERT
1
Invert output HSYNC pulse.
R/W
0
R/W
0
For 525i video input format:
When TRS_861 is set LOW (default), the DE output
will be set HIGH for 480 lines as per CEA-861.
026h
TRS_861
0
When TRS_861 is set HIGH, the DE output will be set
HIGH for 487 lines (based on ITU-R BT.656 TRS
timing).
Only valid when 861_EN is set to '1'. See
Section 4.11.1.1.
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
027h to
036h
Register Name
Bit
Description
R/W
Default
RSVD
–
Reserved.
R
0
RSVD
15-11
Reserved.
R
0
R/W
0
Error mask for global error vector:
bit[0] = EAV_ERR mask
bit[1] = SAV_ERR mask
bit[2] = LNUM_ERR mask
bit[3] = YCRC_ERR mask
037h
ERROR_MASK
10-0
bit[4] = CCRC_ERR mask
bit[5] = YCS_ERR mask
bit[6] = CCS_ERR mask
bit[7] = Reserved
bit[8] = AP_CRC_ERR mask
bit[9] = FF_CRC_ERR mask
038h
039h
RSVD
15-0
Reserved.
R
0
RSVD
15-5
Reserved.
R
0
SCLK_INV
4
Invert polarity of output serial audio clock.
R/W
0
MCLK_INV
3
Invert polarity of output audio master clock.
R/W
0
RSVD
2
Reserved.
R/W
0
R/W
0
Audio Master Clock Select.
MCLK_SEL
1-0
0 = 128 fs
1 = 256 fs
2 = 512 fs
03Ah to
06Bh
06Ch
RSVD
–
Reserved.
R
0
RSVD
15-6
Reserved.
R/W
0
Choses between the in-phase (0) and quadrature (1)
clocks for DDR mode.
R/W
0
Controls the offset for the delay line.
R/W
0
DEL_LINE_CLK_SEL
5
DEL_LINE_OFFSET
4-0
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Table 4-33: Video Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-6
Reserved.
R/W
0
R/W
2
R/W
2
R/W
3
Drive strength adjustment for DOUT[19:10] outputs
and PCLK output:
00 = 4mA
IO_DS_CTRL_DOUT_MSB
5-4
01 = 8mA
10 = 10mA(1.8V), 12mA(3.3V)
11 = 12mA(1.8V), 16mA(3.3V)
Drive strength adjustment for STAT[5:0] outputs:
06Dh
00 = 4mA
IO_DS_CTRL_STAT
3-2
01 = 6mA
10 = 8mA(1.8V), 10mA(3.3V)
11 = 10mA(1.8V), 12mA(3.3V)
Drive strength adjustment for DOUT[9:0] outputs:
00 = 4mA
IO_DS_CTRL_DOUT_LSB
1-0
01 = 6mA
10 = 8mA(1.8V), 10mA(3.3V)
11 = 10mA(1.8V), 12mA(3.3V)
06Eh to
072h
073h
074h to
085h
RSVD
–
Reserved.
R/W
0
RSVD
15-10
Reserved.
R/W
0
R/W
0
EQ_BYPASS
9
0 = EQ enabled
1 = bypass EQ
RSVD
8-0
Reserved.
R/W
0
RSVD
–
Reserved.
R/W
0
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4.19.2 SD Audio Core
Note: The GV7601 only accepts write/read commands to/from the SD Audio Register
Map when the audio de-embedder is locked to the incoming SD video format.
Table 4-34: SD Audio Core Configuration and Status Registers
Address
Register Name
RSVD
Bit
15-14
Description
R/W
Default
Reserved.
R/W
0
R/W
0
R/W
0
Extract Audio Channel Status from second channel
pair.
R/W
0
Reserved.
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Selects deletion of all audio data and all audio control
packets.
ALL_DEL
13
0 = Do not delete existing audio packets
1 = Delete existing audio packets
Mute all output channels.
MUTE_ALL
12
0 = Normal
1 = Muted
ACS_USE_SECOND
RSVD
11
10-8
Causes the channel 7 and 8 output format to use LSB
first.
LSB_FIRSTD
7
0 = MSB first
1 = LSB first
400h
Causes the channel 5 and 6 output format to use LSB
first.
LSB_FIRSTC
6
0 = MSB first
1 = LSB first
Causes the channel 3 and 4 output format to use LSB
first.
LSB_FIRSTB
5
0 = MSB first
1 = LSB first
Causes the channel 1 and 2 output format to use LSB
first.
LSB_FIRSTA
4
0 = MSB first
1 = LSB first
Specifies the Secondary audio group to extract.
00 = Audio group #1
01 = Audio group #2
IDB
3-2
10 = Audio group #3
11 = Audio group #4
Note: Should IDA and IDB be set to the same value,
they automatically revert to their default values.
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
R/W
0
Specifies the Primary audio group to extract.
00 = Audio group #1
01 = Audio group #2
400h
IDA
1-0
10 = Audio group #3
11 = Audio group #4
Note: Should IDA and IDB be set to the same value,
they automatically revert to their default values.
EXT_DET3_4B
15
Set when Secondary group channels 3 and 4 have
extended data. Cleared on write.
ROCW
0
EXT_DET1_2B
14
Set when Secondary group channels 1 and 2 have
extended data. Cleared on write.
ROCW
0
EXT_DET3_4A
13
Set when Primary group channels 3 and 4 have
extended data. Cleared on write.
ROCW
0
EXT_DET1_2A
12
Set when Primary group channels 1 and 2 have
extended data. Cleared on write.
ROCW
0
CTL_DBNB_ERR
11
Set when Secondary group control packet Data Block
Number sequence is discontinuous. Cleared on write.
ROCW
0
CTL_DBNA_ERR
10
Set when Primary group control packet Data Block
Number sequence is discontinuous. Cleared on write.
ROCW
0
EXT_DBNB_ERR
9
Set when Secondary group extended data packet Data
Block Number sequence is discontinuous. Cleared on
write.
ROCW
0
EXT_DBNA_ERR
8
Set when Primary group extended data packet Data
Block Number sequence is discontinuous. Cleared on
write.
ROCW
0
SAMP_DBNB_ERR
7
Set when Secondary group data packet Data Block
Number sequence is discontinuous. Cleared on write.
ROCW
0
SAMP_DBNA_ERR
6
Set when Primary group data packet Data Block
Number sequence is discontinuous. Cleared on write.
ROCW
0
CTRB_DET
5
Set when Secondary group audio control packet is
detected. Cleared on write.
ROCW
0
CTRA_DET
4
Set when Primary group audio control packet is
detected. Cleared on write.
ROCW
0
ACS_DET3_4B
3
Secondary group audio status detected for channels 3
and 4. Cleared on write.
ROCW
0
ACS_DET1_2B
2
Secondary group audio status detected for channels 1
and 2. Cleared on write.
ROCW
0
ACS_DET3_4A
1
Primary group audio status detected for channels 3
and 4. Cleared on write.
ROCW
0
ACS_DET1_2A
0
Primary group audio status detected for channels 1
and 2. Cleared on write.
ROCW
0
401h
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-2
Reserved.
R/W
0
Cause channel status data in ACSR[183:0] to be
transferred to the channel status replacement
mechanism. The transfer does not occur until the next
status boundary.
R/W
0
R/W
0
ACS_APPLY
1
402h
Specifies that Audio Channel Status of all channels
should be replaced with ACSR[183:0] field.
ACS_REGEN
0
0 = Do not replace Channel Status
1 = Replace Channel Status of all channels
IDB_READBACK
15-14
Actual value of IDB in the hardware.
R
1
IDA_READBACK
13-12
Actual value of IDA in the hardware.
R
0
XDPG4_DET
11
Set while embedded Group 4 audio extended packets
are detected.
R
0
XDPG3_DET
10
Set while embedded Group 3 audio extended packets
are detected.
R
0
XDPG2_DET
9
Set while embedded Group 2 audio extended packets
are detected.
R
0
XDPG1_DET
8
Set while embedded Group 1 audio extended packets
are detected.
R
0
ADPG4_DET
7
Set while Group 4 audio data packets are detected.
R
0
ADPG3_DET
6
Set while Group 3 audio data packets are detected.
R
0
ADPG2_DET
5
Set while Group 2 audio data packets are detected.
R
0
ADPG1_DET
4
Set while Group 1 audio data packets are detected.
R
0
ACS_APPLY_WAITD
3
Set while output channels 7 and 8 are waiting for a
status boundary to apply the ACSR[183:0] data.
R
0
ACS_APPLY_WAITC
2
Set while output channels 5 and 6 are waiting for a
status boundary to apply the ACSR[183:0] data.
R
0
ACS_APPLY_WAITB
1
Set while output channels 3 and 4 are waiting for a
status boundary to apply the ACSR[183:0] data.
R
0
ACS_APPLY_WAITA
0
Set while output channels 1 and 2 are waiting for a
status boundary to apply the ACSR[183:0] data.
R
0
R/W
0
ROCW
0
R/W
0
R/W
0
403h
RSVD
15-1
404h
CSUM_ERROR
RSVD
0
15-8
Reserved.
Embedded packet checksum error detected. Cleared
on write.
Reserved.
Mute output channels 8..1 Where bits 7:0 = channel 8:1
405h
MUTE
7-0
1 = Mute
0 = Normal
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
406h
Register Name
Bit
Description
R/W
Default
RSVD
15-8
Reserved.
R/W
0
CH4_VALIDB
7
Secondary group channel 4 sample validity flag.
R
0
CH3_VALIDB
6
Secondary group channel 3 sample validity flag.
R
0
CH2_VALIDB
5
Secondary group channel 2 sample validity flag.
R
0
CH1_VALIDB
4
Secondary group channel 1 sample validity flag.
R
0
CH4_VALIDA
3
Primary group channel 4 sample validity flag.
R
0
CH3_VALIDA
2
Primary group channel 3 sample validity flag.
R
0
CH2_VALIDA
1
Primary group channel 2 sample validity flag.
R
0
CH1_VALIDA
0
Primary group channel 1 sample validity flag.
R
0
RSVD
15
Reserved.
R/W
0
EN_NOT_LOCKED
14
Asserts interrupt when LOCKED signal is not asserted.
R/W
0
EN_NO_VIDEO
13
Asserts interrupt when video format is unknown.
R/W
0
EN_CSUM_ERROR
12
Asserts interrupt when checksum error is detected.
R/W
0
EN_ACS_DET3_4B
11
Asserts interrupt when EN_ACS_DET3_4B flag is set.
R/W
0
EN_ACS_DET1_2B
10
Asserts interrupt when EN_ACS_DET1_2B flag is set.
R/W
0
EN_ACS_DET3_4A
9
Asserts interrupt when EN_ACS_DET3_4A flag is set.
R/W
0
EN_ACS_DET1_2A
8
Asserts interrupt when EN_ACS_DET1_2A flag is set.
R/W
0
EN_CTRB_DET
7
Asserts interrupt when EN_CTRB_DET flag is set.
R/W
0
EN_CTRA_DET
6
Asserts interrupt when EN_CTRA_DET flag is set.
R/W
0
EN_DBNB_ERR
5
Asserts interrupt when EN_DBNB_ERR flag is set.
R/W
0
EN_DBNA_ERR
4
Asserts interrupt when EN_DBNA_ERR flag is set.
R/W
0
EN_ADPG4_DET
3
Asserts interrupt when the ADPG4_DET flag is set.
R/W
0
EN_ADPG3_DET
2
Asserts interrupt when the ADPG3_DET flag is set.
R/W
0
EN_ADPG2_DET
1
Asserts interrupt when the ADPG2_DET flag is set.
R/W
0
EN_ADPG1_DET
0
Asserts interrupt when the ADPG1_DET flag is set.
R/W
0
407h
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
R/W
3
Output channels 7 and 8 word length.
00 = 24-bit
ASWLD
15-14
01 = 20-bit
10 = 16-bit
11 = Automatic 20-bit or 24-bit
ASWLC
13-12
Output channels 5 and 6 word length. (See above for
decoding)
R/W
3
ASWLB
11-10
Output channels 3 and 4 word length. (See above for
decoding)
R/W
3
ASWLA
9-8
Output channels 1 and 2 word length. (See above for
decoding)
R/W
3
R/W
3
408h
Output channels 7 and 8 format selector.
00 = AES/EBU or S/PDIF audio output
AMD
7-6
01 = Serial audio output: Left justified; MSB first
10 = Serial audio output: Right justified; MSB first
11 = I2S serial audio output
AMC
5-4
Output channels 5 and 6 format selector. (See above
for decoding).
R/W
3
AMB
3-2
Output channels 3 and 4 format selector. (See above
for decoding).
R/W
3
AMA
1-0
Output channels 1 and 2 format selector. (See above
for decoding).
R/W
3
RSVD
15-12
Reserved.
R/W
0
R/W
3
Output channel 4 source selector.
000 = Primary audio group channel 1
001 = Primary audio group channel 2
010 = Primary audio group channel 3
OP4_SRC
11-9
011 = Primary audio group channel 4
100 = Secondary audio group channel 1
409h
101 = Secondary audio group channel 2
110 = Secondary audio group channel 3
111 = Secondary audio group channel 4
OP3_SRC
8-6
Output channel 3 source selector (Decode as above).
R/W
2
OP2_SRC
5-3
Output channel 2 source selector (Decode as above).
R/W
1
OP1_SRC
2-0
Output channel 1 source selector (Decode as above).
R/W
0
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
RSVD
Bit
15-12
Description
R/W
Default
Reserved.
R/W
0
R/W
7
Output channel 8 source selector.
000 = Primary audio group channel 1
001 = Primary audio group channel 2
010 = Primary audio group channel 3
OP8_SRC
11-9
011 = Primary audio group channel 4
100 = Secondary audio group channel 1
40Ah
101 = Secondary audio group channel 2
110 = Secondary audio group channel 3
110 = Secondary audio group channel 4
40Bh to
41Fh
OP7_SRC
8-6
Output channel 7 source selector (Decode as above).
R/W
6
OP6_SRC
5-3
Output channel 6 source selector (Decode as above).
R/W
5
OP5_SRC
2-0
Output channel 5 source selector (Decode as above).
R/W
4
RSVD
–
Reserved.
−
−
RSVD
15-9
Reserved.
R/W
0
AFN1_2A
8-0
Primary group audio frame number for channels 1 and
2.
R
0
RSVD
15-9
Reserved.
R/W
0
AFN3_4A
8-0
Primary group audio frame number for channels 3 and
4.
R
0
RSVD
15-8
Reserved.
R/W
0
RATE3_4A
7-5
Primary group sampling frequency for channels 3 and
4
R
0
ASX3_4A
4
Primary group asynchronous mode for channels 3 and
4.
R
0
RATE1_2A
3-1
Primary group sampling frequency for channels 1 and
2.
R
0
ASX1_2A
0
Primary group asynchronous mode for channels 1 and
2.
R
0
R/W
0
R
0
R/W
0
420h
421h
422h
RSVD
15-4
Reserved.
ACTA
3-0
Primary group active channels.
RSVD
15-9
Reserved.
DEL1A_1
8-1
Primary Audio group delay data for channel 1.
R
0
Primary Audio group delay data valid flag for channel
1.
R
0
423h
424h
EBIT1A
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-9
Reserved.
R/W
0
DEL1A_2
8-0
Primary Audio group delay data for channel 1.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL1A_3
8-0
Primary Audio group delay data for channel 1.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL2A_4
8-1
Primary Audio group delay data for channel 2.
R
0
Primary Audio group delay data valid flag for channel
2.
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
425h
426h
427h
EBIT2A
0
RSVD
15-9
Reserved.
DEL2A_5
8-0
Primary Audio group delay data for channel 2.
RSVD
15-9
Reserved.
DEL2A_6
8-0
Primary Audio group delay data for channel 2.
RSVD
15-9
Reserved.
DEL3A_7
8-1
Primary Audio group delay data for channel 3.
R
0
Primary Audio group delay data valid flag for channel
3.
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
428h
429h
42Ah
EBIT3A
0
RSVD
15-9
Reserved.
DEL3A_8
8-0
Primary Audio group delay data for channel 3.
RSVD
15-9
Reserved.
DEL3A_9
8-0
Primary Audio group delay data for channel 3.
RSVD
15-9
Reserved.
DEL4A_10
8-1
Primary Audio group delay data for channel 4.
R
0
Primary Audio group delay data valid flag for channel
4.
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
42Bh
42Ch
42Dh
EBIT4A
0
RSVD
15-9
Reserved.
DEL4A_11
8-0
Primary Audio group delay data for channel 4.
RSVD
15-9
Reserved.
DEL4A_12
8-0
Primary Audio group delay data for channel 4.
RSVD
15-9
Reserved.
AFN1_2B
8-0
Secondary group audio frame number for channels 1
and 2.
RSVD
15-9
Reserved.
AFN3_4B
8-0
Secondary group audio frame number for channels 3
and 4.
42Eh
42Fh
430h
431h
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
432h
Register Name
Bit
Description
R/W
Default
RSVD
15-8
Reserved.
R
0
RATE3_4B
7-5
Secondary group sampling frequency for channels 3
and 4.
R
0
ASX3_4B
4
Secondary group asynchronous mode for channels 3
and 4.
R
0
RATE1_2B
3-1
Secondary group sampling frequency for channels 1
and 2.
R
0
ASX1_2B
0
Secondary group asynchronous mode for channels 1
and 2.
R
0
R/W
0
R
0
R/W
0
RSVD
15-4
Reserved.
ACTB
3-0
Secondary group active channels.
RSVD
15-9
Reserved.
DEL1B_1
8-1
Secondary Audio group delay data for channel 1.
R
0
EBIT1B
0
Secondary Audio group delay data valid flag for
channel 1.
R
0
RSVD
15-9
Reserved.
DEL1B_2
8-0
Secondary Audio group delay data for channel 1.
RSVD
15-9
Reserved.
DEL1B_3
8-0
Secondary Audio group delay data for channel 1.
RSVD
15-9
Reserved.
DEL2B_4
8-1
EBIT2B
0
RSVD
15-9
Reserved.
DEL2B_5
8-0
Secondary Audio group delay data for channel 2.
RSVD
15-9
Reserved.
DEL2B_6
8-0
Secondary Audio group delay data for channel 2.
RSVD
15-9
Reserved.
DEL3B_7
8-1
EBIT3B
0
RSVD
15-9
Reserved.
DEL3B_8
8-0
Secondary Audio group delay data for channel 3.
433h
434h
R/W
435h
R
0
R/W
0
R
0
R/W
0
Secondary Audio group delay data for channel 2.
R
0
Secondary Audio group delay data valid flag for
channel 2.
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
Secondary Audio group delay data for channel 3.
R
0
Secondary Audio group delay data valid flag for
channel 3.
R
0
R/W
0
R
0
436h
437h
438h
439h
43Ah
43Bh
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-9
Reserved.
R/W
0
DEL3B_9
8-0
Secondary Audio group delay data for channel 3.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL4B_10
8-1
Secondary Audio group delay data for channel 4.
R
0
EBIT4B
0
Secondary Audio group delay data valid flag for
channel 4.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL4B_11
8-0
Secondary Audio group delay data for channel 4.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL4B_12
8-0
Secondary Audio group delay data for channel 4.
R
0
440h
ACSR1_2A_0
15-0
Bytes 0 and 1 of audio group A channel status for
channels 1 and 2.
R
0
441h
ACSR1_2A_2
15-0
Bytes 2 and 3 of audio group A channel status for
channels 1 and 2.
R
0
442h
ACSR1_2A_4
15-0
Bytes 4 and 5 of audio group A channel status for
channels 1 and 2.
R
0
443h
ACSR1_2A_6
15-0
Bytes 6 and 7 of audio group A channel status for
channels 1 and 2.
R
0
444h
ACSR1_2A_8
15-0
Bytes 8 and 9 of audio group A channel status for
channels 1 and 2.
R
0
445H
ACSR1_2A_10
15-0
Bytes 10 and 11 of audio group A channel status for
channels 1 and 2.
R
0
446H
ACSR1_2A_12
15-0
Bytes 12 and 13 of audio group A channel status for
channels 1 and 2.
R
0
447h
ACSR1_2A_14
15-0
Bytes 14 and 15 of audio group A channel status for
channels 1 and 2.
R
0
448h
ACSR1_2A_16
15-0
Bytes 16 and 17 of audio group A channel status for
channels 1 and 2.
R
0
449h
ACSR1_2A_18
15-0
Bytes 18 and 19 of audio group A channel status for
channels 1 and 2.
R
0
44Ah
ACSR1_2A_20
15-0
Bytes 20 and 21 of audio group A channel status for
channels 1 and 2.
R
0
44Bh
ACSR1_2A_22
15-0
Bytes 22 of audio group A channel status for channels
1 and 2.
R
0
450h
ACSR3_4A_0
15-0
Bytes 0 and 1 of audio group A channel status for
channels 3 and 4.
R
0
451h
ACSR3_4A_2
15-0
Bytes 2 and 3 of audio group A channel status for
channels 3 and 4.
R
0
43Ch
43Dh
43Eh
43Fh
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
452h
ACSR3_4A_4
15-0
Bytes 4 and 5 of audio group A channel status for
channels 3 and 4.
R
0
453h
ACSR3_4A_6
15-0
Bytes 6 and 7 of audio group A channel status for
channels 3 and 4.
R
0
454h
ACSR3_4A_8
15-0
Bytes 8 and 9 of audio group A channel status for
channels 3 and 4.
R
0
455h
ACSR3_4A_10
15-0
Bytes 10 and 11 of audio group A channel status for
channels 3 and 4.
R
0
456h
ACSR3_4A_12
15-0
Bytes 12 and 13 of audio group A channel status for
channels 3 and 4.
R
0
457h
ACSR3_4A_14
15-0
Bytes 14 and 15 of audio group A channel status for
channels 3 and 4.
R
0
458h
ACSR3_4A_16
15-0
Bytes 16 and 17 of audio group A channel status for
channels 3 and 4.
R
0
459h
ACSR3_4A_18
15-0
Bytes 18 and 19 of audio group A channel status for
channels 3 and 4.
R
0
45Ah
ACSR3_4A_20
15-0
Bytes 20 and 21 of audio group A channel status for
channels 3 and 4.
R
0
RSVD
15-8
Reserved.
R/W
0
ACSR3_4A_22
7-0
Bytes 22 of audio group A channel status for channels
3 and 4.
R
0
460h
ACSR1_2B_0
15-0
Bytes 0 and 1 of audio group B channel status for
channels 1 and 2.
R
0
461h
ACSR1_2B_2
15-0
Bytes 2 and 3 of audio group B channel status for
channels 1 and 2.
R
0
462h
ACSR1_2B_4
15-0
Bytes 4 and 5 of audio group B channel status for
channels 1 and 2.
R
0
463h
ACSR1_2B_6
15-0
Bytes 6 and 7 of audio group B channel status for
channels 1 and 2.
R
0
464h
ACSR1_2B_8
15-0
Bytes 8 and 9 of audio group B channel status for
channels 1 and 2.
R
0
465h
ACSR1_2B_10
15-0
Bytes 10 and 11 of audio group B channel status for
channels 1 and 2.
R
0
466h
ACSR1_2B_12
15-0
Bytes 12 and 13 of audio group B channel status for
channels 1 and 2.
R
0
467h
ACSR1_2B_14
15-0
Bytes 14 and 15 of audio group B channel status for
channels 1 and 2.
R
0
468h
ACSR1_2B_16
15-0
Bytes 16 and 17 of audio group B channel status for
channels 1 and 2.
R
0
45Bh
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
469h
ACSR1_2B_18
15-0
Bytes 18 and 19 of audio group B channel status for
channels 1 and 2.
R
0
46Ah
ACSR1_2B_20
15-0
Bytes 20 and 21 of audio group B channel status for
channels 1 and 2.
R
0
RSVD
15-8
Reserved.
R/W
0
ACSR1_2B_22
7-0
Bytes 22 of audio group B channel status for channels
1 and 2.
R
0
470h
ACSR3_4B_0
15-0
Bytes 0 and 1 of audio group B channel status for
channels 3 and 4.
R
0
471h
ACSR3_4B_2
15-0
Bytes 2 and 3 of audio group B channel status for
channels 3 and 4.
R
0
472h
ACSR3_4B_4
15-0
Bytes 4 and 5 of audio group B channel status for
channels 3 and 4.
R
0
473h
ACSR3_4B_6
15-0
Bytes 6 and 7 of audio group B channel status for
channels 3 and 4.
R
0
474h
ACSR3_4B_8
15-0
Bytes 8 and 9 of audio group B channel status for
channels 3 and 4.
R
0
475h
ACSR3_4B_10
15-0
Bytes 10 and 11 of audio group B channel status for
channels 3 and 4.
R
0
476h
ACSR3_4B_12
15-0
Bytes 12 and 13 of audio group B channel status for
channels 3 and 4.
R
0
477h
ACSR3_4B_14
15-0
Bytes 14 and 15 of audio group B channel status for
channels 3 and 4.
R
0
478h
ACSR3_4B_16
15-0
Bytes 16 and 17 of audio group B channel status for
channels 3 and 4.
R
0
479h
ACSR3_4B_18
15-0
Bytes 18 and 19 of audio group B channel status for
channels 3 and 4.
R
0
47Ah
ACSR3_4B_20
15-0
Bytes 20 and 21 of audio group B channel status for
channels 3 and 4.
R
0
47Bh
ACSR3_4B_22
15-0
Bytes 22 of audio group B channel status for channels
3 and 4.
R
0
480h
ACSR_BYTE0
7-0
Audio channel status to use when ACS_REGEN is set or
when adding audio channel status to non-AES/EBU
audio. 8 bits per register for 23 registers.
R
0
481h
ACSR_BYTE1
7-0
–
W
0
482h
ACSR_BYTE2
7-0
–
W
0
483h
ACSR_BYTE3
7-0
–
W
0
484h
ACSR_BYTE4
7-0
–
W
0
485h
ACSR_BYTE5
7-0
–
W
0
46Bh
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Table 4-34: SD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
486h
ACSR_BYTE6
7-0
–
W
0
487h
ACSR_BYTE7
7-0
–
W
0
488h
ACSR_BYTE8
7-0
–
W
0
489h
ACSR_BYTE9
7-0
–
W
0
48Ah
ACSR_BYTE10
7-0
–
W
0
48Bh
ACSR_BYTE11
7-0
–
W
0
48Ch
ACSR_BYTE12
7-0
–
W
0
48Dh
ACSR_BYTE13
7-0
–
W
0
48Eh
ACSR_BYTE14
7-0
–
W
0
48Fh
ACSR_BYTE15
7-0
–
W
0
490h
ACSR_BYTE16
7-0
–
W
0
491h
ACSR_BYTE17
7-0
–
W
0
492h
ACSR_BYTE18
7-0
–
W
0
493h
ACSR_BYTE19
7-0
–
W
0
494h
ACSR_BYTE20
7-0
–
W
0
495h
ACSR_BYTE21
7-0
–
W
0
496h
ACSR_BYTE22
7-0
–
W
0
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4.19.3 HD Audio Core Registers
Note: The GV7601 only accepts write/read commands to/from the HD Audio Register
Map when the device is locked to the incoming HD video format.
Table 4-35: HD Audio Core Configuration and Status Registers
Address
Register Name
Bit
Description
R/W
Default
ECC_OFF
15
Disables ECC error correction.
R/W
0
R/W
0
R/W
0
R/W
0
R/W
3
R/W
3
R/W
3
R/W
3
Selects deletion of all audio data and all audio
control packets
ALL_DEL
14
0 = Do not delete existing audio control packets
1 = Delete existing audio control packets.
Mute all output channels
MUTE_ALL
13
0 = Normal
1 = Muted
ACS_USE_SECOND
12
Extract Audio Channel Status from second channel
pair.
Secondary group output word length.
00 = 24 bits
ASWLB
11-10
01 = 20 bits
10 = 16 bits
11 = invalid
200h
Primary group output word length
00 = 24 bits
ASWLA
9-8
01 = 20 bits
10 = 16 bits
11 = invalid
Secondary group output format selector.
00 = AES/EBU or S/PDIF audio output
AMB
7-6
01 = Serial audio output: left justified MSB first
10 = Serial audio output: right justified. MSB first
11 = I2S serial audio output
Primary group output format selector.
00 = AES/EBU or S/PDIF audio output
AMA
5-4
01 = Serial audio output: left justified MSB first
10 = Serial audio output: right justified MSB first
11 = I2S serial audio output
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Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
R/W
1
R/W
0
R/W
0
Specifies the Secondary audio group to extract.
00 = Audio group #1
01 = Audio group #2
IDB
3-2
10 = Audio group #3
11 = Audio group #4
Note: Should IDA and IDB be set to the same value,
they automatically revert to their default values.
200h
Specifies the Primary audio group to extract.
00 = Audio group #1
01 = Audio group #2
IDA
1-0
10 = Audio group #3
11 = Audio group #4
Note: Should IDA and IDB be set to the same value,
they automatically revert to their default values.
RSVD
201h
15-8
Reserved.
DBNB_ERR
7
Set when Secondary group audio Data Block
Number sequence is discontinuous.
ROCW
0
DBNA_ERR
6
Set when Primary group audio Data Block Number
sequence is discontinuous.
ROCW
0
CTRB_DET
5
Set when Secondary group audio control packet is
detected.
ROCW
0
CTRA_DET
4
Set when Primary group audio control packet is
detected.
ROCW
0
ACS_DET3_4B
3
Secondary group audio status detected for channels
3 and 4.
ROCW
0
ACS_DET1_2B
2
Secondary group audio status detected for channels
1 and 2.
ROCW
0
ACS_DET3_4A
1
Primary group audio status detected for channels 3
and 4.
ROCW
0
ACS_DET1_2A
0
Primary group audio status detected for channels 1
and 2.
ROCW
0
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Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
202h
Register Name
Bit
Description
RSVD
15-9
IDB_READBACK
IDA_READBACK
Default
Reserved.
R
0
8-7
Actual value of IDB in the hardware.
R
1
6-5
Actual value of IDA in the hardware.
R
0
ADPG4_DET
4
Set while Group 4 audio data packets are detected.
R
0
ADPG3_DET
3
Set while Group 3 audio data packets are detected.
R
0
ADPG2_DET
2
Set while Group 2 audio data packets are detected.
R
0
ADPG1_DET
1
Set while Group 1 audio data packets are detected.
R
0
ACS_APPLY_WAIT
0
Set while output channels 1 and 2 are waiting for a
status boundary to apply the ACSR[183:0] data.
R
0
R/W
0
RSVD
203h
R/W
15-2
Reserved.
ECCA_ERROR
1
Primary group audio data packet error detected.
ROCW
0
ECCB_ERROR
0
Secondary group audio data packet error detected.
ROCW
0
Reserved.
R/W
0
Cause channel status data in ACSR[183:0] to be
transferred to the channel status replacement
mechanism. The transfer does not occur until the
next status boundary.
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RSVD
ACS_APPLY
15-2
1
204h
Specifies that Audio Channel Status of all channels
should be replaced with ACSR[183:0] field.
ACS_REGEN
0
0 = Do not replace Channel Status
1 = Replace Channel Status of all channels
RSVD
15
Reserved.
Mute Secondary output channels 4-1 where
bits 7:4 = channel 4:1
MUTEB
7-4
1 = Mute
0 = Normal
205h
Mute Primary output channels 4-1 where
bits 3:0 = channel 4:1
MUTEA
3-0
1 = Mute
0 = Normal
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Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
206h
207h
Register Name
Bit
Description
R/W
Default
RSVD
15-8
Reserved.
R/W
0
CH4_VALIDB
7
Secondary group channel 4 sample validity flag.
R
0
CH3_VALIDB
6
Secondary group channel 3 sample validity flag.
R
0
CH2_VALIDB
5
Secondary group channel 2 sample validity flag.
R
0
CH1_VALIDB
4
Secondary group channel 1 sample validity flag.
R
0
CH4_VALIDA
3
Primary group channel 4 sample validity flag.
R
0
CH3_VALIDA
2
Primary group channel 3 sample validity flag.
R
0
CH2_VALIDA
1
Primary group channel 2 sample validity flag.
R
0
CH1_VALIDA
0
Primary group channel 1 sample validity flag.
R
0
RSVD
15
Reserved.
R/W
0
EN_MISSING_PHASE
14
Asserts interrupt when chosen group's phase data is
missing
R/W
0
EN_ACS_DET3_4B
13
Asserts interrupt when ACS_DET3_4B flag is set.
R/W
0
EN_ACS_DET1_2B
12
Asserts interrupt when ACS_DET1_2B flag is set.
R/W
0
EN_ACS_DET3_4A
11
Asserts interrupt when ACS_DET3_4A flag is set.
R/W
0
EN_ACS_DET1_2A
10
Asserts interrupt when ACS_DET1_2A flag is set.
R/W
0
EN_CTRB_DET
9
Asserts interrupt when CTRB_DET flag is set.
R/W
0
EN_CTRA_DET
8
Asserts interrupt when CTRA_DET flag is set.
R/W
0
EN_DBNB_ERR
7
Asserts interrupt when DBNB_ERR flag is set.
R/W
0
EN_DBNA_ERR
6
Asserts interrupt when DBNA_ERR flag is set.
R/W
0
EN_ECCB_ERR
5
Asserts interrupt when ECCB_ERR flag is set.
R/W
0
EN_ECCA_ERR
4
Asserts interrupt when ECCA_ERR flag is set.
R/W
0
EN_ADPG4_DET
3
Asserts interrupt when ADPG4_DET flag is set.
R/W
0
EN_ADPG3_DET
2
Asserts interrupt when ADPG3_DET flag is set.
R/W
0
EN_ADPG2_DET
1
Asserts interrupt when ADPG2_DET flag is set.
R/W
0
EN_ADPG1_DET
0
Asserts interrupt when ADPG1_DET flag is set.
R/W
0
GV7601
Final Data Sheet
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Rev.7
April 2014
128 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
RSVD
208h
Bit
15-11
Description
R/W
Default
Reserved.
R/W
0
SEL_PHASE_SRC
10
Selects between the Primary and Secondary
embedded phase info.
R/W
0
LSB_FIRSTB
9
Causes the Secondary group serial output formats to
use LSB first.
R/W
0
LSB_FIRSTA
8
Causes the Primary group serial output formats to
use LSB first.
R/W
0
Reserved.
R/W
0
RSVD
7-4
EN_NOT_LOCKED
3
Asserts interrupt when locked is not asserted.
R/W
0
EN_NO_VIDEO
2
Asserts interrupt when the video format is unknown.
R/W
0
EN_NO_PHASEB
1
Asserts interrupt when NO_PHASEB_DATA is set.
R/W
0
EN_NO_PHASEA
0
Asserts interrupt when NO_PHASEA_DATA is set.
R/W
0
Reserved.
R/W
0
RSVD
15-3
MISSING_PHASE
2
Embedded phase info for chosen group missing or
incorrect.
R
0
NO_PHASEB_DATA
1
Secondary group has invalid embedded clock
information.
R
0
NO_PHASEA_DATA
0
Primary group has invalid embedded clock
information.
R
0
Reserved.
R
0
R/W
3
209h
RSVD
15-12
Output channel 4 source selector.
000: Primary audio group channel 1
001: Primary audio group channel 2
010: Primary audio group channel 3
011: Primary audio group channel 4
100: Secondary audio group channel 1
101: Secondary audio group channel 2
110: Secondary audio group channel 3
111: Secondary audio group channel 4
OP4_SRC
11-9
OP3_SRC
8-6
Output channel 3 source selector (Decode as above).
R/W
2
OP2_SRC
5-3
Output channel 2 source selector (Decode as above).
R/W
1
OP1_SRC
2-0
Output channel 1 source selector (Decode as above).
R/W
0
20Ah
GV7601
Final Data Sheet
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Rev.7
April 2014
129 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
RSVD
Bit
15-12
Description
R/W
Default
Reserved.
R/W
0
R/W
7
Output channel 8 source selector.
OP8_SRC
11-9
OP7_SRC
8-6
Output channel 7 source selector (Decode as above).
R/W
6
OP6_SRC
5-3
Output channel 6 source selector (Decode as above).
R/W
5
OP5_SRC
2-0
Output channel 5 source selector (Decode as above).
R/W
4
20Bh
20Ch to
21Fh
000: Primary audio group channel 1
001: Primary audio group channel 2
010: Primary audio group channel 3
011: Primary audio group channel 4
100: Secondary audio group channel 1
101: Secondary audio group channel 2
110: Secondary audio group channel 3
111: Secondary audio group channel 4
RSVD
–
Reserved.
−
−
RSVD
15-9
Reserved.
R/W
0
AFNA
8-0
Primary group audio frame number.
R
0
RSVD
15-4
Reserved.
R/W
0
RATEA
3-1
Primary group sampling frequency for channels 1
and 2.
R
0
ASXA
0
Primary group asynchronous mode for channels 1
and 2.
R
0
RSVD
15-4
Reserved.
R/W
0
ACTA
3-0
Primary group active channels.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL1_2A_1
8-1
Primary Audio group delay data for channels 1 and 2
[7:0].
R
0
Primary Audio group delay data valid flag for
channels 1 and 2.
R
0
R/W
0
R
0
R/W
0
R
0
220h
221h
222h
223h
EBIT1_2A
0
RSVD
15-9
Reserved.
DEL1_2A_2
8-0
Primary Audio group delay data for channels 1 and 2
[16:8].
RSVD
15-9
Reserved.
DEL1_2A_3
8-0
Primary Audio group delay data for channels 1 and 2
[25:17].
224h
225h
GV7601
Final Data Sheet
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Rev.7
April 2014
130 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
226h
Register Name
Bit
Description
R/W
Default
RSVD
15-9
Reserved.
R/W
0
DEL3_4A_4
8-1
Primary Audio group delay data for channels 3 and 4
[7:0].
R
0
Primary Audio group delay data valid flag for
channels 3 and 4.
R
0
R/W
0
R
0
R/W
0
R
0
EBIT3_4A
0
RSVD
15-9
Reserved.
DEL3_4A_5
8-0
Primary Audio group delay data for channels 3 and 4
[16:8].
RSVD
15-9
Reserved.
DEL3_4A_6
8-0
Primary Audio group delay data for channels 3 and 4
[25:17].
227h
228h
229h to
22Fh
RSVD
–
Reserved.
R/W
0
RSVD
15-9
Reserved.
R/W
0
AFNB
8-0
Secondary group audio frame number.
R
0
RSVD
15-4
Reserved.
R/W
0
RATEB
3-1
Secondary group sampling frequency for channels 1
and 2.
R
0
ASXB
0
Secondary group asynchronous mode for channels 1
and 2.
R
0
RSVD
15-4
Reserved.
R/W
0
ACTB
3-0
Secondary group active channels.
R
0
RSVD
15-9
Reserved.
R/W
0
DEL1_2B_1
8-1
Secondary Audio group delay data valid flag for
channels 1 and 2.
R
0
Secondary Audio group delay data for channels 1
and 2 [7:0].
R
0
R/W
0
R
0
R/W
0
R
0
230h
231h
232h
233h
EBIT1_2B
0
RSVD
15-9
Reserved.
DEL1_2B_2
8-0
Secondary Audio group delay data for channels 1
and 2 [16:8].
RSVD
15-9
Reserved.
DEL1_2B_3
8-0
Secondary Audio group delay data for channels 1
and 2 [25:17].
234h
235h
GV7601
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Rev.7
April 2014
131 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
236h
Register Name
Bit
Description
R/W
Default
RSVD
15-9
Reserved.
R/W
0
DEL3_4B_4
8-1
Secondary Audio group delay data for channels 3
and 4 [7:0].
R
0
Secondary Audio group delay data valid flag for
channels 3 and 4.
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
EBIT3_4B
0
RSVD
15-9
Reserved.
DEL3_4B_5
8-0
Secondary Audio group delay data for channels 3
and 4 [16:8].
RSVD
15-9
Reserved.
DEL3_4B_6
8-0
Secondary Audio group delay data for channels 3
and 4 [25:17].
237h
238h
239h to
23Fh
RSVD
–
Reserved.
240h
ACSR1_2A_0
15-0
Bytes 0 and 1 of audio group A channel status for
channels 1 and 2.
R
0
241h
ACSR1_2A_2
15-0
Bytes 2 and 3 of audio group A channel status for
channels 1 and 2.
R
0
242h
ACSR1_2A_4
15-0
Bytes 4 and 5 of audio group A channel status for
channels 1 and 2.
R
0
243h
ACSR1_2A_6
15-0
Bytes 6 and 7 of audio group A channel status for
channels 1 and 2.
R
0
244h
ACSR1_2A_8
15-0
Bytes 8 and 9 of audio group A channel status for
channels 1 and 2.
R
0
245h
ACSR1_2A_10
15-0
Bytes 10 and 11 of audio group A channel status for
channels 1 and 2.
R
0
246h
ACSR1_2A_12
15-0
Bytes 12 and 13 of audio group A channel status for
channels 1 and 2.
R
0
247h
ACSR1_2A_14
15-0
Bytes 14 and 15 of audio group A channel status for
channels 1 and 2.
R
0
248h
ACSR1_2A_16
15-0
Bytes 16 and 17 of audio group A channel status for
channels 1 and 2.
R
0
249h
ACSR1_2A_18
15-0
Bytes 18 and 19 of audio group A channel status for
channels 1 and 2.
R
0
24Ah
ACSR1_2A_20
15-0
Bytes 20 and 21 of audio group A channel status for
channels 1 and 2.
R
0
RSVD
15-8
Reserved.
R/W
0
ACSR1_2A_22
7-0
Bytes 22 of audio group A channel status for
channels 1 and 2.
R
0
24Bh
GV7601
Final Data Sheet
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Rev.7
April 2014
132 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
24Ch to
24Fh
Register Name
RSVD
Bit
–
Description
R/W
Default
Reserved.
R/W
0
250h
ACSR3_4A_0
15-0
Bytes 0 and 1 of audio group A channel status for
channels 3 and 4.
R
0
251h
ACSR3_4A_2
15-0
Bytes 2 and 3 of audio group A channel status for
channels 3 and 4.
R
0
252h
ACSR3_4A_4
15-0
Bytes 4 and 5 of audio group A channel status for
channels 3 and 4.
R
0
253h
ACSR3_4A_6
15-0
Bytes 6 and 7 of audio group A channel status for
channels 3 and 4.
R
0
254h
ACSR3_4A_8
15-0
Bytes 8 and 9 of audio group A channel status for
channels 3 and 4.
R
0
255h
ACSR3_4A_10
15-0
Bytes 10 and 11 of audio group A channel status for
channels 3 and 4.
R
0
256h
ACSR3_4A_12
15-0
Bytes 12 and 13 of audio group A channel status for
channels 3 and 4.
R
0
257h
ACSR3_4A_14
15-0
Bytes 14 and 15 of audio group A channel status for
channels 3 and 4.
R
0
258h
ACSR3_4A_16
15-0
Bytes 16 and 17 of audio group A channel status for
channels 3 and 4.
R
0
259h
ACSR3_4A_18
15-0
Bytes 18 and 19 of audio group A channel status for
channels 3 and 4.
R
0
25Ah
ACSR3_4A_20
15-0
Bytes 20 and 21 of audio group A channel status for
channels 3 and 4.
R
0
RSVD
15-8
Reserved.
R/W
0
ACSR3_4A_22
7-0
Bytes 22 of audio group A channel status for
channels 3 and 4.
R
0
R/W
0
25Bh
25Ch to
25Fh
RSVD
–
Reserved.
260h
ACSR1_2B_0
15-0
Bytes 0 and 1 of audio group B channel status for
channels 1 and 2.
R
0
261h
ACSR1_2B_2
15-0
Bytes 2 and 3 of audio group B channel status for
channels 1 and 2.
R
0
262h
ACSR1_2B_4
15-0
Bytes 4 and 5 of audio group B channel status for
channels 1 and 2.
R
0
263h
ACSR1_2B_6
15-0
Bytes 6 and 7 of audio group B channel status for
channels 1 and 2.
R
0
264h
ACSR1_2B_8
15-0
Bytes 8 and 9 of audio group B channel status for
channels 1 and 2.
R
0
GV7601
Final Data Sheet
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Rev.7
April 2014
133 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
265h
ACSR1_2B_10
15-0
Bytes 10 and 11 of audio group B channel status for
channels 1 and 2.
R
0
266h
ACSR1_2B_12
15-0
Bytes 12 and 13 of audio group B channel status for
channels 1 and 2.
R
0
267h
ACSR1_2B_14
15-0
Bytes 14 and 15 of audio group B channel status for
channels 1 and 2.
R
0
268h
ACSR1_2B_16
15-0
Bytes 16 and 17 of audio group B channel status for
channels 1 and 2.
R
0
269h
ACSR1_2B_18
15-0
Bytes 18 and 19 of audio group B channel status for
channels 1 and 2.
R
0
26Ah
ACSR1_2B_20
15-0
Bytes 20 and 21 of audio group B channel status for
channels 1 and 2.
R
0
RSVD
15-8
Reserved.
R/W
0
ACSR1_2B_22
7-0
Bytes 22 of audio group B channel status for
channels 1 and 2.
R
0
R/W
0
26Bh
26Ch to
26Fh
RSVD
–
Reserved.
270h
ACSR3_4B_0
15-0
Bytes 0 and 1 of audio group B channel status for
channels 3 and 4.
R
0
271h
ACSR3_4B_2
15-0
Bytes 2 and 3 of audio group B channel status for
channels 3 and 4.
R
0
272h
ACSR3_4B_4
15-0
Bytes 4 and 5 of audio group B channel status for
channels 3 and 4.
R
0
273h
ACSR3_4B_6
15-0
Bytes 6 and 7 of audio group B channel status for
channels 3 and 4.
R
0
274h
ACSR3_4B_8
15-0
Bytes 8 and 9 of audio group B channel status for
channels 3 and 4.
R
0
275h
ACSR3_4B_10
15-0
Bytes 10 and 11 of audio group B channel status for
channels 3 and 4.
R
0
276h
ACSR3_4B_12
15-0
Bytes 12 and 13 of audio group B channel status for
channels 3 and 4.
R
0
277h
ACSR3_4B_14
15-0
Bytes 14 and 15 of audio group B channel status for
channels 3 and 4.
R
0
278h
ACSR3_4B_16
15-0
Bytes 16 and 17 of audio group B channel status for
channels 3 and 4.
R
0
279h
ACSR3_4B_18
15-0
Bytes 18 and 19 of audio group B channel status for
channels 3 and 4.
R
0
27Ah
ACSR3_4B_20
15-0
Bytes 20 and 21 of audio group B channel status for
channels 3 and 4.
R
0
GV7601
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Rev.7
April 2014
134 of 149
Proprietary & Confidential
Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-8
Reserved.
R/W
0
ACSR3_4B_22
7-0
Bytes 22 of audio group B channel status for
channels 3 and 4.
R
0
27Bh
27Ch to
27Fh
RSVD
–
Reserved.
R/W
0
RSVD
15-8
Reserved.
R/W
0
ACSR0
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR1
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR2
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR3
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR4
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR5
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
280h
281h
282h
283h
284h
285h
286h
ACSR6
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Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-8
Reserved.
R/W
0
ACSR7
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR8
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR9
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR10
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR11
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR12
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR13
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
ACSR14
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Table 4-35: HD Audio Core Configuration and Status Registers (Continued)
Address
Register Name
Bit
Description
R/W
Default
RSVD
15-8
Reserved.
R/W
0
ACSR15
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR16
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR17
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR18
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR19
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR20
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR21
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-8
Reserved.
R/W
0
ACSR22
7-0
Audio channel status to use when ACS_REGEN is set
or when adding audio channel status to
non-AES/EBU or S/PDIF audio. 8 bits per register
starting at register 280h and ending at register 296h.
W
0
RSVD
15-0
Reserved.
R
29
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
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Table 4-36: Ancillary Data Extraction Memory Access Registers
Address
Register Name
Bit
Description
R/W
Default
R
0
Extracted Ancillary Data (1024 words).
800h to
BFFh
ANC_PACKET_BANK
15-0
Bit 15-8: Most Significant Word (MSW)
Bit 7-0: Least Significant Word (LSW)
See 4.16.8 Ancillary Data Extraction.
Legend:
R = Read only
ROCW = Read Only, Clear on Write (must write ones to clear)
R/W = Read or Write
W = Write only
4.20 JTAG Test Operation
When the JTAG_EN pin of the GV7601 is set HIGH, the host interface port is configured
for JTAG test operation. In this mode, pins E7, F8, F7, and E8 become TDO, TCK, TMS, and
TDI. In addition, the RESET pin operates as the test reset pin.
Boundary scan testing using the JTAG interface is enabled in this mode.
There are two ways in which JTAG can be used:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly.
2. Under control of a host processor for applications such as system power on self
tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
accomplished with tri-state buffers used in conjunction with the JTAG_EN input signal.
This is shown in Figure 4-65.
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GV7601
Application HOST
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_EN
In-circuit ATE probe
Figure 4-65: In-Circuit JTAG
Alternatively, if the test capabilities are to be used in the system, the host processor may
still control the JTAG_EN input signal, but some means for tri-stating the host must exist
in order to use the interface at ATE. This is represented in Figure 4-66.
Application HOST
GV7601
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_EN
Tri-State
In-circuit ATE probe
Figure 4-66: System JTAG
Scan coverage is limited to digital pins only. There is no scan coverage for analog pins
VBG, SDO/SDO, TERM, LF, and LB_CONT.
The JTAG_EN pin must be held LOW during scan and therefore has no scan coverage.
Please contact your Gennum representative to obtain the BSDL model for the GV7601.
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4.21 Device Power-up
The GV7601 is designed to operate in a multi-voltage environment, therefore, any
power-up sequence is allowed. The charge pump, phase detector, core logic, serial
digital output and I/O buffers can all be powered up in any order.
4.22 Device Reset
Note: At power-up, the device must be reset to operate correctly.
In order to initialize all internal operating conditions to their default states, hold the
RESET signal LOW for a minimum of treset = 1ms after all power supplies are stable. There
are no requirements for power supply sequencing.
When held in reset, all device outputs are driven to a high-impedance state.
Nominal Level
95% of Nominal Level
Supply Voltage
t
t
reset
reset
RESET
Reset
Reset
Figure 4-67: Reset Pulse
4.23 Standby Mode
The STANDBY pin reduces power to a minimum by disabling all circuits except for the
register configuration. Upon removal of the signal to the STANDBY pin, the device
returns to its previous operating condition within 1 second, without requiring input
from the host interface.
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5. References & Relevant Standards
EN 50083-9
Interfaces for CATV/SMATV headends and similar professional equipment
for DVG/MPEG-2 transport streams
ISO/IEC
13818-1
Generic Coding of Moving Pictures and Associated Audio Systems
ITU-R BT.1120-6
Digital interfaces for HDTV studio signals
ITU-R BT.656
Interface for digital component video signals
ITU-R BT.709
Parameter values for the HDTV standards for production and international
programme exchange
SMPTE ST 272
Formatting AES Audio and Auxiliary Data into Digital Video Ancillary Data
Space
SMPTE ST 291
Ancillary Data Packet and Space Formatting
SMPTE ST 296
1280 x 720 Progressive Image Sample Structure - Analog and Digital
Representation and Analog Interface
SMPTE ST 299
24-Bit Digital Audio Format for SMPTE ST 292 Bit-Serial Interface
SMPTE RP165
Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital
Interfaces for Television
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6. Package & Ordering Information
6.1 Package Dimensions
TOP VIEW
BOTTOM VIEW
0.10 C
0.25 C A B
0.40~0.60 (100x)
PIN A1 CORNER
1
2
3
4
5
6
7
8
10 9
9 10
8
7
6
5
PIN A1 CORNER
4
3
2
1
A
A
B
C
C
1.00
B
E
F
E
F
G
G
H
H
J
J
K
K
1.00
0.70 REF
B
0.15
0.25 C
D
11±0.10
9.00
D
9.00
11±0.10
A
0.20 (4x)
Ball Pitch:
Substrate Thickness:
0.36
Mold Thickness:
0.50
0.70
1.00
C
SEATING PLANE
0.30~0.50
1.71 MAX
0.36 REF
Ball Diameter:
Package Outline
100L LBGA
Package Size: 11 x 11 x 1.71 mm
* The ball diameter, ball pitch, stand-off & package thickness
are different from JEDEC spec M0192 (Low profile BGA family)
Figure 6-1: GV7601 Package Dimensions
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6.2 Packaging Data
Table 6-1: Packaging Data
Parameter
Value
Package Type
11mm x 11mm 100-ball LBGA
Package Drawing
Reference
JEDEC M0192 (with exceptions noted in Package Dimensions on
page 142).
Moisture Sensitivity Level
3
Junction to Case Thermal
Resistance, θj-c
15.4°C/W
Junction to Air Thermal
Resistance, θj-a (at zero
airflow)
37.1°C/W
Junction to Board
Thermal Resistance, θj-b
26.4°C/W
Psi, ψ
0.4°C/W
Pb-free and RoHS
Compliant
Yes
6.3 Marking Diagram
Pin 1 ID
GV7601
XXXXXXE3
YYWW
XXXXXX - Last 6 digits (excluding decimal)
of SAP Batch Assembly (FIN) as listed
on Packing Slip.
E3 - Pb-free & Green indicator
YYWW - Date Code
Figure 6-2: GV7601 Marking Diagram
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6.4 Solder Reflow Profiles
The GV7601 is available in a Pb-free package. It is recommended that the Pb-free
package be soldered with Pb-free paste using the reflow profile shown in Figure 6-3.
Temperature
60-150 sec.
20-40 sec.
260°C
250°C
3°C/sec max
217°C
6°C/sec max
200°C
150°C
25°C
Time
60-180 sec. max
8 min. max
Figure 6-3: Pb-free Solder reflow Profile
6.5 Ordering Information
Part Number
Package
Pb-free
Temperature Range
GV7601-IBE3
100-ball BGA
Yes
-20°C to 85°C
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Index
A
PCLK 55
clock generation
AES/EBU or S/PDIF mode 93
audio 96
ancillary data
clock timing
checksum error 81
DDR parallel 56
checksum error correction & insertion 84
extraction 85
command work description 101
preamble remapping, TRS 85
correction & insertion
programmable, checksum calculation 82
ancillary data checksum 84
programmable, detection 81
EDH CRC 84
line based CRC 83
ancillary data checksum error 81
ancillary data checksum error correction & insertion 84
line number error 84
ancillary data detection & indication 78
TRS 83
ancillary data extraction 85
asynchronous lock 36
audio
HD registers 125–138
SD registers 113–124
audio channel status 98
read 98
regeneration 98
D
data block number error 100
data read or write access 102
DDR parallel clock timing 56
descrambling and word alignment 50
detailed descripton 32–140
detect
ancillary data, indication 78
audio clock generation 96
automatic video standards 72
audio control packets 94
ECC error, correction (HD mode only) 95
audio crosspoint block 97
EDH 74
audio data packet extraction block 94
EDH CRC error 78
audio de-embedder 90
EDH flag 75
audio mute 99
EDH packet 75
audio packet delete block 95
HD line number error 78
audio processing 96–100
line based CRC error 77
audio, serial
lock 35
data format support 92
programmable ancillary data 81
data I/O signals 90
TRS error 77
output word length 97
automatic video standards detection 72
video signal error, indication 76
device power-up 140
C
device reset 140
CEA-861 timing generation 61
DOUT[19:0] 50–57
checksum error
ancillary data 81, 84
clock
external crystal/reference 34
GV7601
Final Data Sheet
GENDOC-052155
E
ECC error 100
ECC error detection & correction block (HD mode only) 95
EDH CRC correction & insertion 84
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EDH CRC error detection 78
input
EDH detection 74
EDH flag detection 75
serial digital 32
interruption
signal 36
EDH packet detection 75
error correction
line number 84
J
video 82
JTAG test operation 138
Error Correction Codes... See ECC
error detection
L
line based CRC correction & insertion 83
ECC 95
line based CRC error detection 77
EDH CRC 78
HD line number 78
line based CRC 77
TRS 77
video signal 76
line number error correction & insertion 84
lock
asynchronous 36
lock detect 35
Error Detection and Handling... See EDH
M
error reporting 100
marking diagram 143
external crystal/reference clock 34
mute on loss of lock 100
F
O
full HD output formats 43
ordering information 144
functional description 32
output
serial digital 33
G
Gennum serial peripheral interface 101
P
GSPI 101
package & ordering information 142
GSPI timing 103
package dimensions 142
packaging data 143
H
H:V:F timing signal generation 59
HD audio registers 125–138
HD line number error detection 78
HD mode
ECC error detection & correction block 95
high definition 1080p output formats 41
high definition 720p output formats 43
high definition video output formats 40
host interface register maps 105–138
parallel data bus buffers 50
parallel output clock (PCLK) 55
parallel output in ASI mode 54
parallel output in data-through mode 55
parallel output in video mode 54
parallel video data outputs DOUT[19:0] 50–57
PCLK 55
power-up, device 140
programmable ancillary data checksum calculation 82
programmable ancillary data detection 81
I
programmable multi-function outputs 58
illegal word remapping 84
R
indication
ancillary data, detection 78
video signal error, detection 76
GV7601
Final Data Sheet
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serial digital 33
reclocker PLL loop bandwidth 34
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references & relevant standards 141
high definition 1080p 41
register maps
high definition 720p 43
host interface 105–138
registers
standard definition 37
video signal error detection & indication 76
HD audio 125–138
SD audio 113–124
video core 105–112
reset, device 140
S
SD audio core registers 113–124
serial audio data format support 92
serial audio data I/O signals 90
serial audio output word length 97
serial digital input 32
serial digital output 33
serial digital reclocker 33
setting packet DID 95
signal interruption 36
solder reflow profiles 144
standard definition video output formats 37
standby mode 140
T
timing
vertical 61
timing generation
CEA-861 61
timing signal
generator 57
genration, H:V:F 59
timing signal generator 57
TRS and ancillary data preamble remapping 85
TRS correction & insertion 83
TRS error detection 77
V
vertical timing 61
video core registers 105–112
video error correction 82
video functionality 37–50
video output formats
full HD 43
high definition 40
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Aviia™ is Gennum’s high bandwidth, all digital, long reach A/V interface for professional and
industrial applications; providing high definition video, digital audio, bi-directional control and
power over a single-wire robust and cost effective interface.
DOCUMENT IDENTIFICATION
CAUTION
FINAL DATA SHEET
ELECTROSTATIC SENSITIVE DEVICES
The product is in production. Semtech reserves the right to make changes to the
product at any time without notice to improve reliability, function or design, in
order to provide the best product possible.
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
© Semtech 2009
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
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no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper
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Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
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