GX434CDB

GX434 Monolithic 4x1 Video Multiplexer DATA SHEET FEATURES • low differential gain: 0.03% typ. at 4.43 MHz • low differential phase: 0.012 deg. typ. at 4.43 MHz • low insertion loss: 0.05 dB max at 100 kHz • low disabled power consumption: 5.2 mW typ. • high off isolation: 110 dB at 10 MHz • all hostile crosstalk @ 5 MHz, 97 dB typ. • bandwidth (-3dB) with 30 pF load, 100 MHz typ. • fast make-before-break switching: 200 ns typ. • TTL and 5 volt CMOS compatible logic inputs • low cost 14 pin DIP and16 pin SOIC packages • optimised performance for NTSC, PAL and SECAM applications APPLICATIONS Glitch free analog switching for... • High quality video routing • A/D input multiplexing • Sample and hold circuits • TV/ CATV/ monitor switching IN 0 GND IN 1 GND IN 2 CIRCUIT DESCRIPTION The GX434 is a high performance low cost monolithic 4x1 video multiplexer incorporating four bipolar switches with a common output, a 2 to 4 address decoder and fast chip select circuitry. The chip select input allows for multi-chip paralleled operation in routing matrix applications. The chip is selected by applying a logic 0 on the chip select input. Unlike devices using MOS bilateral switching elements, these bipolar circuits represent fully buffered, unilateral transmission paths when selected. This results in extremely high output to input isolation. They also feature fast make-before-break switching action. These features eliminate such problems as switching 'glitches' and output-to-input signal feedthrough. The GX434 operates from ± 7 to ± 13.2 volt DC supplies. They are specifically designed for video signal switching which requires extremely low differential phase and gain. Logic inputs are TTL and 5 volt CMOS compatible providing address and chip select functions. When the chip is not selected, the output goes to a high impedance state. PIN CONNECTIONS TOP VIEW PIN 1 14 +8V TOP VIEW AO A1 CS O/P NC REXT 7 8 -8V IN 0 GND IN 1 GND IN 2 PIN 1 16 +8V NC AO A1 CS O/P NC R 8 9 -8V EXT AVAILABLE PACKAGING 14 pin DIP and 16 pin SOIC (wide) GND IN 3 GND IN 3 NC FUNCTIONAL BLOCK DIAGRAM PIN CONNECTION 14 PIN DIP PIN CONNECTION 16 PIN SOIC GX434 IN 0 IN 1 IN 2 IN 3 (wide) X TRUTH TABLE X X X OUTPUT CS 0 0 0 A1 0 0 1 1 X A0 0 1 0 1 X OUTPUT IN 0 IN 1 IN 2 IN 3 HI - Z A0 A1 2 TO 4 DECODER LOGIC CHIP SELECT CS 0 1 X = DON'T CARE Document No. 510 - 34 - 2 GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 Japan Branch: A-302 M i yamae Vi l l age, 2–10–42 M i yamae, Suginami–ku, Tokyo 168, Japan tel. (905) 632-2996 fax: (905) 632-5946 tel. (03) 3334-7700 fax (03) 3247-8839 ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION Value & Units ± 13.5V 0° C ≤ TA ≤ 70° C -65° C ≤ T S ≤ 150° C 260° C -4V ≤ VIN ≤ +2.4V Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Part Number GX434 – – CDB GX434 – – CKC GX434 – – CTC Package Type 14 Pin DIP 16 Pin SOIC Tape 16 Pin SOIC Temperature Range 0° to 70° C 0° to 70° C 0° to 70° C Lead Temperature (Soldering, 10 Sec) Analog Input Voltage Analog Input Current Logic Input Voltage 50µA AVG, 10 mA peak -4V ≤ VL ≤ +5.5V CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE DEVICES EXCEPT AT A STATIC-FREE WORKSTATION +Vcc CS 0.7pF IN V IN OUT 1.2k CS CS 3mA #2 #3 #4 -V 1.5pF 2pF + 0.7pF 0.7pF 0.7pF VOUT 0.65V Common COUT 12pF 16pF + 1.3 V 600Ω Fig.1 Crosspoint Equivalent Circuit Fig. 2 Disabled Crosspoint Equivalent Circuit ELECTRICAL CHARACTERISTICS (VS = ± 8V DC, 0°C < TA < 70°C, CL = 30 pF, RL = 10kΩ unless otherwise shown.) GX434 PARAMETER Supply Voltage DC SUPPLY Supply current ISYMBOL ± VS I+ Chip selected (CS=0) Chip not selected (CS=1) Chip selected (CS=0) Chip not selected (CS=1) Analog Output VOUT IBIAS Extremes before clipping occurs. Analog Input Bias Current STATIC Output Offset Voltage VOS T A = 25°C, 75 Ω resistor on each input to gnd Output Offset Voltage Drift REXT = 33.2 kΩ , 1% ∆ VOS/ ∆T 0 7 +50 14 +200 mV µV/°C CONDITIONS MIN 7 TYP 8 10.5 0.4 10.2 0.25 +2 -1.2 22 MAX 13.2 11.5 0.58 11.2 0.38 V µA UNITS V mA mA mA mA 510 -34 -2 2 ELECTRICAL CHARACTERISTICS continued (VS = ± 8V DC, 0°C < TA < 70°C,CL = 30pF, RL = 10k Ω unless otherwise shown.) GX434 PARAMETER Crosspoint Selection Turn-On Time Crosspoint Selection Turn-Off Time Chip Selection Turn-On Time Chip Selection Turn-Off Time LOGIC Logic Input Thresholds SYMBOL CONDITIONS Control input to appearance of signal at the output. Control input to disappearance of signal at output. Control input to appearance of signal at output. Control input to disappearance of signal at output. 1 0 Chip selected A0,A1 = 1 Chip selected A0,A1 = 0 MIN 130 TYP 200 MAX 270 UNITS ns tADR-ON tADR-OFF t CS-ON t CS-OFF V IH VIL 390 600 800 ns 200 300 400 ns 460 700 940 ns 2.0 0.025 100 -0.04 0.03 120 - 1.1 5.0 0.1 1.0 30 0.04 +0.06 V V µA nA nA µA dB MHz dB Address Input Bias Current Chip Select Bias Current Insertion Loss Bandwidth (-3 dB) Gain Spread at 8 MHz I BIAS(ADR) IBIAS(CS) CS = 1 CS = 0 I.L. B.W. 1V p-p sine or sq. wave at 100 kHz Input to Output Signal Delay Matching (chip to chip) ∆tP T = 25°C, R = 75Ω A S ƒ= 3.579545 MHz 0°C < T < 70°C, R as A S above, ƒas above. - - ± 0.15 ± 0.3 degrees degrees Input Resistance DYNAMIC Input Capacitance RIN CIN Chip selected (CS = 0) Chip selected (CS = 0) Chip not selected (CS = 1) 900 - 2.0 2.4 14 15 0.03 0.012 0.05 0.025 kΩ pF pF Ω pF % degrees Output Resistance Output Capacitance Differential Gain Differential Phase All Hostile Crosstalk (see graph) ROUT COUT dg dp X TALK (AH) Chip selected (CS = 0) Chip not selected (CS = 1) at 3.579545 MHz VIN = 40 IRE, (Fig. 7) Sweep on 3 inputs 1V p-p 4th input has 10 Ω resistor to gnd. ƒ = 5 MHz (Fig. 6) - 94 97 - dB Chip Disabled Crosstalk (see graph) X TALK(CD) ƒ = 10 MHz (Fig. 5) +SR VIN = 3V p-p (C L = 0 pF) 100 110 - dB 360 160 450 200 - V/ µs V/ µs Slew Rate -SR REXT = 33.2kΩ, 1% 3 510 -34 -2 TYPICAL PERFORMANCE CURVES OF THE GX434 14 12 10 8 15 pF 0 -1 30 pF PHASE (DEGREES) -2 -3 50 pF 70 pF Load Capacitance Load Capacitance 0 pF GAIN (dB) 6 4 2 0 -2 -4 -4 -5 -6 -7 -8 -9 10 pF 27 pF 47 pF -6 1 10 100 200 -10 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) Gain vs Frequency Phase vs Frequency -40 -50 -60 -70 -80 -90 40 ALL HOSTILE CROSSTALK (dB) ALL HOSTILE CROSSTALK (dB) 50 60 70 80 90 100 110 RL = 10 kΩ 0.1 1 10 100 R IN = 75 Ω R IN RIN = 75 Ω R = 37.5Ω IN = 75 Ω = 10 Ω SW1 / SW2 SW0 - SW3 RIN = 37.5 Ω R IN RIN = 10 Ω -100 -110 0.1 RL = 10 k Ω 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) All Hostile Crosstalk (14 pin DIP) All Hostile Crosstalk (16 pin SOIC) For all graphs, VS = ± 8 V DC and TA = 25° C. The curves shown above represent typical batch sampled results. 510 -34 -2 4 110 CHIP DISABLED CROSSTALK (dB) 90 CHIP DISABLED CROSSTALK (dB) 100 110 100 Analog signal IN is 40 IRE (286 mV p-p) at 10 MHz 90 80 70 60 50 10 100 80 -1 0 +1 +2 +3 FREQUENCY (MHz) INPUT BIAS (V) Chip Disabled Crosstalk vs Frequency Chip Disabled Crosstalk vs Input Bias (V) DIFFERENTIAL PHASE & GAIN (DEGREES & %) +0.05 +0.04 +0.03 +0.02 +0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.8 -0.2 ƒ = 3.58 MHz Blanking level is clamped to V BIAS DIFFERENTIAL PHASE & GAIN (DEGREES & %) +0.05 Blanking level 0V DC dg % +0.04 dg % +0.03 dp ° +0.02 dp ° +0.01 -0.6 -0.4 0 +0.2 +0.4 +0.6 +0.8 0 1 2 3 3.58 4 5 8 10 INPUT BIAS (V) dg/dp vs Input Bias FREQUENCY (MHz) dg/ dp vs Frequency 30 MΩ +1.0 +0.8 10 M Ω 4 GAIN SPREAD (dB) +0.4 +0.2 0.1 -0.2 -0.4 -0.6 -0.8 -1.0 0.1 1 10 100 RIN ON 1 MΩ CIN OFF 100 kΩ CIN ON 2 3 10 k Ω -1 0 +1 +2 +3 1 FREQUENCY (MHz) INPUT BIAS (V) Normalized Gain Spread CL = 30pF Input Impedance 5 510 -34 -2 INPUT CAPACITANCE (pF) +0.6 RIN OFF GAIN SPREAD (dB) INPUT CAPACITANCE (pF) 0.1 V/div 10 mV/div 0.5 µs/div 1 µs/div Fig.3 Switching Transient (crosspoint to crosspoint) VIN Chip disabled crosstalk = 20 log VOUT Fig. 4 Switching Envelope (crosspoint to crosspoint) V OUT All hostile crosstalk = 20 log RIN VIN V OUT V OUT V IN ENABLED CROSSPOINT VIN 37.5 Ω RL ≥10 kΩ Fig. 5 Chip Disabled Crosstalk Test Circuit Fig. 6 All Hostile Crosstalk Test Circuit 10 µH BLANKING LEVEL 10 µH LUMINANCE LEVEL 8V CONTROL BIT FROM I/O PORT R.F. SIGNAL SOURCE 75 Ω 3.9 kΩ 220 Ω RELAY SWITCH 0.1µF 150 Ω AC COUPLING BUFFER AMP 75 Ω x2 DUT RL CL 75 Ω 150 Ω Fig. 7 Differential Phase and Gain Test Circuit DIFFERENTIAL GAIN AND PHASE TEST CIRCUIT The test circuit of Figure 7 allows two DC bias levels, set by the user, to be superimposed on a high frequency signal source. A computer controlled relay selects either the preset blanking or luminance level. One measurement is taken at each level and the change in gain or phase is calculated. This procedure is repeated one hundred times to provide a reasonably large sample. The results are averaged to reduce the standard deviation and therefore improve the accuracy of the measurement. The output from the device under test is AC coupled to a buffer amplifier which allows the buffer to operate at a constant luminance level so that it does not contribute any dg or dp to the measurement. 510 -34 -2 6 OPTIMISING THE PERFORMANCE OF THE GX434 1. Power Supply Considerations Supply Voltage ±8 +8/ -12 ± 12 +12/ -7 Differential Gain % (Typical) Table 1 shows the effect on differential gain (dg) and differential phase (dp) of various power supply voltages that may be used. A nominal supply voltage of ± 8 volts result in parameter values as shown in the top row of the table. By using other power supply voltage combinations, improvements to these parameters are possible at the sacrifice of increased chip power dissipation. Maximum degradation of the differential gain and phase occurs for the last combination of +12 , -7 volts along with an increase in power dissipation; these voltages are not recommended. Differential Phase degrees (Typical) 0.030 0.010 0.010 0.084 0.012 0.007 0.007 0.080 Table 2 shows the general characteristic variations of the GX434 when different combinations of power supply voltages are used. These changes are relative to a circuit using ± 8 volts Vcc. Supply Voltage ±7 Characteristic Changes - lower logic thresholds - max logic I/P (≈ 4.5V) - loss of off isolation (≈20 dB) - poorer dg and dp - slight increase in negative supply current - slight decrease in offset - very similar frequency response - better dg and dp - increase in supply current (10%) - increase in offset ( ≈ 2-4 mV) - very similar frequency response - better dg and dp - loss in off isolation (≈20 dB) - poorer dg and dp +8/ -12 ± 12 The GX434 does not require input DC biasing to optimise dg or dp nor does it need switching transient suppression at the output. Furthermore, both the analog signal and logic circuits within the chip use one common power supply, making power supply configurations relatively simple and straightforward. Several of the input characteristic graphs on pages 4-5 show that for best operation, the input bias should be 0 volts. The switching transient photographs on page 6 show how small the actual transients are and clearly show the make-beforebreak action of the GX434 video multiplexer switch. +12/ -7 7 510 -34 -2 2. Load Resistance Considerations 3. Multi-chip Considerations Whenever multi-chip bus systems are to be used, the total input and output capacitance must be carefully considered. The input capacitance of an enabled crosspoint (chip selected), is typically only 2 pF and increases slightly to 2.4 pF when the chip is disabled. The total output capacitance when the chip is disabled is approximately 15 pF per chip. Usually the GX434 multiplexer switch is used in a matrix configuration of (n x 1) crosspoints perhaps combined in an (n x m) total routing matrix. This means for example, that four ICs produce a 16 x 1 configuration and have a total output capacitance of 4 x15 pF or 60 pF if all four chips are disabled. For any one enabled crosspoint, the effective load capacitance will be 3 x15 pF or 45 pF. In a multi-input/multi-output matrix, it is important to consider the total input bus capacitance. The higher the bus capacitance and the more it varies from the ON to OFF condition, the more difficult it is to maintain a wide frequency response and constant drive from the input buffer. A 16 x 16 matrix using 64 ICs (16 x 4), would have a total input bus capacitance of 16 x 2.4 pF or 40 pF. The GX434 crosspoint switch is optimised for load resistances equal to or greater than 3 kΩ. Figure 8 shows the effect on the differential gain and phase when the load resistance is varied from 100 Ω to 100 kΩ. DIFFERENTIAL PHASE & GAIN (DEGREES & %) 10 ƒ= 3.58 MHz, 20 IRE BLANKING LEVEL = 0V DC 1.0 0.1 dp dg 0.01 0.001 100 1K 10K 100K RL (Ω) Fig. 8 dg/dp vs RL The negative slew rate is dependant upon the output current and load capacitance as shown below. -SR = I + 3 mA I ≤ 8 mA CL The current I is determined from the following equation: I = -VEE R ≥1kΩ R It is possible to increase the negative slew rate (-S.R.) and thus the large signal bandwidth, by adding a resistance from the output to - VEE. This resistor increases the output current above the 3 mA provided by the internal current generator and increases the negative slew rate. The additional slew rate improving resistance must not be less than 1kΩ in order to prevent excessive currents in the output of the device. An adverse effect of utilising this negative slew rate improving resistor, is the increase in differential phase from typically 0.009° to 0.014° . Under these same conditions, the differential gain drops from typically 0.033 % to 0.021 %. +8V 1 2 3 4 X G 4 41 X G 4 41 X G 4 41 X G 4 41 BUFFERS 5 6 7 8 X G 4 41 X G 4 41 X G 4 41 X G 4 41 INPUT 9 10 11 12 X G 4 41 X G 4 41 X G 4 41 X G 4 41 IN 0 GND IN 1 GND IN 2 GND IN 3 1 2 3 4 5 6 7 14 13 12 A1 11 10 9 8 NC R ≥ 1kΩ CS OUTPUT A0 n O U TP U T B U FF E RS 1 2 3 m -8V Fig.9 Negative Slew Rate (-SR) Improvement Fig.10 Multi-chip Connections 510 -34 -2 8 APPLICATIONS INFORMATION The GX434 multiplexer is a very high performance, wideband circuit requiring careful external circuit design. Good power supply regulation and decoupling are necessary to achieve optimum results. The circuit designer must use proper lead dress, component placement and PCB layout as in any high frequency circuit. Functionally, the video switches are non-inverting, unity gain bipolar switches with buffered inputs requiring DC coupling and 75Ω line terminating resistors when directly driven from 75Ω cable. The output must be buffered to drive 75Ω lines. This is usually accomplished with the addition of an operational amplifier/ buffer which also allows adjustments to be made to the gain, offset and frequency response of the overall circuit. VIDEO INPUTS GX434 SWITCHES 0.1 1 2 3 4 5 6 7 75 75 75 0.1 1 2 3 4 5 6 7 75 75 75 75 -8V 0.1 V8 V9 V 10 V 11 75 75 75 75 1 2 3 4 5 6 7 IN 0 GND IN 1 GND IN 2 GND IN 3 0.1 -8V 0.1 1 IN 0 +V 2 GND A 0 3 A1 IN 1 4 GND CS 5 IN 2 OUT 6 GND R EXT 7 -V IN 3 75 75 75 75 -8V 0.1 14 13 12 11 10 9 8 +8V 14 +V 13 A0 A 1 12 CS 11 10 OUT REXT 9 -V 8 +8V 330 2-10pF +V 14 A 0 13 A 1 12 11 CS GND 10 IN 2 OUT GND REXT 9 -V 8 IN 3 IN 0 GND IN 1 0.1 IN 0 GND IN 1 GND IN 2 GND IN 3 0.1 -8V +8V +V 14 13 A0 A 1 12 CS 11 10 OUT REXT 9 -V 8 +8V A typical video routing application is shown in Figure 11. Four ICs are used in a 16 x 1 multiplexer switching circuit. An external address decoder is shown which generates the 16 address and chip enable codes from a binary number. The address inputs to each chip are active high while the chip select inputs are active low. Depending on the application and speed of the logic family used, latches may be required for synchronization where timing and delays are critical. Since the individual crosspoint switching circuits are unidirectional bipolar elements, low crosstalk and high isolation are inherent. The makebefore-break switching characteristics of the GX434 means virtually 'glitch' free switching. BINARY ADDRESS DECODER V0 V1 V2 V3 75 A0 A1 33K 1% 4 5 6 7 1 2 3 2 1 A2 A3 ENABLE 74HC139 V4 V5 V6 V7 8 16 +5V 0.1 33K 1% +5V 0.1 + 7 6 3 100 75 2 4 250 Video Out 500 300 33K 1% 0.1 CLC 410 (comlinear) -5V DOCUMENT IDENTIFICATION PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice. DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. V 12 V 13 V14 V15 33K 1% All resistors in ohms, all capacitors in microfarads unless otherwise stated. Fig.11 16 x 1 Video Multiplexer Circuit Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. ©Copyright August 1989 Gennum Corporation. Revision date: January 1993. All rights reserved. Printed in Canada. 9 510 -34 -2