SC1112TSTR

SC1112 Triple Low Dropout Regulator Controllers POWER MANAGEMENT Description Features The SC1112 was designed for the latest high speed motherboards. It includes three low dropout regulator controllers. The controllers provide the power for the system AGTL bus Termination Voltage, Chipset, and clock circuitry. ‹ Triple linear controllers ‹ Selectable and adjustable output voltages ‹ LDOs track input voltage within 200mV (Function of ‹ ‹ ‹ ‹ An adjustable controller with a 1.2V reference is available, while two selectable outputs are provided for the VTT (1.25 V or 1.5V, SC1112) or (1.2V or 1.5V, SC1112A) and the AGP (1.5V or 3.3V). The SC1112 low dropout regulators are designed to track the 3.3V power supply as the VTTIN supply is cycled On and Off. A latched short circuit protection is also available for the VTT output. the MOSFETs used) until regulation Integrated charge pump Programmable power good delay signal Latched over current protection (VTT) Pb-free package available, fully WEEE and RoHS compliant Applications ‹ Pentium® III Motherboards Other features include an integrated charge pump that ‹ Triple power supplies provides adequate gate drives for the external MOSFETs, and a capacitive programable delay for the power good signal. Typical Application Circuit +3.3V VTT +5V STBY 1K C1 10u R1 C6 330u 5VSTBY Q2 ADJGATE ADJ 0.1u ADJSEN C11 RA 1u C13 0.1u C12 330u RB C10 22n C5 C3 0.1u SC1112/A POWER GOOD GND VTTGATE CAP+ VTTSEN FC AGPSEL DELAY VTTSEL VTTIN VTT SELECT Signal Revision: August 30, 2006 C14 330u AGP AGPSEN CAP- PWRGD Q3 AGPGATE 1 Q1 C2 C18 330u C16 330u C17 0.1u VTT C19 330u C8 330u C9 0.1u AGP SELECT Signal www.semtech.com SC1112 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units 5VSTBY to GND -0.3 to +7 V VTTSEN to GND -0.3 to 5 V AGPSEN to GND -0.3 to 5 V ADJSEN to GND -0.3 to 5 V Operating Temperature Range TA 0 to +70 °C Junction Temperature Range TJ 0 to +125 °C Storage Temperature Range TSTG -65 to +150 °C Lead Temperature (Soldering) 10 Sec. TL 300 °C Thermal Resistance Junction to Ambient SOIC TSSOP θJ A 130 115 °C/W Thermal Impedance Junction to Case SOIC TSSOP θJ C 30 38 °C/W ESD 2 kV ESD Rating (Human Body Model) Electrical Characteristics Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C Parameter Symbol Conditions Min Typ Max Units 4.75 5 5.25 V 6 8 12 mA Supply (5VSTBY) Supply Voltage 5VSTBY Supply Current I5VSTBY 5VSTBY = 5V VTT Short Circuit Protection VTT Short Circuit Delay Timer Threshold(4) SCTh 1.5 V VTT Short Circuit Delay Time(4) SCtd (Cdelay*SCTH)/ISC S ISC 16 22 28 µA VTTSCTh 650 700 750 mV PGDelay_TH 1.450 1.500 1.550 V PWRGD Threashold(5) PGTH_1.2 1.060 1.085 1.110 V PWRGD Threashold (5) PGTH_1.5 1.330 1.350 1.390 V PWRGD Delay Time(5) PGtd_1.2 (Cdelay*PGTH_1.2)/IPG S PGtd_1.5 (Cdelay*PGTH_1.5)/IPG S VTT Short Circuit Delay Source Current(4) VTT Short Circuit Threshold(4) VTT Pow er Good PWRGD Delay Timer Threshold(5) PWRGD Delay Time (5) PWRGD Source Current (5) IPG 16 22 28 µA VTTINTH 1.45 1.52 1.55 V Linear Sections VTT Input Supply Threshold Tracking Difference  2006 Semtech Corp. (1)(3) DeltaTRACK VIN = 3.30V, IO = 0A 2 200 mV www.semtech.com SC1112 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: 5VSTBY=4.75V to 5.25V; VTTIN=3.3V; TA = 25°C Parameter Symbol Conditions Min Typ Max Units (SC1112A) VTT1.2 IO = 0 to 2A, VTTSEL = LOW 1.176 1.200 1.224 V (SC1112) VTT1.25 IO = 0 to 2A, VTTSEL = LOW 1.225 1.250 1.275 VTT1.5 IO = 0 to 2A, VTTSEL = HIGH 1.470 1.500 1.530 V AGP1.5 IO = 0 to 2A, AGPSEL = LOW 1.470 1.500 1.530 V AGP3.3 IO = 0 to 2A, AGPSEL = HIGH 3.234 3.300 AD J IO = 0 to 2A -2% 1.2*(1+RA/RB) +2% V 90 120 140 µA 1 5 µA 150 170 µA 1 5 µA Linear Sections (Cont.) Output Voltage VTT Output Voltage AGP Output Voltage ADJ VTTSEN Bias Current (SC1112) IbiasVTTSEN VTTSEN Bias Current (SC1112A) IbiasVTTSEN AGPSEN Bias Current IbiasAGPSEN ADJSEN Bias Current IbiasADJSEN VTT Gate Current IsourceVTTgate 110 5VSTBY = 4.75V, Vgate = 3.0V IsinkVTTgate AGP Gate Current IsourceAGPgate 5VSTBY = 4.75V, Vgate = 3.0V IsinkAGPgate ADJ Gate Current IsourceADJgate 5VSTBY = 4.75V, Vgate = 3.0V IsinkADJgate V 500 µA 500 µA 500 µA 500 µA 500 µA 500 µA Load Regulation LOADREG VTTIN = 3.30V, IO = 0 to 2A 0.3 % Line Regulation LINEREG VTTIN = 3.13V to 3.47V, Io = 2A 0.3 % Gain (AOL)(2) GAINLDO LDOS Output to GATE 50 dB Notes: (1) All electrical characteristics are for the application circuit on page 19. (2) Guaranteed by design (3) Tracking Difference is defined as the delta between 3.3V Vin and the VTT, AGP, ADJ output voltages during the linear ramp up until regulation is achieved. The Tracking Voltage difference might vary depending on MOSFETs Rdson, and Load Conditions. (4) During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled. (5) PWRGD pin is kept low during the power up, until the VTT output has reached its PGtd1.2 or PGtd1.5 level. At that time the PWRGD source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the capacitor is charged above the PGDelay_TH (1.5V), the PWRGD pin is released from ground.  2006 Semtech Corp. 3 www.semtech.com SC1112 POWER MANAGEMENT Timing Diagrams NORMAL STARTUP CONDITION VTTIN VTTIN=1.5V VTT The delay capacitor does not begin charging until VTTIN has reached 1.5V and VTT is above the powergood threshold of 1.08V. Once DELAY reaches 1.5V, the PWRGD signal goes high. DELAY DELAY=1.5V VTTGATE initially turns on hard, until VTT reaches regulation. Then VTTGATE drops to its normal regulating level. PWRGD VTTGATE SHORT-CIRCUIT STARTUP VTTIN VTTIN=1.5V VTT The delay capacitor does not begin charging until VTTIN has reached 1.5V and VTT is below the short circuit threshold of 0.7V. VTTGATE initially turns on hard and is latched off when DELAY DELAY reaches 1.5V and VTT is below 0.7V DELAY=1.5V PWRGD VTTGATE  2006 Semtech Corp. 4 www.semtech.com SC1112 POWER MANAGEMENT Timing Diagrams (Cont.) SHORT-CIRCUIT DURING NORMAL OPERATION VTTIN VTT Once VTT drops out of regulation, VTTGATE turns on harder to try and raise VTT. When VTT drops below 1.08V, the delay capacitor is discharged and PWRGD goes low. When VTT drops below 0.7V, the delay capacitor begins charging. VTT=1.08V VTT=0.7V DELAY DELAY=1.5V If VTT is still below 0.7V when DELAY reaches 1.5V, VTTGATE is latched off. PWRGD VTTGATE SHORT-CIRCUIT AND RECOVERY DURING NORMAL OPERATION VTTIN Once VTT drops out of regulation, VTTGATE turns on harder to try and raise VTT. VTT When VTT drops below 1.08V, the delay capacitor is discharged and PWRGD goes low. When VTT drops below 0.7V, the delay capacitor begins charging. If VTT recovers above 0.7V before DELAY reaches 1.5V, DELAY is again discharged. VTT=1.08V VTT=0.7V VTT=1.08V DELAY DELAY=1.5V If VTT reaches 1.08V the delay capacitor begins charging and normal operation continues. PWRGD VTTGATE  2006 Semtech Corp. 5 www.semtech.com SC1112 POWER MANAGEMENT Pin Configuration Ordering Information Top View 5VSTBY PWRGD DELAY VTTSEL AGPSEL ADJGATE ADJSEN CAP- 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 Part Number (1)(2) Temp Range (TJ) SO-16 0° to 125°C TSSOP-16 0° to 125°C SC1112STR GND VTTIN VTTGATE VTTSEN AGPGATE AGPSEN FC CAP+ SC1112STRT(3) SC1112ASTR SC1112TSTR SC1112TSTRT(3) SC1112ATSTR SC1112EVB Evaluation Board Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Part Number (SO-16): SC1112STR and SC1112STRT = 1.25V and SC1112ASTR = 1.2V. Part Number (TSSOP-16): SC1112TSTR = 1.25V and SC1112ATSTR = 1.2V. (3) Pb-free product. This product is fully WEEE and RoHS compliant. (16-Pin SOIC or TSSOP)  2006 Semtech Corp. P ackag e 6 www.semtech.com SC1112 POWER MANAGEMENT Pin Descriptions Pin # Pin Name Pin Function 1 5VSTBY 5V Standby input, supplies power for Ref, Charge Pump, Oscillator and FET controllers. 2 PWRGD Open collector Power Good Flag for VTT output. 3 DELAY A capacitor from this pin to GND will program the delay for the Power Good Flag of VTT output and the glitch immunity time. 4 VTTSEL TTL signal that programs the VTT output voltage: VTTSEL = LOW, VTT = 1.2XV VTTSEL = HIGH, VTT = 1.5V 5 AGPSEL TTL signal that programs the AGP output voltage: AGPSEL = LOW, AGP = 1.5V AGPSEL = HIGH, AGP = 3.3V 6 ADJGATE Gate drive output for AGP. 7 A D JS E N Sense input for ADJ. 8 C AP- Negative connection to boost capacitor. 9 C AP+ Positive connection to boost capacitor. 10 FC 11 AGPSEN Sense input for AGP. 12 AGPGATE Gate drive output for AGP. 13 VTTSEN Sense input for VTT. 14 VTTGATE Gate drive output for VTT. 15 VTTIN Short circuit sense line connected to the 3.3Vin. 16 GND Ground. Filter capacitor for the internal charge pump should be connected from this pin to GND. NOTE: (1) All logic level inputs and outputs are open collector TTL compatible.  2006 Semtech Corp. 7 www.semtech.com SC1112 POWER MANAGEMENT Block Diagram 5VSTBY VTTSEL FC 1.5V 1.5V Bandgap Reference +- + _ 1.35V 1.2V + _ 1.08V VTTGATE Disable1.5 VTTSEN 1.2V Vref + _ 0.7V Disable1.2 + _ S VTTIN Q R DELAY FC _ 1.5V 1.5V + _ + AGPGATE Disable1.5 + _ AGPSEN Vref + _ Disable3.3 0.7V Oscillator + _ VTTSEN FC ChargePump PWRGD + _ Pwrgd Threshold 1.2V + _ ADJGATE ADJSEN GND  2006 Semtech Corp. AGPSEL CAP+ CAP- 8 www.semtech.com SC1112 POWER MANAGEMENT Typical Characteristics VTT(1.5V) Output Voltage @ Io = 2A vs Ta 1.5035 1.5050 1.5030 1.5045 1.5025 1.5040 1.5020 VTT 1.5 (V) VTT1.5(V) VTT(1.5V) Output Voltage @ Io = 0A vs Ta 1.5055 1.5035 1.5030 1.5015 1.5010 1.5025 1.5005 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.5020 5V S tby = 5.25V 5V S tby = 5.00V 5V S tby = 4.75V 1.5000 1.5015 1.4995 0 10 20 30 40 50 60 70 0 10 20 30 VTT(1.25V) Output Voltage @ Io = 0A vs Ta 50 60 70 VTT(1.5V) Output Voltage @ Io = 2A vs Ta 1.2485 1.2465 1.2480 1.2460 1.2475 1.2455 1.2470 1.2450 VTT1.2(V) VTT 1.2(V) 40 T a (°C .) Ta (°C.) 1.2465 1.2445 1.2440 1.2460 1.2455 1.2435 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.2450 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.2430 1.2425 1.2445 0 10 20 30 40 50 60 0 70 10 20 30 40 50 60 70 Ta (°C.) Ta (°C.) VTT Input Supply Threshold vs Ta VTT Sense Bias current vs Ta 1.498 116 5V Stby = 5.25V 5V Stby = 5.00V 1.497 5V Stby = 4.75V 114 1.496 Ibias VTTSEN (uA) VTTINTH(V) 112 1.495 1.494 110 108 1.493 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 1.492 106 1.491 104 0 10 20 30 40 50 60 70 0 Ta (°C.)  2006 Semtech Corp. 10 20 30 40 50 60 70 Ta (°C.) 9 www.semtech.com SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) VTT Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta VTT Short circuit Delay source current vs Ta 800 23.60 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V Source current Sink current 750 23.40 23.20 700 23.00 22.80 ISC(uA) IVTT_Gate(uA) 650 600 22.60 22.40 550 22.20 500 22.00 450 21.80 400 21.60 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) 40 50 60 70 Ta (°C.) VTT Short circuit Delay Time (Cdelay = 0.1uF) vs Ta 8.40 8.30 SCtd(mS) 8.20 8.10 8.00 7.90 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 7.80 7.70 0 10 20 30 40 50 60 70 Ta (°C.) VTT Short circuit Delay Timer Threshold vs Ta 1.515 1.510 1.505 1.500 SCth(V) 1.495 1.490 1.485 1.480 1.475 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 1.470 1.465 0 10 20 30 40 50 60 70 Ta (°C.)  2006 Semtech Corp. 10 www.semtech.com SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) VTT (1.25V) Power Good Threshold vs Ta VTT (1.25V) Power Good Delay Time vs Ta 1.098 8.40 1.096 8.30 1.094 8.20 PG td_1.25(mS) PG TH_1.25(V) 1.092 1.090 1.088 8.10 8.00 1.086 7.90 5V Stby = 4.75V 1.084 5V Stby = 5.00V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 5.25V 7.80 1.082 1.080 7.70 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) 40 50 60 70 Ta (°C.) VTT (1.5V) Power Good Threshold vs Ta VTT (1.5V) Power Good Delay Time vs Ta 8.40 1.361 1.360 8.30 1.359 1.358 8.20 PGtd_1.5(mS) PGTH_1.5 (V) 1.357 1.356 1.355 8.10 8.00 1.354 7.90 1.353 5V Stby = 4.75V 5V Stby = 5.00V 1.352 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.351 5V Stby = 5.25V 7.80 1.350 7.70 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) 40 50 60 70 Ta (°C.) VTT Power Good Source current vs Ta 23.60 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 23.40 23.20 23.00 IPG(uA) 22.80 22.60 22.40 22.20 22.00 21.80 21.60 21.40 0 10 20 30 40 50 60 70 Ta (°C.)  2006 Semtech Corp. 11 www.semtech.com SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) AGP (1.5V) Output Voltage @ Io = 2A vs Ta 1.5035 1.5050 1.5030 1.5045 1.5025 1.5040 1.5020 1.5035 1.5015 AGP1.5(V) AGP1.5 (V) AGP (1.5V) Output Voltage @ Io = 0A vs Ta 1.5055 1.5030 1.5010 1.5025 1.5005 1.5020 1.5000 1.5015 1.4995 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.5010 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 1.4990 1.4985 1.5005 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) AGP (3.3V) Output Voltage @ Io = 0A vs Ta 50 60 70 AGP (3.3V) Output Voltage @ Io = 2A vs Ta 3.2900 3.2900 3.2890 3.2890 3.2880 3.2880 3.2870 3.2870 AGP3.3(V) AGP3.3 (V) 40 Ta (°C.) 3.2860 3.2850 3.2860 3.2850 3.2840 3.2840 5V Stby = 5.25V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 4.75V 3.2830 3.2830 3.2820 3.2820 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) 40 50 60 70 Ta (°C.) AGP Gate Current @ Vgate = 3V, 5V Stby = 4.75 vs Ta AGP Sense Bias current vs Ta 142 900 5V Stby = 5.25V Sink current 5V Stby = 5.00V 5V Stby = 4.75V 140 Source current 850 138 136 IAGP_Gate(uA) IbiasAGPSEN (uA) 800 134 750 700 132 650 130 128 600 0 10 20 30 40 50 60 70 0 Ta (°C.)  2006 Semtech Corp. 10 20 30 40 50 60 70 Ta (°C.) 12 www.semtech.com SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) ADJ (1.2V) Output Voltage @ Io = 0A vs Ta ADJ (1.2V) Output Voltage @ Io = 2A vs Ta 1.2020 1.1955 1.2010 1.1950 1.1945 1.2000 ADJ1.2(V) ADJ1.2(V) 1.1940 1.1990 1.1980 1.1935 1.1930 1.1970 5V Stby = 5.25V 1.1925 5V Stby = 5.00V 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 5V Stby = 4.75V 1.1960 1.1920 1.1950 1.1915 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) 40 50 60 70 Ta (°C.) ADJ Sense Bias current vs Ta 350 ADJ Gate Current @ Vgate = 3V, 5V Stby = 4.75V vs Ta 900 5V Stby = 4.75V 5V Stby = 5.00V 5V Stby = 5.25V 330 Sink current Source current 850 310 290 IADJ_Gate(uA) IbiasADJSEN (uA) 800 270 250 750 230 700 210 190 650 170 150 600 0 10 20 30 40 50 60 70 0 Ta (°C.)  2006 Semtech Corp. 10 20 30 40 50 60 70 Ta (°C.) 13 www.semtech.com SC1112 POWER MANAGEMENT Typical Characteristics (Cont.) I 5V Stby vs Ta Output Select Threshold vs Ta 7.50 1.60 VTTSEL 7.30 AGPSEL 1.55 7.10 1.50 Output Select Threshold (V) I5vstby (mA) 6.90 6.70 6.50 6.30 6.10 1.45 1.40 1.35 1.30 5.90 5V Stby = 5.25V 5V Stby = 5.00V 5V Stby = 4.75V 5.70 1.25 5.50 1.20 0 10 20 30 40 50 60 70 0 10 20 30 Ta (°C.) Line Regulation VTTIN = 3.13V to 3.47V Io = 2A vs Ta 50 60 70 Load Regulation VTTIN = 3.3V Io = 0 to 2A vs Ta 160.0E-3 180.0E-3 140.0E-3 170.0E-3 120.0E-3 160.0E-3 100.0E-3 150.0E-3 Load Regulation(%) Line Regulation(%) 40 Ta (°C.) 80.0E-3 60.0E-3 140.0E-3 130.0E-3 120.0E-3 40.0E-3 VTT 1.25V VTT 1.25V AGP 1.25V AGP 1.25V 110.0E-3 20.0E-3 100.0E-3 000.0E+0 0 10 20 30 40 50 60 0 70 10 20 30 40 50 60 70 Ta (°C.) Ta (°C.) Charge Pump Output Voltage vs Ta Charge Pump Frequency vs Ta 9.32 375 V Charge Pump Charge Pump Frequency 9.31 370 9.30 Charge Pump Frequency (kHz) V Charge Pump(V) 9.29 9.28 9.27 9.26 9.25 365 360 355 9.24 9.23 350 9.22 345 9.21 0 10 20 30 40 50 60 0 70  2006 Semtech Corp. 10 20 30 40 50 60 70 Ta (°C.) Ta (°C.) 14 www.semtech.com SC1112 POWER MANAGEMENT Typical Gain & Phase Margin SC1112 Gain / Phase VTT = 1.25V @ 2A SC1112 Gain / Phase VTT = 1.5V @ 2A Gain Phase (deg) 50 Gain 40 60 180 200 Gain Phase (deg) 50 160 Gain 40 140 100 10 80 0 Gain (dB) Phase 20 Phase (deg) 30 120 100 10 80 40 -10 -20 20 -20 -30 0 1000000 -30 10 100 1000 10000 100000 120 Phase 20 0 60 -10 60 40 20 10 100 1000 Freq (Hz) 10000 100000 0 1000000 Freq (Hz) SC1112 Gain / Phase AGP = 1.5V @ 2A SC1112 Gain / Phase ADJ = 1.2V @ 2A 200 50 Gain Phase (deg) 40 180 160 140 30 Gain (dB) 200 Phase (deg) 60 50 200 Gain Phase (deg) 180 40 Gain Gain 160 180 160 30 30 Phase 10 100 80 0 60 140 120 Phase 20 100 10 80 60 0 -10 40 -20 40 -10 20 -30 10 100 1000 10000 100000 20 0 1000000 -20 10 Freq (Hz)  2006 Semtech Corp. Phase (deg) 120 Gain (dB) Gain (dB) 20 Phase (deg) 140 100 1000 10000 100000 0 1000000 Freq (Hz) 15 www.semtech.com SC1112 POWER MANAGEMENT Applications Infomation Theory Of Operation The SC1112 was designed for the latest high speed mother boards requiring a controlled power up sequencing of the Outputs, and a programmable delay for the Power good signal. Three Linear controllers have been incorporated into the SC1112. The VTT output can be programmed to either a 1.250V or a 1.500V by applying a LOW or a HIGH control signal to the VTTSEL pin. AGP output can also be programmed via AGPSEL pin to a 1.50V or a 3.30V. The SC1112 also provides an Adjustable output which utilizes a resistive voltage divider. Also included is an overcurrent protection circuit that monitors the VTT voltage. If the output voltage drops below 700mV, as would occur during an overcurrent or short condition, the device will pull the drive pin low and latch off the output. Fixed Output Voltage Options (VTT, AGP) Please refer to the Application Circuit on Page 1. The VTT and the AGP fixed output voltage can be programed from a Control logic signal. Table below shows the possible voltages: The +5VSTBY supply will power the internal Reference, Charge Pump, Oscillator, and the Fet controllers. After the +5VSTBY has been established, LDO outputs will track the VTTIN (3.30V) supply as it is applied. VTTSEL AGPSEL VTT AGP 0 0 1.25V 1.50V 0 1 1.25V 3.30V 1 0 1.50V 1.50V An external capacitor connected to the Delay pin will program the VTT short circuit delay time (SCtd), and the PWRGD delay time (PGtd). 1 1 1.50V 3.30V During power up, an internal short circuit glitch timer will start once the VTT Input Voltage exceeds the VTTINTH (1.5V). During the glitch timer immunity time, determined by the Delay capacitor (Delay time is approximately equal to (Cdelay*SCTH)/ISC), the short circuit protection is disabled to allow VTT output to rise above the trip threshold (0.7V). If the VTT output has not risen above the trip threshold after the immunity time has elapsed, the VTT output is latched off and will only be enabled again if either the VTT input voltage or the 5VSTBY is cycled. PWRGD pin is kept low during the power up, until the VTT output has reached its PGtd1.25 or PGtd1.5 level. At that time the PWRGD source current IPG (20uA) is enabled and will start charging the external PWRGD delay capacitor connected to the DELAY pin. Once the capacitor is charged above the PGDelay_TH (1.5V), the PWRGD pin is released from ground. A detailed timing diagram is shown on pages 4 to 5.  2006 Semtech Corp. Once the VTTSEL or the AGPSEL signal is established, an internal resistive divider is used to compare the bandgap reference voltage with the feedback output voltage. The drive pin voltage is then adjusted to maintain the output voltage set by the internal resistor divider. Referring to the block diagram on page 8. It is possible to adjust the output voltage of the VTT or AGP, by applying an external resistor divider to the sense pin (please refer to Figure 1 on Page 17). Since the sense pin sinks a nominal 100µA, the resistor values should be selected to allow 10mA to flow through the divider. This will ensure that variations in this current do not adversely affect output voltage regulation. Thus a target value for R2 (maximum) can be calculated: R2 ≤ V OUT ( FIXED ) 10 mA Ω The output voltage can only be adjusted upwards from the fixed output voltage, and can be calculated using the following equation: VOUT ( ADJUSTED 16 ) R1   = VOUT ( FIXED ) •  1 +  + R1 • 100 µ A R2   Volts www.semtech.com SC1112 POWER MANAGEMENT Applications Infomation (Cont.) +3.3V +5V STBY C1 10u C3 0.1u SC1112 5VSTBY ADJGATE ADJSEN GND C14 330u AGP AGPSEN CAP- VTTGATE CAP+ VTTSEN FC AGPSEL DELAY VTTSEL PWRGD Q3 AGPGATE VTTIN Q1 C2 C18 330u C16 330u C17 0.1u VTT C19 330u C8 330u C9 0.1u R1 VTT SELECT Signal AGP SELECT Signal R2 Figure 1: Adjusting The Output Voltage of VTT or AGP Adjustable Output Voltage Option The adjustable output voltage option does not have an internal resistor divider. The adjust pin connects directly to the inverting input of the error amplifier, and the output voltage is set using external resistors (please refer to Figure 2). In this case, the adjust pin sources a nominal 0.5µA, so the resistor values should be selected to allow 50µA to flow through the divider. Again, a target value for RB (maximum) can be calculated: 1 .200 V RB ≤ 50 µ A VTT 1K R1 C6 330u Ω 5VSTBY ADJGATE 0.1u The output voltage can be calculated as follows: VOUT SC11 POWER GOOD Q2 ADJSEN C11 RA CAPCAP+ RA   = 1 .200 •  1 +  − 0.5µA • RA RB   1u C10 22n C5 FC DELAY C13 0.1u The maximum output voltage that can be obtained from the adjustable option is determined by the input supply voltage and the RDS(ON) and gate threshold voltage of the external MOSFET. Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and a worst-case drive voltage of 9V, VOUT(MAX) is given by: C12 330u RB PWRGD Figure 2 VOUT(MAX) = VTTIN(MIN) − IOUT(MAX) • RDS(ON)(MAX )  2006 Semtech Corp. 17 www.semtech.com SC1112 POWER MANAGEMENT Applications Infomation (Cont.) Short Circuit Protection Layout Guidelines The VTT short circuit protection feature of the SC1112 is implemented by using the RDS(ON) of the MOSFET. As the output current increases, the regulation loop maintains the output voltage by turning the FET on more and more. Eventually, as the RDS(ON) limit is reached, the MOSFET will be unable to turn on any further, and the output voltage will start to fall. When the VTT output voltage falls to approximately 700mV, the LDO controller is latched off, setting output voltage to 0V. Power must be cycled to reset the latch. One of the advantages of using the SC1112 to drive an external MOSFET is that the bandgap reference and control circuitry do not need to be located right next to the power device, thus a very accurate output voltage can be obtained since heating effects will be minimal. To prevent false latching due to capacitor inrush currents or low supply rails, the current limit latch is initially disabled. It is enabled once the short circuit delay time has elapsed. Timing diagram on pages 4 to 5 will show a detailed operation of the Short Circuit protection circuitry. To be most effective, the MOSFET RDS(ON) should not be selected artificially low. The MOSFET should be chosen so that at maximum required current, it is almost fully turned on. If, for example, a supply of 1.5V at 4A is required from a 3.3V ± 5% rail, the maximum allowable RDS(ON) would be: R DS ( ON )( MAX ) = (0 . 95 • 3 . 3 − 1 . 5 • 1 . 025 ) ≈ 4 The 0.1µF bypass capacitor should be located close to the +5VSTBY supply pin, and connected directly to the ground plane. The ground pin of the device should also be connected directly to the ground plane. The sense or adjust pin does not need to be close to the output voltage plane, but should be routed to avoid noisy traces if at all possible. Power dissipation within the device is practically negligible, requiring no special consideration during layout. 400 m Ω To allow for temperature effects 200mΩ would be a suitable room temperature maximum, allowing a peak short circuit current of approximately 15A for a short time before shutdown. Capacitor Selection Output Capacitors: Low ESR aluminum electrolytic or tantalum capacitors are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Input Capacitors: Placement of low ESR aluminum electrolytic or tantalum capacitors at the input to the MOSFET (VTTIN) will help to hold up the power supply during fast load changes, thus improving overall transient response. The +5VSTBY supply should be bypassed with a 10µF ceramic capacitor.  2006 Semtech Corp. 18 www.semtech.com SC1112 POWER MANAGEMENT Evaluation Board Gerbers Board Layout Assembly Top Board Layout Assembly Bottom Board Layout Top Board Layout Bottom  2006 Semtech Corp. 19 www.semtech.com  2006 Semtech Corp. 20 J13 ADJ ADJ J16 J17 GND GND C12 + ** ADJ = 1.2*(1+RA/RB) 330uF J11 ADJ C6 + 330uF C13 0.1uF C7 0.1uF RB ** RA ** Q2 IRFR120N 100k 22nF J15 JP1 * 2 2 1 1 AGP SELECT Signal J14 VTT SELECT Signal R3 R2 100k C5 J6 POWER GOOD VTT JP2 * R1 1k U1 CAP- C11 ADJSEN ADJGATE AGPSEL VTTSEL DELAY 0.1uF CAP+ FC AGPSEN AGPGATE VTTSEN VTTGATE VTTIN GND SC1112CS PWRGD 5VSTBY 9 10 11 12 13 14 15 16 * JP2 = SHORT, AGP = 1.5 V * JP2 = OPEN, AGP = 3.3 V * JP1 = SHORT, VTT = 1.25 V * JP1 = OPEN, VTT = 1.5 V 8 7 6 5 4 3 2 1 C3 0.1uF 1uF C10 C17 0.1uF + C16 330uF Q3 IRFR120N + C14 330uF + C19 330uF + C2 + C18 330uF 330uF + C8 330uF C15 0.1uF C9 0.1uF Q1 IRFR120N C4 0.1uF AGP VTT +3.3V +5VSTBY C1 10uF VTT VTT GND GND +3.3V +3.3V GND +5VSTBY AGP J19 J21 GND J20 GND AGP J18 J12 GND J10 GND J9 J8 J7 J5 J4 J3 J2 J1 SC1112 POWER MANAGEMENT Evaluation Board Schematic www.semtech.com SC1112 POWER MANAGEMENT Evaluation Board Bill of Materials Item Qty. Reference 1 1 C1 10uF 1206 2 8 C2,C6,C8,C12,C14,C16,C18,C19 330uF CPCYL/D.2.75/LS.100/.031 3 8 C3,C4,C7,C9,C11,C13,C15,C17 0.1uF 0805 4 1 C5 22nF 0805 5 1 C 10 1uF 0805 6 2 JP1,JP2 TP2 VIA/2P 7 1 J1 +5VSTBY E D 5052 8 9 J2,J5,J7,J10,J12,J16,J17,J20,J21 GND E D 5052 9 2 J3,J4 +3.3V E D 5052 10 1 J6 Power Good E D 5052 11 2 J8,J9 VTT E D 5052 12 2 J11,J12 AD J E D 5052 13 1 J1 4 VTT SELECT Signal E D 5052 14 1 J1 5 AGP SELECT Signal E D 5052 15 2 J18,J19 AGP E D 5052 16 3 Q1,Q2,Q3 IRFR120N DPAKFET 17 3 R1,RA,RB 1k 0805 18 2 R2,R3 100k 0805 19 1 U1 SC1112STRT SO-16  2006 Semtech Corp. Part 21 Foot Print www.semtech.com SC1112 POWER MANAGEMENT Outline Drawing - TSSOP-16 A DIMENSIONS MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX D e N A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc 2X E/2 E1 E PIN 1 INDICATOR 1 2 3 ccc C 2X N/2 TIPS e/2 B 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 16 0° 8° 0.10 0.10 0.20 D aaa C SEATING PLANE .047 .002 .006 .031 .042 .007 .012 .003 .007 .192 .196 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 16 0° 8° .004 .004 .008 A2 A C H A1 bxN bbb C A-B D c GAGE PLANE 0.25 SIDE VIEW SEE DETAIL L (L1) DETAIL A 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB. Land Pattern - TSSOP-16 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20 P NOTES: 1.  2006 Semtech Corp. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 22 www.semtech.com SC1112 POWER MANAGEMENT Outline Drawing - SO-16 A D e N 2X E/2 E1 E ccc C 1 2 3 e/2 2X N/2 TIPS B D DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX DIM .053 .069 .010 .004 .065 .049 .020 .012 .007 .010 .386 .390 .394 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 16 0° 8° .004 .010 .008 A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc 1.75 1.35 0.25 0.10 1.65 1.25 0.31 0.51 0.25 0.17 9.80 9.90 10.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 16 0° 8° 0.10 0.25 0.20 aaa C A2 A SEATING PLANE C h A1 bxN bbb h H C A-B D c GAGE PLANE 0.25 SIDE VIEW SEE DETAIL L (L1) A DETAIL 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AC. Minimum Land Pattern - SO-16 X DIM (C) G Z Y C G P X Y Z DIMENSIONS INCHES MILLIMETERS (.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 304A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804  2006 Semtech Corp. 23 www.semtech.com