SC1159SWTRT

SC1159 Programmable Synchronous DC/DC Hysteretic Controller with VRM 8.5 VID Range POWER MANAGEMENT Description Features The SC1159 is a synchronous-buck switch-mode controller designed for use in single ended power supply applications where efficiency is the primary concern. The controller is a hysteretic type, with a user selectable hysteresis. The SC1159 is ideal for implementing DC/DC converters needed to power advanced microprocessors such as Pentium® llI and Athlon®, in both single and multiple processor configurations. Inhibit, under-voltage lockout and soft-start functions are included for controlled power-up. ‹ ‹ ‹ ‹ ‹ ‹ Programmable hysteresis 5 bit DAC programmable output (1.050V-1.825V) On-chip power good and OVP functions Designed to meet latest Intel specifications Up to 95% efficiency VIDs pulled up to +3.3V Applications ‹ ‹ ‹ ‹ ‹ SC1159 features include an integrated 5 bit D/A converter, temperature compensated voltage reference, current limit comparator, over-current protection, and an adaptive deadtime circuit to prevent shoot-through of the power MOSFET during switching transitions. Power good signaling, logic compatible shutdown, and over-voltage protection are also provided. The integrated D/A converter provides programmability of output voltage from 1.050V to 1.825V in 25mV increments. Server Systems and Workstations Pentium® III Core Supplies AMD Athlon® Core Supplies Multiple Microprocessor Supplies Voltage Regulator Modules The SC1159 high side driver can be configured as either a ground-referenced or as a floating bootstrap driver. The high and low side MOSFET drivers have a peak current rating of 2 amps. Typical Application Circuit +5V R1 * R3 * 1 IOUT R10 1k R9 10k U1 SC1159CSW PWRGD PWRGD 28 "POWER GOOD" R2 1k 2 R4 1k DROOP VID0 OCP VID1 VHYST VID2 C6 0.1 27 INHIB 3 4 R5 * 5 C1 0.1 R6 20k C2 0.001 6 7 8 C3 0.1 9 +5V 10 C4 0.01 11 12 13 VREFB VSENSE VID3 VID25 AGND INHIBIT SOFTST IOUTLO N/C LOSENSE LODRV HISENSE LOHIB BOOTLO DRVGND LOWDR HIGHDR BOOT 26 "INHIBIT" 24 L1 0.5uH + 23 Cin HF 22 DRV VIN12V Vin +5V/12V _ C8 0.033 20 19 Q1 FDB6035AL 18 R12 1.0 17 L2 1.0uH 16 C9 1.0 15 + Q2 FDB7030BL R14 1.6 C5 Cin Bulk 21 +12V 14 C7 0.1 R11 1k 25 Cout Bulk Cout HF 1.05 to 1.825V C10 _ R8 10k Revision: December 9, 2003 R7 * *) for the values see specific application circuit somewhere else in the datasheet 1 www.semtech.com SC1159 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units VINMAX -0.3 to 14 V BOOT to DRVGND -0.3 to 25 V BOOT to BOOTLO -0.3 to 15 V Digital Inputs -0.3 to 7.3 V ±0.5 V LOHIB to AGND -0.3 to 14 V LOSENSE to AGND -0.3 to 14 V IOTLO to AGND -0.3 to 14 V HISENSE to AGND -0.3 to 14 V VSENSE to AGND -0.3 to 5 V VIN12V AGND to DRVGND Continuous Power Dissipation, TA = 25°C PD 1.2 W Continuous Power Dissipation, TC = 25°C PD 6.25 W Operating Junction Temperature Range TJ 0 to +125 °C Lead Temperature (Soldering) 10 Sec. TLEAD 300 °C Storage Temperature TSTG -65 to 150 °C DC Electrical Characteristics Unless specified: 0 < TJ < 125°C, VIN = 12V Parameter Symbol Supply Voltage Range VIN12V Supply Current (Quiescent) High Side Driver Supply Current (Quiescent) © 2003 Semtech Corp. IINq IBOOTq Conditions Min Typ Max Units 11.4 12 13 V INH = 5V, Vin above UVLO threshold during start-up, fsw = 200 kHz, BOOTLO = 0V, C D H = C D L = 50pF 15 mA INH = OV or Vin below UVLO threshold during start-up, BOOT = 13V, BOOTLO = 0V 2 mA INH = 5V, VIN above UVLO threshold during start-up, fsw = 200kHz, BOOT = 13V, BOOTLO = 0V, C D H = 50pF 5 mA 2 www.semtech.com SC1159 POWER MANAGEMENT DC Electrical Characteristics (Cont) Unless specified: 0 < TJ < 125°C, VIN = 12V Parameter Symbols Conditions Min 11.4V < VIN12V< 12.6V, over full VID range (see Output Voltage Table) -1.2 Typ Max Units 1.2 % Reference/Voltage Identification Reference Voltage Accuracy VREF VID0 - VID25mV High Threshold Voltage VTH(H) VID0 - VID25mV Low Threshold Voltage VTH(L) 2.25 V 1 V 88 %VREF Pow er Good Undervoltage Threshold Output Saturation Voltage Hysteresis VTH(PWRGD) VSAT 82 IO = 5mA VHYS(PWRGD) 0.5 V 10 mV Over Voltage Protection OVP Trip Point Hysteresis (1) VOVP 12 VHYS(OVP) 15 20 10 %VOUT mV Soft Start Charge Current Discharge Current ICHG Idischg VSS = 0.5V, resistance from VREFB pin to AGND = 20kΩ, VREFB = 1.3V Note: ICHG = (IVREFB / 5) 10.4 V(SS) = 1V 13 15.6 1 μA mA Inhibit Comparator Start Threshold Vstart(NH) 1 2.0 2.4 V Start Threshold VstartUVLO 9.25 10.25 11.25 V Hysteresis VhysUVLO 1.8 2.1 2.4 V 5 mV VIN 12V UVLO Hysteretic Comparator Input Offset Voltage VosHYSCMP Input Bias Current IbiasHYSCMP 1 uA Hysteresis Accuracy VHYS ACC 7 mV Hysteresis Setting VHYS SET 60 mV © 2003 Semtech Corp. VDROOP pin grounded 3 www.semtech.com SC1159 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Unless specified: 0 < TJ < 125°C, VIN = 12V Parameter Symbols Conditions Min Typ Max Units 8 mV 0.11 V 100 nA Droop Compensation Initial Accuracy VDROOP ACC VDROOP = 50 mV Overcurrent Protection OCP Trip Point Input Bias Current VOCP 0.09 0.1 IbiasOCP High-Side VDS Sensing Gain Initial Accuracy IOUT Source IOUT Sink Current VIOUT Voltage Swing 2 VIOUT AC C VHISENSE = 12V, VIOUTLO = 11.9V 6 mV VIOUT = 0.5V, VHISENSE = 12V, VIOUTLO = 11.5V 500 IsinkIOUT VIOUT =0.05V, VHISENSE = 12V, VIOUTLO = 12V 38 VIOUT(11) VHISENSE = 11V, RIOUT = 10K Ω 0 3.75 V VIOUT(4.5V) VHISENSE = 4.5V, RIOUT = 10k Ω 0 2.0 V VIOUT(3V) VHISENSE = 3V, RIOUT = 10k Ω 0 1.0 V IsourceIOUT LOSENSE High Level Input Voltage VihLOSENSE VHISENSE = 4.5V (Note 1) LOSENSE Low Level Input Voltage VilLOSENSE VHISENSE = 4.5V (Note 1) Sample/Hold Resistance V/V RS/H (Note 1) μA 50 μA 2.85 50 V 65 1.8 V 80 Ω Buffered Reference VREFB Load Regulation VldregREFB 10μA < IREFB < 500μA 2 mV Deadtime Circuit (1) LOHIB High Level Voltage VihLOHIB LOHIB Low Level Input Voltage VilLOHIB LOWDR High Level Input Voltage VihLOWDR LOWDR Low Level Input Voltage VilLOWDR 2 V 1.0 2 V V 1.0 V 9 V Drive Regulator DRV Voltage VDRV Load Regulation VldregDRV Short Circuit Current IshortDRV © 2003 Semtech Corp. 11.4 < VIN12V < 12.6V, IDRV = 50mA 7 1mA < IDRV < 50mA 100 100 4 mV mA www.semtech.com SC1159 POWER MANAGEMENT DC Electrical Characteristics (Cont.) Unless specified: 0 < TJ < 125°C, VIN = 12V Parameter Symbol Conditions Min Typ Max Units High-Side Output Driver Peak Output Current Equivalent Output Resistance IsrcHIGHDR duty cycle < 2%, tpw < 100us, TJ = 125°C IsinkHIGHDR VBOOT - VBOOTLO = 6.5V, VHIGHDR = 1.5V (src), or VHIGHDR = 5V (sink) RsrcHIGHDR TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 6V RsinkHIGHDR TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.5V IsrcLOWDR duty cycle < 2%, tpw < 100us, TJ = 125°C VDRV = 6.5V, VLOWDR = 1.5V (src), or VLOWDR = 5V (sink) 2 A 45 Ω 5 Low -Side Output Driver Peak Output Current IsinkLOWDR Equivalent Output Resistance RsrcLOWDR TJ = 125°C VDRV = 6.5V, VLOWDR = 6V RsinkLOWDR TJ = 125°C VDRV = 6.5V, VLOWDR = 0.5V 2 A 45 Ω 5 AC Electrical Characteristics (Note 1) Parameter Symbol Conditions Min Typ Max Units 150 250 ns Hysteretic Comparators Propagation Delay Time from VSENSE to HIGHDR or LOWDR (excluding deadtime) tHCPROP 10mV overdrive, 1.3V ≤ Vref ≤ 1.8V HIGHDR rise/fall time trHIGHDR trHIGHDR CI = 9nF, VBOOT = 6.5v, VBOOTLO = grounded, TJ =125°C 60 ns LOWDR rise/falltime trLOWDR tfLOWDR CI = 9nF, VDRV = 6.5V, TJ =125°C 60 ns Output Drivers Overcurrent Protection Comparator Propagation Delay Time tOVPROP Deglitch Time (Includes comparator propagation delay time) tOVDGL © 2003 Semtech Corp. 1 2 5 μs 5 μs www.semtech.com SC1159 POWER MANAGEMENT AC Electrical Characteristics (Cont.) (Note 1) Parameter Symbols Conditions Min Typ Max Units Overvoltage Protection Comparator Propagation Delay Time tOVPROP Deglitch Time (Includes comparator protection delay time) tOVDGL 1 1 μs 3 μs VHISENSE = 12V, VIOUTLO pulsed from 12V to 11.9V, 100ns rise and fall times 2 μs VHISENSE = 4.5V, VIOUTLO pulsed from 4.5V to 4.4V, 100ns rise and fall times 3 μs VHISENSE = 3V, VIOUTLO pulsed from 3.0V to 2.9V, 100ns rise and fall times 3 μs High-Side Vds Sensing Response Time tVDSRESP Short Circuit Protection Rising Edge Delay tVDSRED LOSENSE grounded 300 500 ns Sample/Hold Switch turn-on/turn-off Delay tSWXDLY 3V < VHISENSE < 11V VLOSENSE = VHISENSE 30 100 ns Pow er Good Comparator Propagation Delay tPWRGD 1 μs Softstart Comparator Propagation Delay tSLST overdrive = 10mV tNOL CLOWDR = 9nF, 10% threshold on LOWDR 560 900 ns 100 ns 400 ns Deadtime Driver Non-overlap Time 30 LODRV Propagation Delay TLODRVDLY Note: (1) Guaranteed, but not tested. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required. © 2003 Semtech Corp. 6 www.semtech.com SC1159 POWER MANAGEMENT Test Circuit Timing Diagram Simplified Block Diagram © 2003 Semtech Corp. 7 www.semtech.com SC1159 POWER MANAGEMENT Pin Configuration Ordering Information Device TOP VIEW (1) SC1159SWTR IOUT 1 28 PWRGD DROOP 2 27 VID0 OCP 3 26 VID1 VHYST 4 25 VID2 VREFB 5 24 VID3 VSENSE 6 23 VID25 AGND 7 22 INHIBIT SOFTST 8 21 IOUTLO N/C 9 20 LOSENSE LODRV 10 19 HISENSE LOHIB 11 18 BOOTLO DRVGND 12 17 HIGHDR LOWDR 13 16 BOOT DRV 14 15 VIN12V P ackag e Temp Range (TJ) SO-28 0° to 125°C SC1159EVB Evaluation Board Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices. (28 Pin SOIC) Pin Descriptions Pin # Pin Name 1 IOUT Current Out. The output voltage on this pin is proportional to the load current as measured across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD. DROOP Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a function of load current. The voltage is set by a resistor divider between IOUT and AGND. 2 Pin Function 3 OCP 4 VHYST Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor divider between VREFB and AGND. 5 VREFB Buffered Reference Voltage (from VID circuitry). 6 VSENSE 7 AGND 8 SOFTST 9 NC 10 LODRV Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is grounded, this pin can be used to control LOWDR. 11 LOHIB Low Side Inhibit. This pin is used to eliminate shoot-thru current. 12 DRVGND 13 LOWDR © 2003 Semtech Corp. Over Current Protection. This pin is used to set the trip point for over current protection by a resistor divider between IOUT and AGND. Output Voltage Sense. Small Signal Analog and Digital Ground. Soft Start. Connecting a capacitor from this pin to AGND sets the time delay. Not connected. Power Ground. Insure output capacitor ground is connected to this pin. Low Side Driver Output. Connect to gate of low side MOSFET. 8 www.semtech.com SC1159 POWER MANAGEMENT Pin Descriptions (Cont.) Pin # Pin Name 14 DRV Drive Regulator for the MOSFET Drivers. 15 VIN12V 12V Supply. Connect to 12V power rail. 16 BOOT Bootstrap. This pin is used to generate a floating drive for the high side FET driver. 17 HIGHDR High Side Driver Output. Connect to gate of high side MOSFET. 18 BOOTLO Bootstrap Low. In desktop applications, this pin connect to DRVGND. 19 HISENSE High Current Sense. Connected to the drain of the high side FET,or the input side of a current sense resistor between the input and the high side FET. 20 LOSENSE Low Current Sense. Connected to the source of the high side FET, or the FET side of a current sense resistor between the input and the high side FET. 21 IOUTLO This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin when the high side FET is on. 22 INHIBIT Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V through a pull-up resistor. 23 VID25 Programming Input . 24 VID3 Programming Input. 25 VID2 Programming Input. 26 VID1 Programming Input. 27 VID0 Programming Input . 28 PWRGD © 2003 Semtech Corp. Pin Function Power Good. This open collector logic output is high if the output voltage is within 15% of the set point. 9 www.semtech.com © 2003 Semtech Corp. 10 - 100mV VSENSE + + DEGLITCH OCP - DEGLITCH 0.85VREF + 1.15VREF - PWRGD Q Vcc AGND 10V - + UVLO S R + INHIBIT 2V - INH BANDGAP FAULT 50uA IOUT - + G=2 + + - - - + FILTER FILTER - + - + - + - + VHYST VREFB 0.85VREF HIGHDR LOSENSE DROOP VSENSE VREF VID0 VID2 VID25 VID1 VID3 VID DAC + 1.15VREF SHUTDOWN HISENSE IOUTLO + - I(VREFB) / 5 VREF RISING EDGE DELAY LOHIB ANALOG BIAS SOFTST FILTER PREREG LODRV LOWDR REGULATOR DRIVE Vcc DRVGND LOWDR BOOTLO HIGHDR BOOT DRV VIN12V SC1159 POWER MANAGEMENT Block Diagram www.semtech.com SC1159 POWER MANAGEMENT Output Voltage Table 0 = GND, 1 = OPEN VID25mV (2) VID3 (1) VID2 (1) VID1 (1) VIDO (1) VDC (V) 0 0 1 0 0 1.05 1 0 1 0 0 1.075 0 0 0 1 1 1.10 1 0 0 1 1 1.125 0 0 0 1 0 1.15 1 0 0 1 0 1.175 0 0 0 0 1 1.20 1 0 0 0 1 1.225 0 0 0 0 0 1.25 1 0 0 0 0 1.275 0 1 1 1 1 1.30 1 1 1 1 1 1.325 0 1 1 1 0 1.35 1 1 1 1 0 1.375 0 1 1 0 1 1.40 1 1 1 0 1 1.425 0 1 1 0 0 1.45 1 1 1 0 0 1.475 0 1 0 1 1 1.50 1 1 0 1 1 1.525 0 1 0 1 0 1.55 1 1 0 1 0 1.575 0 1 0 0 1 1.60 1 1 0 0 1 1.625 0 1 0 0 0 1.65 1 1 0 0 0 1.675 0 0 1 1 1 1.70 1 0 1 1 1 1.725 0 0 1 1 0 1.75 1 0 1 1 0 1.775 0 0 1 0 1 1.80 1 0 1 0 1 1.825 NOTE: (1) VID (3:0) correspond to legacy VRM 8.4 voltage levels for 1.3V - 1.8V. (2) VID 25mV provides a 25mV increment. © 2003 Semtech Corp. 11 www.semtech.com SC1159 POWER MANAGEMENT Applications Information - Functional Description Reference/Voltage Identification The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID pins are TTL compatable inputs to the VID selection network. They are internally pulled up to +3.3V generated from the +12V supply by a resistor divider, and provide programmability of output voltage from 1.050V to 1.825V in 25mV increments. Refer to the Output Voltage Table for the VID code settings. The output voltage of the VID network, VREF is within 1% of the nominal setting over the full input and output voltage range and junction temperature range. The output of the reference/VID network is indirectly brought out through a buffer to the REFB pin. The voltage on this pin will be within 3mV of VREF. It is not recommended to drive loads with REFB other than setting the hysteresis of the hysteretic comparator, because the current drawn from REFB sets the charging current for the soft start capacitor. Refer to the soft start section for additional information. Hysteretic Comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis of tne comparator will be equal to twice the voltage difference between REFB and HYST, and has a maximum value of 60mV. The maximum propagation delay from the comparator inputs to the driver outputs is 250ns. Low Side Driver The low side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink. The bias for the low side driver is provided internally from VDRV. High Side Driver The high side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink current. It can be configured either as a ground referenced driver or as a floating bootstrap driver. When © 2003 Semtech Corp. configured as a floating driver, the bias voltage to the driver is developed from the DRV regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 25V. The driver can be referenced to ground by connecting BOOTLO to PGND, and connecting +12V to the BOOT pin. Deadtime Control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the FET drivers. The high side driver is not allowed to turn on until the gate drive voltage to the low-side FET is below 2 volts, and the low side driver is not allowed to turn on until the voltage at the junction of the 2 FETs (VPHASE) is below 2 volts. An internal low-pass filter with an 11MHz pole is located between the output of the low-side driver (DL) and the input of the deadtime circuit that controls the high-side driver, to filter out noise that could appear on DL when the high-side driver turns on. Current Sensing Current sensing is achieved by sampling and holding the voltage across the high side FET while it is turned on. The sampling network consists of an internal 50Ω switch and an external 0.033μF hold capacitor. Internal logic controls the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until VPHASE transitions high and turns off when the input to the high side driver goes low. Thus sampling will occur only when the high side FET is conducting current. The voltage at the IO pin equals 2 times the sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high side FET and the voltage across the sense resistor can be sampled by the current sensing circuit. Droop Compensation The droop compensation network reduces the load transient overshoot/undershoot at VOUT, relative to VREF. VOUT is programmed to a voltage greater than VREF equal to VREF • (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load 12 www.semtech.com SC1159 POWER MANAGEMENT Applications Information - Functional Description (Cont.) current transient. The overshoot during a high to low load current transient is reduced by subtracting the voltage that is on the DROOP pin from VREF. The voltage on the IO pin is divided down with an external resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VOUT is regulated to: VOUT = VREF • (1+R7/R8) - IOUT • R2/(R1+R2). Inhibit The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INH is low, the output drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the controller is in a low IQ state. When INH goes high, the short across the soft start capacitor is removed, the soft start current source is enabled, and normal converter operation begins. When the system logic supply is connected to INH, it controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the INH circuit; thus the +12V supply and the system logic supply (either +5V or 3.3V) must be above UVLO thresholds before the controller is allowed to start up. VIN The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start threshold during power-up. While the controller is disabled, the output drivers will be low, the soft start capacitor will be shorted and the soft start current is disabled and the controller will be in a low IQ state. When VIN exceeds the start threshold, the short across the soft start capacitor is removed, the soft start current source is enabled and normal converter operation begins. There is a 2V hysteresis in the undervoltage lockout circuit for noise immunity. Soft Start The soft start circuit controls the rate at which VOUT powers up. A capacitor is connected between SS and AGND and is charged by an internal current source. The value of the current source is proportional to the reference voltage so the charging rate of CSS is also proportional to the reference voltage. By making the charging current © 2003 Semtech Corp. proportional to VREF, the power-up time for VOUT will be independent of VREF. Thus, CSS can remain the same value for all VID settings. The soft start charging current is determined by the following equation: ISS = IREFB/5. Where IREFB is the current flowing out of the REFB pin. It is recommended that no additional loads be connected to REFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine the soft start charging current. The maximum current that can be sourced by REFB is 500μA. Power Good The power good circuit monitors for an undervoltage condition on VOUT. If VSENSE is 15% (nominal) below VREF, then the power good pin is pulled low. The PWRGD pin is an open drain output. Overvoltage Protection The overvoltage protection circuit monitors VOUT for an overvoltage condition. If VSENSE is 15% above VREF, than a fault latch is set and both output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. Overcurrent Protection The overcurrent protection circuit monitors the current through the high side FET. The overcurrent threshold is adjustable with an external resistor divider between IO and AGND, with the divider voltage connected to the OCP pin. If the voltage on the OCP pin exceeds 100mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high side FET against a short-toground fault on the terminal common to both power FETs (VPHASE). Drive Regulator The drive regulator provides drive voltage to the low side driver, and to the high side driver when the high side driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA. 13 www.semtech.com © 2003 Semtech Corp. +5V R4 1k 0.001 0.001 R2 1k C2 R3 4.3k C1 R1 2k 14 C7 0.01 R7 100 R6 20k C5 0.001 * R5 R8 10k C6 0.1 R9 150 C4 0.1 C3 0.1 C8 2.2 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C59 1.0 DRV LOWDR DRVGND LOHIB LODRV N/C SOFTST AGND VSENSE VREFB VHYST OCP DROOP IOUT U1 SC1159 VIN12V BOOT HIGHDR BOOTLO HISENSE LOSENSE IOUTLO INHIBIT VID25 VID3 VID2 VID1 VID0 PWRGD J4 J3 J2 J1 J0 +12V C14 2.2 15 16 17 18 19 20 21 22 23 24 25 26 27 28 R22 1.6 C13 1.0 R11 1k R18 NS R17 NS Q4 FDB7030BL R23 1.6 Q2 R21 FDB6035AL 1.0 R13 0 R12 1k INHIB PWRGD 0.0022 2pl. R24,25 3.3 2pl. C33,34 R19 0 C15-23 1.0 "INHIBIT" "POWER GOOD" R26,27 3.3 2pl. C35,36 0.0022 2pl. C12 22.0 R14,15,16 0 C10 0.1 C9 0.1 40A+ Evaluation Board Q3 FDB7030BL Q1 R20 FDB6035AL 1.0 D1 MBRA130L C11 0.033 R10 10k +5V D2(opt) MBRB2515L L2 1.0uH@40A C37-46 1500uF 6.3V 0.5uH L1 C24-32 820uF 16V +12V GND/IN _ C47-58 10.0 Vin +5V/12V + POS/IN GND +12V GND/OUT _ Vout + POS/OUT SC1159 POWER MANAGEMENT Application Circuit www.semtech.com SC1159 POWER MANAGEMENT Typical Characteristics VIN = 5V; IOUT = 0A to 40A “Droop” & “Offset” Disabled 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 3% 2% Regulation Efficiency VOUT = 1.8V 1% 0% -1% -2% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 Current, A 20 25 30 35 40 25 30 35 40 25 30 35 40 Current, A 3% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 2% Regulation Efficiency VOUT = 1.5V 1% 0% -1% -2% -3% 0 5 10 15 20 25 30 35 0 40 5 10 15 20 Current, A Current, A 3% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 2% Regulation Efficiency VOUT = 1.1V 1% 0% -1% -2% -3% 0 5 10 15 20 25 30 35 0 40 10 15 20 Current, A Current, A © 2003 Semtech Corp. 5 15 www.semtech.com SC1159 POWER MANAGEMENT Typical Characteristics (Cont.) VIN = 12V; IOUT = 0A to 40A “Droop” & “Offset” Disabled 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 3% 2% Regulation Efficiency VOUT = 1.8V 1% 0% -1% -2% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 Current, A 20 25 30 35 40 25 30 35 40 25 30 35 40 Current, A 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 3% 2% Regulation Efficiency VOUT = 1.5V 1% 0% -1% -2% -3% 0 5 10 15 20 25 30 35 40 0 5 10 15 Current, A 20 Current, A 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 3% 2% Regulation Efficiency VOUT = 1.1V 1% 0% -1% -2% -3% 0 5 10 15 20 25 30 35 40 0 Current, A © 2003 Semtech Corp. 5 10 15 20 Current, A 16 www.semtech.com SC1159 POWER MANAGEMENT Evaluation Board Artwork Top Layer Bottom Layer Mid Layer © 2003 Semtech Corp. 17 www.semtech.com SC1159 POWER MANAGEMENT Evaluation Board Artwork (Cont.) Top Overlay Bottom Overlay © 2003 Semtech Corp. 18 www.semtech.com SC1159 POWER MANAGEMENT Materials List Quantity Reference Part/Description 3 C1,C2,C5 0.001μF 6 C3,C4,C6,C7,C9,C10 1 Vendor TDK, Murata, Taiyo-Yuden 0.1μF any C11 0.033μF any 1 C 12 22μF any 11 C13, C15-C23, C59 1μF any 2 C8,C14 2.2μF any 9 C 24 - C 32 820μF, 16V 10 C 37 - C 46 1500μF, 6.3V, thru hole 12 C 47 - C 58 10μF any 4 C 33 - C 36 .0022μF any 1 D1 1 SANYO P/N: 16MV820AX SANYO P/N: 6R3MV1500AX MBRA130L. Schottky ON Semi D2 (optional) MBRB2515L ON Semi 1 L1 0.5uH, Toroid Micrometals P/N: T51-26C, 18 AWG 1 L2 1.0uH, Toroid Magnetics, #77310, 3ts, 4 X 20 AWG 2 Q1,Q2 D2Pak, MOSFET Fairchild P/N: FDB6035AL 2 Q3,Q4 D2Pak, MOSFET Fairchild P/N: FDB7030BL 1 R1 2k any 4 R2,R4,R11,R12 1k any 1 R3 4.3k any 1 R6 20k any 1 R5 *150 any 1 R7 100 any 2 R8,R10 10k any 1 R9 150 any 2 R20,R21 1 any 2 R22,R23 1.6 any 4 R24,R25,R26,R27 3.3 any 1 U1 © 2003 Semtech Corp. SC1159CSW.TR 19 Semtech Corp. 805-498-2111 www.semtech.com SC1159 POWER MANAGEMENT Layout Guidelines (See pg. 1) 1. Locate R8 and C2 close to pins 6 and 7. 2. Locate C1 close to pins 5 and 7. 3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND. 4. The bypass capacitors C5 and C10 should be placed close to the IC and referenced to DRVGND. 5. Locate bootstrap capacitor C13 close to the IC. 6. Place bypass capacitor close to Drain of the top FET and Source of the bottom FET to be effective. 7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise. 8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin. 9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass. 10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower Vout settings, it needs to be placed next to the aforementioned FET in very close proximity. 11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be achieved by connecting the AGND to the ground side of the bulk output capacitors. 12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple vias. 13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the chip with the cathode connected to BOOTLO and anode connected to DRVGND. Outline Drawing - SO-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2003 Semtech Corp. 20 www.semtech.com