SC2446
Dual-Phase Single or Two Output
Synchronous Step-Down Controllers
POWER MANAGEMENT
Description
Features
2-Phase synchronous continuous conduction mode
The SC2446 is a high-frequency dual synchronous stepdown switching power supply controller. It provides outof-phase high-current output gate drives to all N-channel MOSFET power stages. The SC2446 operates in synchronous continuous-conduction mode. Both phases are
capable of maintaining regulation with sourcing or sinking load currents, making the SC2446 suitable for generating both VDDQ and the tracking VTT for DDR applications.
The SC2446 employs fixed frequency peak current-mode
control for the ease of frequency compensation and fast
transient response.
The dual-phase step-down controllers of the SC2446 can
be configured to provide two individually controlled and
regulated outputs or a single output with shared current
in each phase. The Step-down controllers operate from an
input of at least 4.7V and are capable of regulating outputs as low as 0.5V
The step-down controllers in the SC2446 have the provision to sense a synthesized MOSFET RDS(ON) for current-mode control. This sensing scheme (U.S. patent
6,441,597) eliminates the need of the current-sense resistor and is more noise-immune than direct sensing of
the high-side or the low-side MOSFET voltage. Precise current-sensing with sense resistor is optional.
Individual soft-start and overload shutdown timer is included in each step-down controller. The SC2446 implements hiccup overload protection. In two-phase singleoutput configuration, the master timer controls the softstart and overload shutdown functions of both controllers.
for high efficiency step-down converters
Out of phase operation for low input current ripples
Output source and sink currents
Fixed frequency peak current-mode control
75mV/-110mV maximum current sense voltage
Synthesized MOSFET RDS(ON) current-sensing for
low-cost applications
Optional resistor current-sensing for precise currentlimit
Dual outputs or 2-phase single output operation
Excellent current sharing between individual phases
Wide input voltage range: 4.7V to 16V
Individual soft-start, overload shutdown and enable
Duty cycle up to 88%
0.5V feedback voltage for low-voltage outputs
External reference input for DDR applications
Buffered VDDQ/2 output
Programmable frequency up to 1MHz per phase
External synchronization
Industrial temperature range
28-lead TSSOP package
Applications
Telecommunication power supplies
DDR memory power supplies
Graphic power supplies
Servers and base stations
Typical Application Circuit
VIN
C92
D11
D12
PVCC
Q21
VO2
C99
R73
L11
C93
C95
CFILTER
+
R79
C96
R75
Q23
RCS-
VPN1
CS2+
CS1+
CS2-
CS1-
IN2-
IN1-
COMP2
REF
SYNC
C106
REF
VIN2
C97
R80
RCS-
R82
C102
C104
C105
R84
AGND
SYNC
C107
C100
+
R76
RCS+
COMP1
REFIN
VIN
C98
CFILTER
RFILTER
PGND
VPN2
VO1
L12
Q24
GDL1
RFILTER
C103
Q22
R74
C94
R78
C101
Revision: March 23, 2004
GDH1
GDL2
R81
Figure 1
BST1
GDH2
R77
RCS+
R83
BST2
Rosc
SS1/EN1
AVCC
SS2/EN2
REFOUT
R85
VIN
C108
U1
C109
SC2446
Dual Independant Outputs
1
U.S. Patent No. 6,441,597, www.semtech.com
SC2446
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum Ratings
Units
AVCC, PVCC
-0.3 to 20
V
VIN2
-0.3 to 20
V
High-Side Driver Supply Voltages
VBST1,VBST2
-0.3 to 32
V
IN1-, IN2- Voltages
VIN1-,VIN2-
-0.3 to AVCC+0.3
V
VREF ,VREFOUT
-0.3 to 6
V
VREFIN
-0.3 to AVCC+0.3
V
VCOMP1,VCOMP2
-0.3 to AVCC+0.3
V
VCS1+,VCS1-,VCS2+,VCS2-
-0.3 to AVCC+0.3
V
VSYNC
-0.3 to AVCC+0.3
V
VSS1,VSS2
-0.3 to 6
V
IGDH1, IGDH2, IGDL1, IGDL2
3
A
IVPN1, IVPN2
100
mA
Ambient Temperature Range
TA
-40 to 85
°C
Thermal Resistance Junction to Case (TSSOP-28)
θJC
13
°C/W
Thermal Resistance Junction to Ambient (TSSOP-28)
θJA
84
°C/W
Storage Temperature Range
TSTG
-60 to 150
°C
Lead Temperature (Soldering) 10 sec
TLEAD
260
°C
TJ
150
°C
Supply Voltage For Step-Down Controllers
Input Voltage For the Second Converter
REF, REFOUT Voltages
REFIN Voltage
COMP1, COMP2 Voltages
CS1+, CS1-, CS2+ and CS2- Voltages
SY NC Voltage
SS1/EN1 AND SS2/EN2 Voltages
Peak Gate Drive Currents
Peak VPN1 and VPN2 Output Currents
Maximum Junction Temperature
Electrical Characteristics
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
4.5
4.7
V
Undervoltage Lockout
AVCC Start Threshold
AVCCTH
AVCC Start Hysteresis
AVCCHYST
AVCC Operating Current
ICC
AVCC Quiescent Current in UVLO
AVCC Increasing
0.17
AVCC= 12V
12
AVCC = AVCCTH - 0.2V
1.7
V
16
mA
mA
Channel 1 Error Amplifier
Non-inverting Input Voltage
VIN1+
0.490
0.500
0.510
V
0.02
%/ V
1
±3
mV
-250
nA
AVCCTH < AVCC< 15V
Non-inverting Input Line Regulation
Input Offset Voltage
Inverting Input Bias Current
IIN1-
-100
Amplifier Transconductance
G M1
260
µΩ −1
Amplifier Open-Loop Gain
aOL1
65
dΒ
5
ΜΗz
2.2
V
Amplifier Unity Gain Bandwidth
Minimum COMP1 Switching Threshold
2004 Semtech Corp.
VCS1+ = VCS1- = 0
VSS1 Increasing
2
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SC2446
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Amplifier Output Sink Current
VIN1- = 1V, VCOMP1 = 2.5V
16
µA
Amplifier Output Source Current
VIN1- = 0, VCOMP1 = 2.5V
12
µA
Channel 2 Error Amplifier
Input Common-mode Voltage Range
(Note 1)
0
3
V
Inverting Input Voltage Range
(Note 1)
0
AVCC
V
1.5
±3
mV
Input Offset Voltage
Non-inverting Input Bias Current
IIN2+
-150
-380
nA
Inverting Input Bias Current
IIN2-
-100
-250
nA
Inverting Input Voltage for 2-Phase Single
Output Operation
2.5
V
Amplifier Transconductance
G M2
260
µΩ −1
Amplifier Open-Loop Gain
aOL2
65
dΒ
5
MHz
Amplifier Unity Gain Bandwidth
Minimum COMP2 Switching Threshold
VCS2+ = VCS2- = 0
VSS2 Increasing
2.2
V
Amplifier Output Sink Current
VCOMP2 = 2.5V
16
µA
Amplifier Output Source Current
VCOMP2 = 2.5V
12
µA
Oscillator
Channel Frequency
fCH1, fCH2
Synchronizing Frequency
450
(Note 1)
SY NC Input High Voltage
500
ISYNC
Channel Maximum Duty Cycle
DMAX1, DMAX2
Channel Minimum Duty Cycle
DMIN1, DMIN2
KHz
2.1fCH
KHz
1.5
V
SY NC Input Low Voltage
SY NC Input Current
550
VSYNC = 0.2V
VSYNC = 2V
0.5
V
1
100
µA
88
%
0
%
AVCC - 1
V
Current-limit Comparators
Input Common-Mode Range
0
Cycle-by-cycle Peak Current Limit
VILIM1+,
VILIM2+
VCS1- = VCS2- = 0.5V,
Sourcing Mode
60
75
90
mV
Valley Current Overload Shutdown
Threshold
VILIM1-, VILIM2-
VCS1- = VCS2- = 0.5V,
Sinking Mode
-85
-110
-130
mV
Positive Current-Sense Input Bias Current
ICS1+, ICS2+
VCS1+ = VCS1- = 0
VCS2- = VCS2- = 0
-0.7
-2
µA
Negative Current-Sense Input Bias
Current
ICS1-, ICS2-
VCS1+ = VCS1- = 0
VCS2+ = VCS2- = 0
-0.7
-2
µA
High-side Gate Drive Peak Source
Current
VBST1 ,VBST2 = 12V
1.5
A
High-side Gate Drive Peak Sink Current
VBST1 ,VBST2 = 12V
1
A
Gate Drivers
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SC2446
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Low-side Gate Drive Peak Source
Current
AVCC = PVCC =12V
1.5
A
Low-side Gate Drive Peak Sink Current
AVCC = PVCC =12V
1
A
Gate Drive Rise Time
CL = 2200pF
20
ns
Gate Drive Fall Time
CL = 2200pF
20
ns
Low-side Gate Drive to High-side Gate
Drive Non-overlapping Delay
CL = 0
90
ns
High-side Gate Drive to Low-side Gate
Drive Non-overlapping Delay
CL = 0
90
ns
Minimum On-Time
TA = 25°C
150
ns
2
µA
3.2
V
Soft-Start, Overload Latchoff and Enable
Soft-Start Charging Current
ISS1, ISS2
VSS1 = VSS2 = 1.5V
Overload Latchoff Enabling Soft-Start
Voltage
VSS1 and VSS2 Increasing
Overload Latchoff IN1- Threshold
VSS1 = 3.8V, VIN1-Decreasing
0.75VREF
V
Overload Latchoff IN2- Threshold
VSS2 = 3.8V, VIN2-Decreasing
0.72 X
VREFIN
V
1.4
µA
Soft-Start Discharge Current
ISS1(DIS),
ISS2(DIS)
VIN1-= 0.5VREF,
VIN2-= 0.5VREFIN ,
VSS1 = VSS2 = 3.8V
Overload Latchoff Recovery Soft-Start
Voltage
VSSRCV1,
VSSRCV2
VSS1 and VSS2 Decreasing
Gate Drive Disable SS/EN Voltage
0.3
0.5
0.7
0.9
Gate Drive Enable SS/EN Voltage
1.2
0.7
V
V
1.5
V
Channel 1 Virtual Phase Node Voltage
Output High Voltage
VVPN1H
IVPN1= -100µA, VBST1= 24V
Output Low Voltage
VVPN1L
IVPN1= 100µA, VBST1= 24V
VPVCC-0.05
V
20
mV
Output Sourcing Current
VBST1= 24V,
VVPN1= VPVCC - 0.2V
7
mA
Output Sinking Current
VBST1= 24V, VVPN1= 0.2V
7
mA
Channel 2 Virtual Phase Node Voltage
Output High Voltage
VVPN2H
IVPN2= -100µA, VBST2= 24V
Output Low Voltage
VVPN2L
IVPN2= 100µA, VBST2= 24V
VIN2 - 0.05
V
20
mV
Output Sourcing Current
VBST2= 24V,
VVPN2= VIN2 - 0.2V
7
mA
Output Sinking Current
VBST2= 24V, VVPN2= 0.2V
7
mA
External Reference Buffer
External Reference Input Voltage Range
Buffered Output Voltage
2004 Semtech Corp.
VREFIN
VREFOUT
0
VREFIN=1.25V, IREFOUT= -1mA
4
VREFIN -0.01
VREFIN
4
V
VREFIN +0.01
V
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SC2446
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Load Regulation
Conditions
Min
0 < IREFOUT < -5mA
Typ
Max
0.02
Units
%/mA
Internal 0.5V Reference Buffer
Output Voltage
VREF
Load Regulation
IREF= -1mA
490
0 < IREF < -5mA
500
0.05
510
mV
%/mA
Notes:
(1) Guaranteed by design not tested in production.
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Pin Configurations
Ordering Information
(TOP VIEW)
CS1+
CS1ROSC
IN1COMP1
SYNC
AGND
REF
REFOUT
REFIN
COMP2
IN2CS2CS2+
SS1/EN1
VPN1
BST1
GDH1
GDL1
PVCC
PGND
GDL2
GDH2
BST2
VPN2
VIN2
AVCC
SS2/EN2
Device
Package(1)
Temp. Range( TA)
SC2446ITSTRT(2)
TSSOP-28
-40 to 85°C
S C 2446E V B
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for TSSOP package.
(2) Lead free product.
(28-Pin TSSOP)
Figure 2
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SC2446
POWER MANAGEMENT
Pin Descriptions
TSSOP Package
Pin
Pin Name
1
CS1+
The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 1.
2
CS1-
The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. Normally
tied to the output of the converter.
3
ROSC
An external resistor connected from this pin to GND sets the oscillator frequency.
4
IN1-
5
COMP1
6
SY NC
Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above
1.5V or the ground. An external clock (frequency > frequency set with ROSC) at this pin
synchronizes the controllers.
7
AGND
Analog Signal Ground.
8
REF
9
REFOUT
10
REFIN
11
COMP2
12
IN2-
Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie an external resistive
divider between output2 and the ground for output voltage sensing. Tie to AVCC for two-phase
single output applications
13
CS2-
The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 2. Normally
tied to the output of the converter.
14
CS2+
The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 2
15
SS2/EN2
16
AVCC
Power Supply Voltage for the Analog Portion of the Controllers.
17
VIN2
This pin is tied to the voltage supplying the drain of the high side power MOSFET of converter
2. This pin is used only in "Combi" current sense.
18
VPN2
The Second Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current
sense only. This pin is left open when sensing current with a sense resistor at the converter
output.
19
BST2
Bootstrapped Supply for the High-side Gate Drive 2. Connect to a bootstrap capacitor and an
external diode as described in application information.
20
GDH2
Gate Drive Output for the High-side N-channel MOSFET of Output 2. Gate drive voltage
swings from ground to VBST2.
2004 Semtech Corp.
Pin Function
Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie an external resistive
divider between OUTPUT1 and the ground for output voltage sensing.
The Error Amplifier Output for Step-down Controller 1. This pin is used for loop
compensation.
Buffered Output of the Internal 0.5V Reference. The non-inverting input of the error amplifier
for the step-down converter 1 is internally connected to this pin .
Buffered output of the external voltage applied to Pin 10.
An external Reference voltage is applied to this pin.The non-inverting input of the error
amplifier for the step-down converter 2 is internally connected to this pin.
The Error Amplifier Output for Step-down Controller 2. This pin is used for loop
compensation.
An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off
time for step-down converter 2. Pulling this pin below 0.7V shuts off the gate drivers for the
second controller. Leave open for two-phase single output applications.
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SC2446
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name
21
GDL2
Gate Drive Output for the Low-side N-channel MOSFET of Output 2. Gate drive voltage
swings from ground to PVCC.
22
PGND
Ground Supply for All the Gate drivers.
23
PVCC
Power Supply Voltage for Low-side MOSFET Drivers.
24
GDL1
Gate Drive Output for the Low-side N-channel MOSFET of Output 1. Gate drive voltage
swings from ground to PVCC.
25
GDH1
Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage
swings from ground to VBST1.
26
BST1
Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an
external diode as described in application information.
27
VPN1
The First Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current
sense only. This pin is left open when sensing current with a sense resistor at the converter
output.
28
SS1/EN1
An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off
time for buck converter 1. Pulling this pin below 0.7V shuts off the gate drivers for the first
controller.
2004 Semtech Corp.
Pin Function
7
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SC2446
POWER MANAGEMENT
Block Diagram
SYNC
6
AVCC
16
CLK2
OSCILLATOR
ROSC
3
REFERENCE
CLK1
UVLO
4.3/4.5V
COMP1
26
5
IN14
GDH1
25
EA1
+
REF/IN1+
8
+
CS1+
1
CS12
BST1
R
PWM
+
0.5V
UVLO
0.75 VREF
SLOPE
COMP
Soft-Start And
Overload
Hiccup
Control
+ +
+ISEN
-
Σ
+ILIM+
75mV
ILIM+
110mV
COMP2
11
IN212
REFIN/IN2+
10
REFOUT
9
AGND
7
Non-Overlapping
Conduction
Control
Q
S
PVCC
23
GDL1
24
VPN1
27
PGND
22
SS1/EN1
OL
DSBL
28
GDH2
20
OCN
VIN2
17
VPN2
18
EA2
+
GDL2
21
+
0.72 VREFOUT
Figure 3. SC2446 Block Diagram (Channel 1 PWM Control Only)
OCN
IN0.75(VREF)
/ 0.72(VREFOUT)
+
S
2 µΑ
Q
OL
R
SS/EN
0.5V/3.2V
DSBL
UVLO
0.9V/1.2V
3 .4µΑ
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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SC2446
POWER MANAGEMENT
Operation
Overview
The SC2446 is a constant frequency 2–phase currentmode step-down PWM switching controller driving all Nchannel MOSFET’s. The two channels of the controller
operate at 180 degrees out of phase from each other.
Since input currents are interleaved in a two-phase
converter, input ripple current is lower and smaller input
capacitor can be used for filtering. Also, with lower
inductor current and smaller inductor ripple current per
phase, overall I2R losses are reduced.
inductor current reaches the threshold determined by
the error amplifier output and ramp compensation, the
high-side MOSFET is turned off. After a non-overlapping
conduction time of 90ns, the low-side MOSFET is turned
on.
The supply voltages for the high-side gate drivers are
obtained from two diode-capacitor bootstrap circuits. If the
bootstrap capacitor is charged from VCC, the high-side gate
drive voltage swing will be from approximately 2VCC to the
ground. The power dissipated in the high-side gate driver
is not higher with higher voltage swing because the gatesource voltage of the high-side MOSFET still swing from
zero to VCC.The outputs of the low-side gate drivers swing
from VC to the ground.
The SC2446 operates in synchronous continuousconduction mode. It can be configured either as two
independent step-down controllers producing two
separate outputs or as a dual-phase single-output
controller by tying the IN2- pin to VCC. In single output
operation, the channel one error amplifier controls both
channels and the channel two error amplifier is disabled.
Soft-start and overload hiccup of both channels is
synchronized to channel one.
The SC2446 has internal ramp-compensation to prevent
sub-harmonic oscillation when operating above 50% duty
cycle. There is enough ramp internally for a sensed
voltage ripple between ¼ to 1/3 of the full-scale sensed
voltage limit of 75mV. The maximum sensed voltage limit
is unaffected by the compensation ramp.
Frequency Setting and Synchronization
The internal oscillator of the SC2446 runs at twice the
phase frequency. The free-running frequency of the
oscillator can be programmed with an external resistor
from the ROSC pin to the ground. The step-down controllers
are capable of operating up to 1 MHz. It is necessary to
consider the operating duty-ratio before deciding the
switching frequency. See Applications Information section
for more details.
Current-Sensing
There are two ways to sense the inductor current for
current-mode control with the SC2446. Since the peak
inductor current corresponds to 75mV of sensed voltage
(CS+ - CS-), resistor current sensing can be used at the
output without resulting in excessive power dissipation.
Although accurate and far easier to lay out than highside resistor sensing, a pair of precision sense resistors
adds cost to the converter. The SC2446 has provision to
reconstruct a differential voltage proportional to the
inductor current at the output of the converter (U.S. patent
6,441,597). The voltage to current ratio or the equivalent
sense resistance Req is a combination of high-side and lowside MOSFET RDS(ON) ’s and the inductor series resistance
(hence the name “Combi-Sense”). The SC2446 provides
the virtual phase voltages VPN1 and VPN2 (these are
When synchronized externally, the applied clock frequency
should be twice the desired phase frequency. The
synchronizing clock frequency should also be between 11.33 times the set free-running frequency.
Control Loop
The SC2446 uses peak current-mode control for fast
transient response, ease of compensation and current
sharing in single output operation. The low-side MOSFET
of each channel is turned off at the falling-edge of the
phase timing clock. After a brief non-overlapping time
interval of 90ns, the high-side MOSFET is turned on. The
phase inductor current ramps up. When the sensed
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SC2446
POWER MANAGEMENT
Operation (Cont.)
unloaded versions of their respective power phase
voltages) for current sensing. This method does not
require any precision sense resistor. It is cheaper to
implement but is less accurate than resistor current
sensing. Since the sensed voltage is developed at the
output of the step-down converter, it is less prone to
switching transient spikes. This method will be described
in more details in the Applications Information section.
Error Amplifiers
In closed loop operation, the error amplifier output ranges
from 1.1V to 3.5V. The upper output operating range of
either error amplifier is reserved for positive currentsense voltage (CS+ - CS-) and corresponds to positive
(sourcing) output current. If the amplifier swings to its
lower operating range, the amplifier will still modulate
the high-side gate drive duty-ratio. However the peak
current-sense voltage (hence the peak inductor current)
will be limited to a negative value. The error amplifier
output is about 2.2V when the peak sense-voltage is zero.
The built-in offset in the current sense amplifier together
with synchronous continuous-conduction mode of
operation allows the SC2446 to regulate the output
irrespective of the direction of the load current.
The non-inverting input of the first feedback amplifier is
tied to the internal 0.5V voltage reference. Both the noninverting and the inverting inputs of the second error
amplifier are brought out as device pins so that the output
of the second converter can be made to track the output
of the first channel. For example in DDR applications,
Channel 1 can be used to generate VDDQ (2.5V) from the
input (5V or 12V) and channel 2 is used to produce a
tracking VTT (1.25V) with VDDQ being its input.
Current-Limit
The maximum current sense voltage of +75mV is the
cycle-by-cycle peak current limit when the load is drawing
current from the converter. There is no cycle-by-cycle
current limiting when the inductor current flows in the
negative direction. However once the valley of the current
sense voltage exceeds –110mV, the corresponding
channel will undergo shutdown and restart (hiccup).
2004 Semtech Corp.
Soft-Start and Overload Protection
The undervoltage lockout circuit discharges the SS/EN
capacitors. After VCC rises above 4.5V, the SS/EN capacitors
are slowly charged by internal 2µA current source. With
internal PNP transistors, the SS/EN voltages clamp the
error amplifier outputs. When the error amplifier output
rises to 2.2V, the high-side MOSFET starts to switch. As
the SS/EN capacitor continues to be charged, the COMP
voltage follows. The converter gradually delivers increasing
power to the output. The inductor current follows the COMP
voltage envelope until the output goes into regulation. The
SS/EN clamp on COMP is then released.
After the SS/EN capacitor is charged above 3.2V (high
enough for the error amplifier to provide full load current),
the overload detection circuit is activated. If the output
voltage falls below 70% of its set value or the valley
current-sense voltage exceeds –110mV, an overload latch
will be set and both the top and the bottom MOSFETs will
be turned off. The SS/EN capacitor is slowly discharged
with an internal 1.4µA current sink. The overload latch is
reset when the SS/EN capacitor is discharged below 0.5V.
The SS/EN capacitor is then recharged with the 2µA current
source and the converter undergoes soft-start. If overload
persists, the SC2446 will undergo repetitive shutdown and
restart (Figure 3).
If the output is short-circuited, the inductor current will
not increase indefinitely between the time the inductor
current reaching its current limit and the instant the
converter shuts down. This is due to cycle skipping
reduces the actual operating frequency.
The SS/EN pin can also be used as the enable input for
that channel. Both the high-side and the low-side
MOSFETs will be turned off if the SS/EN pin is pulled
below 0.7V.
10
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SC2446
POWER MANAGEMENT
Application Information
SC2446 consists of two current-mode synchronous buck
controllers with many integrated functions. By proper
application circuitry configuration, SC2446 can be used
to generate
1) two independent outputs from a common input or two
different inputs or
2) dual phase output with current sharing,
3) current sourcing/sinking from common or separate
inputs as in DDR (I and II) memory application.
The application information related to the converter design
using SC2446 is described in the following.
Step-down Converter
Starting from the following step-down converter
specifications,
Input voltage range: Vin ∈ [ Vin,min , Vin,max ]
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η
Selection criteria and design procedures for the following
are described.
1) output inductor (L) type and value,
2) output capacitor (Co) type and value,
3) input capacitor (Cin) type and value,
4) power MOSFET’s,
5) current sensing and limiting circuit,
6) voltage sensing circuit,
7) loop compensation network.
Operating Frequency (fs)
The switching frequency in the SC2446 is userprogrammable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered.
2004 Semtech Corp.
1)
2)
3)
4)
5)
Passive component size
Circuitry efficiency
EMI condition
Minimum switch on time and
Maximum duty ratio
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET’s/Diodes switching losses are
proportional to the operating frequency. Other issues such
as heat dissipation, packaging and the cost issues are
also to be considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
Minimum Switch On Time Consideration
In the SC2446 the falling edge of the clock turns on the
top MOSFET. The inductor current and the sensed voltage
ramp up. After the sensed voltage crosses a threshold
determined by the error amplifier output, the top MOSFET
is turned off. The propagation delay time from the turnon of the controlling FET to its turn-off is the minimum
switch on time. The SC2446 has a minimum on time of
about 150ns at room temperature. This is the shortest
on interval of the controlling FET. The controller either does
not turn on the top MOSFET at all or turns it on for at least
150ns.
For a synchronous step-down converter, the operating duty
cycle is VO/VIN. So the required on time for the top MOSFET
is VO/(VINfs). If the frequency is set such that the required
pulse width is less than 150ns, then the converter will
start skipping cycles. Due to minimum on time limitation,
simultaneously operating at very high switching frequency
and very short duty cycle is not practical. If the voltage
conversion ratio VO/VIN and hence the required duty cycle
is higher, the switching frequency can be increased to reduce
the sizes of passive components.
There will not be enough modulation headroom if the on
time is simply made equal to the minimum on time of the
SC2446. For ease of control, we recommend the required
pulse width to be at least 1.5 times the minimum on time.
11
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
Setting the Switching Frequency
The switching frequency is set with an external resistor
connected from Pin 3 to the ground. The set frequency
is inversely proportional to the resistor value (Figure 5).
800
700
fs (kHz)
600
500
400
300
200
100
0
0
50
100
150
200
250
Rosc (k Ohm)
Figure 5. Free running frequency vs. ROSC.
Inductor (L) and Ripple Current
Both step-down controllers in the SC2446 operate in
synchronous continuous-conduction mode (CCM) regardless
of the output load. The output inductor selection/design
is based on the output DC and transient requirements.
Both output current and voltage ripples are reduced with
larger inductors but it takes longer to change the inductor
current during load transients. Conversely smaller inductors
results in lower DC copper losses but the AC core losses
(flux swing) and the winding AC resistance losses are
higher. A compromise is to choose the inductance such
that peak-to-peak inductor ripple-current is 20% to 30% of
the rated output load current.
Assuming that the inductor current ripple (peak-to-peak)
value is δ*Io, the inductance value will then be
The followings are to be considered when choosing
inductors.
a) Inductor core material: For high efficiency applications
above 350KHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350KHz
but with attendant higher core losses.
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The
designer can choose the adjacent (larger) standard
inductance value. The inductance varies with
temperature and DC current. It is a good engineering
practice to re-evaluate the resultant current ripple at
the rated DC output current.
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
Output Capacitor (Co) and Vout Ripple
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load transient.
The output capacitor can be modeled as an ideal capacitor
in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure
6).
Co
Lesl
Resr
Figure 6. An equivalent circuit of Co.
If the current through the branch is ib(t), the voltage across
the terminals will then be
t
V (1 − D)
L= o
.
δIo fs
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
IL,rms = Io 1 +
2004 Semtech Corp.
δ2
.
12
v o ( t ) = Vo +
di ( t )
1
ib ( t )dt + L esl b + R esr ib ( t ).
Co 0
dt
∫
This basic equation illustrates the effect of ESR, ESL and
Co on the output voltage.
The first term is the DC voltage across Co at time t=0. The
second term is the voltage variation caused by the charge
balance between the load and the converter output. The
12
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
third term is voltage ripple due to ESL and the fourth
term is the voltage ripple due to ESR. The total output
voltage ripple is then a vector sum of the last three
terms.
Since the inductor current is a triangular waveform with
peak-to-peak value δ*Io, the ripple-voltage caused by
inductor current ripples is
∆v C ≈
δIo
,
8C o fs
the ripple-voltage due to ESL is
∆v ESL = L esl fs
δIo
,
D
and the ESR ripple-voltage is
∆v ESR = R esr δIo .
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low ESL’s.
The ESR has the dominant effect on the output ripple
voltage. It is therefore very important to minimize the ESR.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-voltage
< ∆Vo, the ESR should satisfy
R esr1 <
∆Vo
.
δIo
To limit the dynamic output voltage overshoot/undershoot
within α (say 3%) of the steady state output voltage) from
no load to full load, the ESR value should satisfy
R esr 2 <
αVo
.
Io
should be an order of magnitude smaller than the voltage
ripple caused by the ESR. To guarantee this, the
capacitance should satisfy
Co >
In many applications, several low ESR ceramic capacitors
are added in parallel with the aluminum capacitors in
order to further reduce ESR and improve high frequency
decoupling. Because the values of capacitance and ESR
are usually different in ceramic and aluminum capacitors,
the following remarks are made to clarify some practical
issues.
Remark 1: High frequency ceramic capacitors may not carry
most of the ripple current. It also depends on the capacitor
value. Only when the capacitor value is set properly, the
effect of ceramic capacitor low ESR starts to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic capacitors
at the ripple frequency. If a 100µF, 2mΩ ceramic capacitor
is used, the ripple current in the ceramic capacitor will be
about 4.2 times of that in the electrolytic capacitors. When
two 100µF, 2mΩ ceramic capacitors are used, the current
ratio increases to 8.3. In this case most of the ripple
current flows in the ceramic decoupling capacitor. The ESR
of the ceramic capacitors will then determine the output
ripple-voltage.
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead they
should be calculated using the following formulae.
Then, the required ESR value of the output capacitors
should be
Resr = min{Resr1,Resr2 }.
C eq (ω) :=
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also be
greater than
R eq (ω) :=
δIo
2 3
.
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement. The
voltage ripple cause by the capacitor charge/discharge
2004 Semtech Corp.
10
.
2πfsR esr
2
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
2
2
(R1a C1a + R1b C1b )ω2 C1a C1b + (C1a + C1b )
2
2
2
2
R1aR1b (R1a + R1b )ω2C1a C1b + (R1b C1b + R1a C1a )
2
2
(R1a + R1b )2 ω2 C1a C1b + (C1a + C1b )2
where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively. (Figure
7)
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
C1a
R1a
C1b
R1b
Ceq
Req
Figure 7. Equivalent RC branch.
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b =
R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin)
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 8.
Figure 9. Typical waveforms at converter input.
It can be seen that the current in the input capacitor pulses
with high di/dt. Capacitors with low ESL should be used. It
is also important to place the input capacitor close to the
MOSFET’s on the PC board to reduce trace inductances
around the pulse current loop.
The RMS value of the capacitor current is approximately
ICin = Io D[(1 +
δ2
D
D
)(1 − )2 + 2 (1 − D) ].
12
η
η
The power dissipated in the input capacitors is then
PCin = ICin2Resr.
Figure 8. A simple model for the converter input
For reliable operation, the maximum power dissipation in
the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high enough
to handle the ripple current. For higher power applications,
multiple capacitors are placed in parallel to increase the
ripple current handling capability.
In Figure 8 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR of
Resr. MOSFET and input capacitor current waveforms, ESR
voltage ripple and input voltage ripple are shown in Figure
9.
2004 Semtech Corp.
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SC2446
POWER MANAGEMENT
Application Information (Cont.)
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
δ
∆v ESR = R esr (1 + )Io .
2
2
If D1>0.5 and D2 > 0.5, then
2
2
ICin ≈ (D1 + D 2 − 1)(Io1 + Io 2 )2 + (1 − D 2 )Io1 + (1 − D1 )Io2 .
The peak-to-peak input voltage ripple due to the capacitor
is
∆v C ≈
2
ICin ≈ 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 − D 2 − 0.5)Io 2 .
DIo
,
Cin fs
From these two expressions, CIN can be found to meet the
input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce ripple.
The two step-down channels of the SC2446 operate at
180 degrees from each other. If both step-down channels
in the SC2446 are connected in parallel, both the input
and the output RMS currents will be reduced.
Choosing Power MOSFET’s
Main considerations in selecting the MOSFET’s are power
dissipation, cost and packaging. Switching losses and
conduction losses of the MOSFET’s are directly related to
the total gate charge (Cg) and channel on-resistance
(Rds(on)). In order to judge the performance of MOSFET’s,
the product of the total gate charge and on-resistance is
used as a figure of merit (FOM). Transistors with the same
FOM follow the same curve in Figure 10.
50
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the individual
DC input currents. The combined input current waveform
depends on duty ratio and the output current waveform.
Assuming that the output current ripple is small, the
following formula can be used to estimate the RMS value
of the ripple current in the input capacitor.
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
If D1
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