SC508/SC508A
EcoSpeed® DC-DC Buck Controller
with Integrated LDO
POWER MANAGEMENT
Features
Description
Power system
Input voltage — 4.5V to 46V
Output voltage — 0.6V to >85% x VIN
Integrated bootstrap switch
Fixed 5V LDO output — 200mA
1% reference
Selectable internal/external bias power supply
EcoSpeed® architecture with pseudo-fixed frequency adaptive on-time control
Logic input and output control
Independent control EN for LDO and switcher
Programmable soft-start time
Programmable VIN UVLO threshold
Power Good output
Selectable power-save mode for >80% efficiency under light load
Programmable ultrasonic power-save mode
SmartDriveTM for reduced EMI
Protections
Automatic restart on fault shutdown
Over-voltage and under-voltage
TC compensated RDS(ON) sensed current limit
Thermal shutdown
Smart power-save
Pre-bias start-up
Capacitor types: SP, POSCAP, OSCON, and ceramic
Package — 3 x 3(mm), 20-pin MLPQ
Lead-free and halogen-free
RoHS and WEEE compliant
AEC-Q100 Qualified available in SC508A
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The SC508/SC508A is a synchronous EcoSpeed® buck regulator which incorporates Semtech’s advanced, patented
adaptive on-time control architecture to provide excellent
light-load efficiency and fast transient response. It features an integrated bootstrap switch and a fixed 5V LDO in
a 3 x 3(mm) package. The device is highly efficient and
uses minimal PCB area. The SC508A is available for automotive applications and is qualified to AEC-Q100.
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The SC508 supports using standard capacitor types such as
electrolytic or special polymer, in addition to ceramic, at switching frequencies up to 1MHz. The programmable frequency,
synchronous operation, and programmable power-save
provide high efficiency operation over a wide load range.
Additional features include cycle-by-cycle current limit,
programmable soft-start, under and over-voltage protection, programmable over-current protection, start-up into
pre-biased output, automatic fault recovery (hiccup restart),
soft-shutdown, selectable power-save modes, and programmable ultrasonic power-save. The device also provides
separate enable inputs for the PWM controller and LDO as
well as a power good output for the PWM controller. Output
voltage range is 0.6 to 5V, with output voltages greater than
5V supported using additional components.
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Applications
Office automation and computing
Networking and telecommunication equipment
Point-of-load power supplies and module replacement
Automotive applications
The input voltage can range from 4.5V to 46V. The wide
input voltage range, programmable frequency, and integrated 5V LDO make the device extremely flexible and
easy to use in a broad range of applications. Support is
provided for multi-cell battery systems in addition to traditional DC power supply applications.
Typical Application Circuit
VEXT or VLDO
PGOOD
EN
ENABLE LDO
RTON
VEXT or VLDO
0.1µF
SC508
SC508A
ENL
TON
VDDA
VDDP
10nF
VIN
CIN
DH
LX
BST
ILIM
1µF
VLDO
1µF
VIN
PGOOD
ENABLE
3.3O
L1
VOUT
+
COUT
RLIM
DL
VOUT
VLDO
SS
PSV
AGND
FB
PGND
PSV
Revision 4.3
© 2012 Semtech Corporation
SC508/SC508A
FB
TON
AGND
EN
ILIM
Ordering Information
ENL
Pin Configuration
20
19
18
17
16
Top View
1
15
PGOOD
VOUT
2
14
PSV
VDDA
3
13
VDDP
VLDO
4
12
DL
VIN
5
11
PGND
7
8
9
10
BST
DH
LX
SS
6
NC
AGND PAD
Device
Package
SC508ULTRT(1)(2)
MLPQ-UT20
SC508AULTRT(1)(2)(3)
MLPQ-UT20
SC508EVB
Evaluation Board
SC508AEVB
Evaluation Board
Notes:
1) Available in tape and reel only. A reel contains 3000 devices.
2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
3) AEC-Q100 Qualified.
MLPQ-UT20
Marking Information
508
yyww
xxxx
508A
yyww
xxxx
yyww = Date Code
xxxx = Semtech Lot Number
yyww = Date Code
xxxx = Semtech Lot Number
SC508/SC508A
Absolute Maximum Ratings
Recommended Operating Conditions
LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +50
Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 46
LX to PGND (V) (transient — 100ns) . . . . . . . . . . -2 to +50
VDDA to AGND, VDDP to PGND (V). . . . . . . . . . . . 4.5 to 5.5
DH, BST to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +55
VOUT to PGND (V)(2). . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5
DH, BST to LX (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
DL to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6
Supports output voltages greater than 5.5V using
external components
VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +50
Thermal Information
EN, FB, ILIM, PGOOD to AGND (V). . . . -0.3 to +(VDDA + 0.3)
Storage Temperature (°C). . . . . . . . . . . . . . . . . . . . . -60 to +150
PSV, SS, TON to AGND (V). . . . . . . . . . . -0.3 to +(VDDA + 0.3)
Maximum Junction Temperature (°C). . . . . . . . . . . . . . . . 150
VLDO, VOUT to AGND (V). . . . . . . . . . . -0.3 to +(VDDA + 0.3)
Operating Junction Temperature (°C). . . . . . . . . -40 to +125
TON to AGND (V). . . . . . . . . . . . . . . . . . . -0.3 to +(VDDA -1.5)
Thermal resistance, junction to ambient(3) (°C/W). . . . . . . 50
ENL to AGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VIN
Peak IR Reflow Temperature (°C). . . . . . . . . . . . . . . . . . . . 260
VDDP to PGND, VDDA to AGND (V) . . . . . . . . . . . 0.3 to +6
VDDA to VDDP (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
AGND to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +0.3
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) VOUT pin must not exceed (VDDA pin + 0.3V).
(3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: VIN =12V, VDDA = VDDP = 5V, TA = +25°C for Typ, -40 to +85 °C for Min and Max, TJ < 125°C, Typical Application Circuit
Parameter
Conditions
Min
Typ
Max
Units
VDDA = 5V
4.5
46
V
Sensed at ENL pin, rising edge
1.50
1.56
1.70
Sensed at ENL pin, falling edge
1.45
1.52
1.65
Input Supplies
Input Supply Voltage (VIN)
VIN UVLO Threshold(1)
VIN UVLO Hysteresis
V
Sensed at ENL pin; EN = 5V
0.04
V
Measured at VDDA pin, rising edge
3.7
3.9
4.1
Measured at VDDA pin, falling edge
3.5
3.7
3.9
VDDA UVLO Threshold
V
VDDA UVLO Hysteresis
VIN Supply Current
0.2
Shutdown mode; ENL, EN = 0V, VIN = 46V
20
Standby mode; VDDA, VDDP, ENL = 5V, EN = 0V
130
V
35
μA
SC508/SC508A
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
ENL , EN = 0V
3
7
μA
Power-save operation
EN = 5V, PSV = open (float), VFB > 600mV
0.4
Ultrasonic Power-save operation
EN = 5V, RPSV = 115kΩ, VFB > 600mV
2.4
Forced Continuous Mode operation
Operating fSW = 220kHz, PSV = VDDA, no load
13
Input Supplies (continued)
VDDA + VDDP Supply Current(2)
FB Comparator Threshold
Frequency Range
Static VIN and load, 0 to +85 °C
0.5952
Static VIN and load, -40 to +85 °C
0.594
0.600
Continuous mode operation
mA
0.6048
V
0.606
V
1000
kHz
1870
ns
Timing
On-Time
Forced Continuous Mode operation
VIN = 30V, VOUT = 3 V, RTON = 600kΩ, VDDA = 5V
1530
On-time Accuracy; Forced Continuous Mode
VIN = 4.5 to 10V, VOUT = 3 V, RTON = 600kΩ, VDDA = 5V
1700
±15
%
Minimum On-Time
80
ns
Minimum Off-Time
250
ns
25
kHz
3.0
μA
500
kΩ
Ultrasonic Frequency
Minimum switching frequency, RPSV = 115kΩ
Soft-Start
Soft-Start Charge Current
Analog Inputs/Outputs
VOUT Input Resistance
Current Sense
Zero Cross Detector Threshold
LX with respect to PGND
-3
0
+3
mV
Power Good
Power Good Threshold
Startup Delay Time
Upper limit, VFB > internal 600mV reference
+20
Lower limit, VFB < internal 600mV reference
-10
EN rising edge to PGOOD rising edge, CSS = 10nF
11
ms
5
µs
Fault (noise immunity) Delay Time
Leakage
Power Good On-Resistance
PGOOD = high impedance (open)
PGOOD = pulled low to AGND
%
1
10
µA
Ω
SC508/SC508A
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
9
10
11
μA
Fault Protection
ILIM Source Current
ILIM Source Current Temperature Coefficient
ILIM Comparator Offset
0.41
With respect to AGND
-8
0
%/°C
+8
mV
Output Under-Voltage Threshold
VFB with respect to internal 600mV reference,
8 consecutive cycles
-25
%
Smart Power-Save Protection Threshold
VFB with respect to internal 600mV reference
+10
%
Over-Voltage Protection Threshold
VFB with respect to internal 600mV reference
+20
%
5
μs
165
°C
Over-Voltage Fault Delay
Over-Temperature Shutdown
10°C hysteresis
Logic Inputs/Outputs
Logic Input High Voltage — EN
Logic Input High Voltage — PSV
Logic Input Low Voltage — EN, ENL(3)
Forced Continuous Mode operation;
PSV pin with respect to VDDA
1.4
V
-0.4
V
With respect to AGND
EN Input Bias Current
EN = VDDA or AGND
ENL Input Bias Current
VIN = 46V
FB Input Bias Current
FB = VDDA or AGND
-10
0.4
V
+10
μA
+11
-1
PSV = VDDA
5
PSV < 1.5V
1
μA
+1
μA
16
μA
PSV Input Bias Current
μA
Linear Regulator
VLDO Accuracy
Current Limit
VLDO load = 10mA
4.875
5.0
VLDO < 1V start-up
13
1V < VLDO < 4.5V (typ)
90
Operating, VLDO > 4.5V (typ)
200
5.125
V
mA
VLDO to VOUT Switch-over Threshold (4)
-130
+130
mV
VLDO to VOUT Non-switch-over Threshold (4)
-500
+500
mV
VLDO to VOUT Switch-over Resistance
VLDO Drop Out Voltage
VLDO = VOUT = 5V
2.0
Ω
VIN to VLDO, LDO load = 50mA
1.2
V
SC508/SC508A
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ
Max
Units
High-Side Driver (DH, BST, LX)
Peak Current
VDDP = 5V, DH pin sourcing or sinking
2
RDH_PULL-UP, LX < 0.5V, VDDP = 5V
3.0
6.0
Ω
RDH_PULL-UP, LX > 0.5V, VDDP = 5V
1.0
2.0
Ω
RDH_PULL-DOWN, VDDP = 5V
0.6
1.2
Ω
Rise Time
CDH-LX = 3nF, VDDP = 5V
22
ns
Fall Time
CDH-LX = 3nF, VDDP = 5V
12
ns
From FB Input to DH
45
ns
Shoot-thru Protection Delay
45
ns
Bootstrap Switch Resistance
16
Ω
VDDP = 5V, DL sourcing
2
A
VDDP = 5V, DL sinking
4
RDL_PULL-UP, VDDP = 5V
1.0
2.1
Ω
RDL_PULL-DOWN, VDDP = 5V
0.50
0.86
Ω
Rise Time
CDL = 3nF, VDDP = 5V
7
ns
Fall Time
CDL = 3nF, VDDP = 5V
3.5
ns
On Resistance
Propagation Delay
A
Low-Side Driver (DL, VDDP, PGND)
Peak Current
On Resistance
Notes:
(1) VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
(2) For UPSV and FCM operation, the VDDA and VDDP supply current includes the DH/DL current required to drive the external MOSFETS.
(3) The ENL pin will enable the LDO with 0.8V typical. The ENL pin VIN ULVO function will disable the switcher unless the ENL pin exceeds the VIN
UVLO Threshold which is typically 1.56V.
(4) The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures
that VLDO will not switch-over to VOUT.
SC508/SC508A
Typical Characteristics (continued)
Efficiency vs Load — PSAVE Mode
Efficiency vs Load — 5V output
VOUT 1.8V, External 5V bias, 220kHz Frequency
100
100
90
42V
28V
80
42V
28V
Efficiency (%)
Efficiency (%)
15V
90
15V
80
VOUT 5V, Internal 5V bias, Power-save, 250kHz Frequency
70
60
50
70
60
50
40
40
30
30
20
20
Inductor: Cyntec PCMB104E-4R7MS
High side MOSFET: Alpha Omega AO4440
Low side MOSFET: Fairchild FMDS5352
0
1
2
3
4
IOUT (ADC)
5
6
7
8
0
1
VOUT 1.8V, External 5V bias, 220kHz Frequency
100
5
6
28V
15V
80
4
VOUT 12V, External 5V bias, Power-save, 400kHz Frequency
90
90
42V
80
42V
28V
Efficiency (%)
Efficiency (%)
3
IOUT (ADC)
Efficiency vs Load — 12V output
Efficiency vs Load — Ultrasonic PSAVE Mode
100
2
70
60
50
70
60
50
40
40
30
30
20
20
Inductor: Cyntec PCMB104E-4R7MS
High side MOSFET: Fairchild FMDS5352
Low side MOSFET: Fairchild FMDS5352
0
1
2
3
4
IOUT (ADC)
5
6
7
8
0
1
2
Efficiency vs Load — Forced Continuous Mode
100
6
VOUT 1.8V, External 5V bias, 220kHz Frequency
42 VIN
PSAVE
1.84
1.83
42V
28V
1.82
70
60
50
15 VIN
FCM
28 VIN
UPSAVE
1.81
VOUT (V)
Efficiency (%)
5
1.85
15V
80
4
Load Regulation
VOUT 1.8V, External 5V bias, 220kHz Frequency
90
3
IOUT (ADC)
1.80
1.79
1.78
40
1.77
30
1.76
1.75
20
0
1
2
3
IOUT
4
(ADC)
5
6
7
8
0
1
2
3
4
IOUT (ADC)
5
6
7
8
SC508/SC508A
Typical Characteristics (continued)
Start-up — EN Input
Pre-Bias Start-up — EN Input
VIN = 42V, VOUT = 1.8V, IOUT = 0A, PSAVE
EN (5V/div)
VIN = 42V, VOUT = 1.8V, IOUT = 0A, PSAVE
EN (5V/div)
VOUT (1V/div)
VOUT (1V/div)
PGOOD (5V/div)
PGOOD (5V/div)
LX (50V/div)
LX (50V/div)
Time (1ms/div)
Time (1ms/div)
Start-up — SS ramp-up
Shutdown — EN Input
VIN = 42V, VOUT = 1.8V, IOUT = 0A, PSAVE, startup using EN input
VIN = 42V, VOUT = 1.8V, IOUT = 1A, PSAVE
EN (5V/div)
SS (5V/div)
VOUT (1V/div)
VOUT (1V/div)
PGOOD (5V/div)
PGOOD (5V/div)
LX (50V/div)
LX (50V/div)
Time (1ms/div)
Time (1ms/div)
Start-up, Shutdown — ENL Input (VIN UVLO)
Over-current — Automatic Restart
VIN = 42V, VOUT = 1.8V, External load = 15A
VIN = 42V, VOUT = 1.8V, IOUT = 1A, PSAVE
SS (5V/div)
ENL (5V/div)
VOUT (1V/div)
VOUT (1V/div)
IOUT (10A/div)
PGOOD (5V/div)
LX (50V/div)
LX (50V/div)
Time (4ms/div)
Time (20ms/div)
SC508/SC508A
Typical Characteristics (continued)
Switching — PSAVE
Transient Response — PSAVE
VIN = 42V, VOUT = 1.8V, IOUT = 0A
VOUT (50mV/div)
VIN = 42V, VOUT = 1.8V, IOUT = 0A to 8A to 0A
VOUT (50mV/div)
DL (5V/div)
IOUT (5AV/div)
LX (50V/div)
LX (50V/div)
Time (10ms/div)
Time (100µs/div)
Switching — UPSAVE
Transient Response — UPSAVE
VIN = 42V, VOUT = 1.8V, IOUT = 0A
VIN = 42V, VOUT = 1.8V, IOUT = 0A to 8A to 0A
VOUT (50mV/div)
VOUT (50mV/div)
DL (5V/div)
IOUT (5A/div)
LX (50V/div)
LX (50V/div)
Time (20μs/div)
Time (100μs/div)
Transient Response — FCM
Switching — FCM
VIN = 42V, VOUT = 1.8V, IOUT = 0A to 8A to 0A
VIN = 42V, VOUT = 1.8V, IOUT = 0A
VOUT (50mV/div)
VOUT (50mV/div)
DL (5V/div)
IOUT (5A/div)
LX (50V/div)
LX (50V/div)
Time (4μs/div)
Time (100μs/div)
SC508/SC508A
Detailed Application Circuit
ENABLE LDO
EN
PGOOD
5
ILIM
EN
VDDP
VLDO
DL
VIN
VIN
100nF
SC508
VDDA
CSS
3.9nF
PGND
6
7
8
9
1µF
15
14
13
(1)
RLIM
6.81kW
12
VIN
(2)
RPSV
11
LX
VLDO
100nF
PSV
DH
1µF
VOUT
BST
4
5V
16
PGOOD
N/C
3(1)
FB
SS
2
5V
17
18
AGND
PAD
1
19
ENL
20
TON
RTON
154kW
10
Q1
CIN1 CIN2
RBST
3.3W
10µF 10µF
CBST
100nF
Q2
L1
36V to 1.8V @ 8A
COUT
1µF
+
CTOP*
np
RTOP
20kW
VOUT
RBOT
10kW
Key Components
Component
Value
Manufacturer
Part Number
CIN1, CIN2
10µF/50V
Murata
UMK325BJ106MM-T
www.murata.com
COUT
330µF/6mW
Sanyo
2TPF330M6
edc.sanyo.com
Web
L1
1.8µH
Vishay
IHLP4040EZER1R8M01
www.vishay.com
Q1
AO4440
Alpha Omega
AO4440
www.aosmd.com
Q2
FDMS5352
Fairchild
FDMS5352
www.fairchildsemi.com
Notes:
(1)
5V:
(2)
RPSV:
Connect VDDA and VDDP to external 5V supply for external bias.
Connect VDDA and VDDP to VLDO for self -biased operation.
Use 115kW for Ultrasonic operation.
Remove RPSV for Power-Save operation.
Connect PSV pin to VDDA for Forced Continuous Mode operation.
10
SC508/SC508A
Pin Descriptions
Pin #
Pin Name
Pin Function
1
FB
Feedback input for switching regulator — connect to an external resistor divider from output — used to program the output voltage.
2
VOUT
Switcher output voltage sense pin — also the input to the internal switch-over MOSFET between VOUT and
VLDO. The voltage at this pin must not exceed the VDDA pin. For output voltages up to 5V connect this pin
directly to the switcher output. For output voltages exceeding 5V connect this pin to the switcher output
through a resistor divider.
3
VDDA
5V supply input for internal analog circuits — connect to external 5V supply or connect to VLDO — also the
sense input for VDDA Under Voltage Lockout (VDDA UVLO).
4
VLDO
Output of the 5V LDO — The voltage at this pin must not exceed the voltage at the VDDA pin.
5
VIN
Input supply voltage — connect to the same supply used for the high-side MOSFET. Connect a 100nF capacitor from this pin to AGND to filter high frequency noise.
6
SS
Soft-Start — connect an external capacitor to AGND to program the soft start and automatic recovery time.
7
NC
No Connection
8
BST
Bootstrap pin — connect a 100nF minimum capacitor and series resistor from BST to LX to develop the floating voltage for the high-side gate drive. A 3.3 ohm resistor is recommended.
9
DH
High-side gate drive output
10
LX
Switching (phase) node
11
PGND
12
DL
13
VDDP
14
PSV
15
PGOOD
16
ILIM
17
EN
18
AGND
19
TON
ON time programming input — set the on-time by connecting through a resistor to AGND.
20
ENL
Enable input for the LDO and VIN UVLO input for the switching regulator — connect ENL to AGND to disable
the LDO — drive to logic high (>1.7V) to enable the LDO and inhibit VIN UVLO — connect to resistor divider
from VIN to AGND to program the VIN UVLO threshold.
PAD
AGND
Power ground for the DL and DH drivers and the low-side external MOSFET.
Low-side gate drive output
5V supply input for the DH and DL gate drives — connect to the same 5V supply used for VDDA.
Power-save programming input — connect a resistor to AGND to set a minimum (ultrasonic) power-save frequency — float pin to select power-save with no minimum frequency — pull up to VDDA to disable powersave and select forced continuous mode.
Open-drain Power Good indicator — high impedance indicates the switching regulator output is good. An
external pull-up resistor is required when connecting the PGOOD signal to external logic.
Current limit sense pin — used to program the current limit by connecting a resistor from ILIM to LX.
Enable input for switching regulator — logic low disables the switching regulator — logic high enables the
switching regulator.
Analog ground
Analog ground
11
SC508/SC508A
Block Diagram
VDDA
PGOOD
PSV
EN
VIN
VDDP
3
15
14
17
5
13
VDDA
AGND
A
VDDA UVLO
VDDA
SS
FB
6
VIN
VDDP
Control & Status
Bootstrap Switch
Reference
DL
VIN ULVO
Soft Start/
Automatic
Restart
Gate Drive
Control
On-time
Generator
1
FB Comparator
TON
VDDP
19
Zero Cross Detector
VOUT
BST
9
DH
10
LX
12
DL
11
PGND
16
ILIM
DL
2
VLDO Switchover Comparator
Current Limit
A
VLDO
8
4
Y
VLDO Switchover MUX
B
VIN
5V
LDO
VIN ULVO
detect
To Control & Status
20
ENL
A = connected to pins 18 and PAD
12
SC508/SC508A
Applications Information
Synchronous Buck Converter
The SC508 is a step down synchronous DC-DC buck controller with an internal 5V LDO. It provides efficient operation in a space saving 3x3 (mm) 20-pin package. The
programmable operating frequency range up to 1MHz
enables optimizing the configuration for PCB area and
efficiency. For automotive applications, the SC508A is
qualified to AEC-Q100.
The controller uses a pseudo-fixed frequency adaptive
on-time control. This allows fast transient response which
permits the use of smaller output capacitors.
Input Voltage Requirements
The SC508 requires two input supplies for normal operation: VIN and VDDA/VDDP. VIN operates over the wide
range of 5V to 46V. VDDA and VDDP require a 5V supply
which can be from an external source or from the internal
LDO. VDDA and VDDP must be derived from the same
source voltage.
Psuedo-fixed Frequency Adaptive On-time Control
The PWM control method used by the SC508 is pseudofixed frequency, adaptive on-time, as shown in Figure 1.
The ripple voltage generated at the output capacitor ESR
is used as a PWM ramp signal. This ripple is used to trigger
the on-time of the controller.
TON
VIN
VLX
CIN
Q1
VFB
VLX
VOUT
L
Q2
FB Threshold
The adaptive on-time is determined by an internal oneshot timer. When the one-shot is triggered by the output
ripple, the device sends a single on-time pulse to the highside MOSFET. The pulse period is determined by VOUT and
VIN. The period is proportional to output voltage and
inversely proportional to input voltage. With this adaptive
on-time configuration, the device automatically anticipates the on-time needed to regulate VOUT for the present
VIN condition and at the selected frequency.
The advantages of adaptive on-time control are:
•
•
•
•
•
Predictable operating frequency compared to
other variable frequency methods.
Reduced component count by eliminating the
error amplifier and compensation components.
Reduced component count by removing the
need to sense and control inductor current.
Fast transient response — the response time is
controlled by a fast comparator instead of a typically slow error amplifier.
Reduced output capacitance due to fast transient response.
One-Shot Timer and Operating Frequency
One-shot timer operation is shown in Figure 2. The FB
comparator output goes high when VFB is less than the
internal 600mV reference. This feeds into the DH gate
drive and turns on the high-side MOSFET, and also starts
the one-shot timer. The one-shot timer uses an internal
comparator and a capacitor. One comparator input is connected to VOUT, the other input is connected to the capacitor. When the on-time begins, the capacitor charges from
zero volts through a current which is proportional to VIN.
When the capacitor voltage reaches VOUT, the on-time is
completed and the high-side MOSFET turns off.
ESR
+
FB
COUT
FB
REF
VOUT
VIN
Figure 1 — PWM Control Method, VOUT Ripple
RTON
FB Comparator
Gate
Drives
+
One-Shot
Timer
VIN
DH
Q1
VLX
DL
Q2
VOUT
L
ESR
COUT
+
FB
On-time = K x RTON x (VOUT/VIN)
Figure 2 — On-Time Generation
13
SC508/SC508A
Applications Information (continued)
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
fSW
721 QV u 9,1
S) u 9287
§ 9287
·
¨¨
QV ¸¸ u 9,1
9
u
I
© ,1 6:
¹
S) u 9287
The maximum recommended RTON value is shown by the
following equation.
5721B0$;
9,1B0,1
u ȝ$
Immediately after the on-time, the DL output drives high
to energize the low-side MOSFET. DL has a minimum high
time of ~250ns, after which DL continues to stay high until
one of the following occurs:
•
•
To FB pin
R1
R2
Figure 3 — Output Voltage Selection
VOUT
TON u VIN
The SC508 uses an external resistor to set the on-time which
indirectly sets the frequency. The on-time can be programmed to provide an operating frequency of up to 1MHz
using a resistor between the TON pin and ground. The resistor value is selected by the following equation.
5721
VOUT
The FB input falls below the 600mV reference
The Zero Cross Detector trips if power-save is
active
Note that the on-time variation increases to typically 15%
at input voltages from 4.5 to 10V. In most applications this
does not significantly affect overall performance.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to the
internal 600mV reference voltage (see Figure 3).
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC value of
VOUT is offset by the output ripple according to the following equation.
VOUT
§ R · §V
·
0.6 u ¨¨1 1 ¸¸ ¨ RIPPLE ¸
© R2 ¹ © 2 ¹
In some applications a small capacitor CTOP is placed in
parallel with R1 to provide a larger ripple signal from VOUT
to the FB pin. In these applications, the output voltage
VOUT is calculated according to the following equation in
which w represents the switching frequency.
9287
§
5 · §9
·
u ¨¨ ¸¸ ¨ 5,33/( ¸ u
5
©
¹
¹
©
5Ȧ&723
§ 5 u 5
·
¨¨
Ȧ&723 ¸¸
5
5
©
¹
Configuring VOUT Greater Than 5V
The switcher output voltage can be programmed higher
than 5V with careful attention to the VOUT and RTON pins.
In these applications the VOUT pin cannot connect directly
to the switcher output due to its maximum voltage rating.
An additional resistor divider network is required to
connect from the switcher output to the VOUT pin as
shown in Figure 4.
LX
L
VOUT > 5V
RV1
COUT
To VOUT pin
RV2
Figure 4 — Resistor Divider For VOUT Exceeding 5V
14
SC508/SC508A
Applications Information (continued)
If the internal LDO is used for bias power, the LDO switchover function must be inhibited by selecting the resistor
divider so that the voltage at the VOUT pin does not
exceed 4V; this will inhibit the VLDO switch-over function. If the SC508 bias power is from an external 5V supply
and the LDO is disabled by grounding the ENL pin, the
voltage at the VOUT pin is not limited to 4V and can be as
high as the VDDA supply voltage.
Note that the VOUT pin has an internal 500kW resistor
connected to AGND. To minimize the effect of this resistor
on the resistor divider ratio, the maximum recommend
value for resistor RV2 in Figure 4 is 10kW.
In addition to the resistor divider, the RTON resistor value
must be adjusted. The on-time is generated according to
the voltage at the VOUT pin. In order to select the desired
on-time and operating frequency, the RTON resistor
should be adjusted to a higher value to compensate for
the reduced voltage at the VOUT pin. For output voltages
exceeding 5V, the required RTON value can be determined
by the following equation. The desired operating frequency is fSW.
5721
§ 9287
·
¨¨
QV ¸¸ u 9,1
§ 5 ·
© 9,1 u I6:
¹
u ¨¨ 9 ¸¸
S) u 9287
© 5 9 ¹
For applications where VOUT exceeds 5V, FCM operation is
recommended.
Forced Continuous Mode Operation
The SC508 operates the switcher in Forced Continuous
Mode (FCM) by connecting the PSV pin to VDDA. The PSV
pin should never exceed the VDDA supply. See Figure 5
for FCM waveforms. In this mode one of the power
MOSFETs is always on, with no intentional dead time other
than to avoid cross-conduction. This results in more
uniform frequency across the full load range with the
trade-off being reduced efficiency at light loads due to
the high-frequency switching of the MOSFETs.
The PSV pin contains a 5μA current sink to prevent stray
leakage current from pulling the PSV pin up to the VDDA
supply when the PSV pin is floated to select Power-Save
operation. To select Forced Continuous Mode operation,
the maximum recommended resistance between the
VDDA supply and the PSV pin is 40kW.
FB Ripple
Voltage (VFB)
FB threshold
DC Load Current
Inductor
Current
On-time
(TON)
DH on-time is triggered when
VFB reaches the FB Threshold.
DH
DL
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
Figure 5 — Forced Continuous Mode Operation
Programmable Ultrasonic Power-Save Operation
The device provides programmable ultrasonic power-save
operation at light loads; the minimum operating frequency is programmed by connecting a resistor from PSV
to AGND. The SC508 uses the PSV resistor to set an internal timer that monitors the time between consecutive
high-side gate pulses. If the time exceeds the programmed
timer, DL drives high to turn the low-side MOSFET on. This
draws current from VOUT through the inductor, forcing both
VOUT and VFB to fall. When VFB drops to the 600mV threshold, the next DH on-time is triggered. After the on-time is
completed the high-side MOSFET is turned off and the
low-side MOSFET turns on, and the internal timer is
restarted. The low-side MOSFET remains on until the
inductor current ramps down to zero, at which point the
low-side MOSFET is turned off. This ends the cycle until VFB
again falls below the 600mV threshold, or the internal
timer forces another DL turn-on.
15
SC508/SC508A
Applications Information (continued)
Because the period between on-times is limited to a
maximum value, a minimum operating frequency is maintained. Figure 6 shows ultrasonic power-save operation.
ately exits power-save and returns to forced continuous
mode. Figure 7 shows power-save operation at light
loads.
minimum frequency
FB Ripple
Voltage (VFB)
FB threshold
(0A)
Inductor
Current
On-time
(TON)
FB Ripple
Voltage
(VFB)
DH
DH On-time is triggered when
VFB reaches the FB Threshold.
DL
After the programmable time-out, DL drives
high if VFB has not reached the FB threshold.
Figure 6 — Ultrasonic Power-Save Operation
The equation for determining the RPSV resistor value is
shown next. The desired minimum frequency is fSWMIN.
RPSV
Zero (0A)
On-time (TON)
DH
DL
FB threshold
Inductor
Current
DH On-time is triggered when
VFB reaches the FB Threshold
programmable time-out
Dead time varies
according to load
1
350pF u fSWMIN
Power-Save Mode Operation
The device provides power-save operation at light loads
with no minimum operating frequency, selected by floating the PSV pin (no connection). In this mode of operation, the zero cross comparator monitors inductor current
via the voltage across the low-side MOSFET during the
off-time. If the inductor current falls to zero for 8 consecutive switching cycles, the controller enters power-save
operation. It will then turn off the low-side MOSFET on
each subsequent cycle, provided that the current falls to
zero. After the low-side MOSFET is off, both high-side and
low-sides MOSFETs remain off until VFB drops to the 600mV
threshold. While the MOSFETs are off the load is supplied
by the output capacitor. If the inductor current does not
reach zero on any switching cycle, the controller immedi-
DL drives high when on-time is completed.
DL remains high until inductor current reaches zero.
Figure 7 — Power-Save Operation
Smart Power-Save Protection
Active loads may leak current from a higher voltage into
the switcher output. Under light load conditions with
power-save enabled, this can force VOUT to slowly rise and
reach the over-voltage threshold, resulting in an overvoltage shutdown. Smart power-save prevents this condition. When the FB voltage exceeds 10% above nominal
(exceeds 660mV), the device immediately disables powersave and DL drives high to turn on the low-side MOSFET.
This draws current from VOUT through the inductor and
causes VOUT to fall. When VFB drops back to the 600mV trip
point, a normal TON switching cycle begins. This method
prevents over-voltage shutdown by cycling energy from
VOUT back to VIN. It also minimizes operating power under
light load conditions by avoiding forced continuous mode
operation.
Figure 8 shows typical waveforms for the Smart Powersave feature.
16
SC508/SC508A
Applications Information (continued)
Smart Power Save
Threshold
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
FB
threshold
Current Limit Protection
DH and DL off
High-side
Drive (DH)
Single DH on-time pulse
after DL turn-off
Low-side
Drive (DL)
DL turns on when Smart
PSAVE threshold is reached
Note that the LDO enable pin (ENL) can also disable the
switching regulator through the VIN UVLO function. Refer
to the ENL Pin and VIN UVLO section.
Normal DL pulse after DH
on-time pulse
DL turns off when FB
threshold is reached
Figure 8 — Smart Power-Save
SmartDriveTM
For each DH pulse, the DH driver initially turns on the
high-side MOSFET at a slower speed. This produces a
softer, controlled turn off and reverse recovery of the lowside diode. Once the low-side diode is off and the LX
voltage has risen 0.8V above PGND, the SmartDrive circuit
automatically drives the high-side MOSFET on at a rapid
rate. This two stage technique reduces switching noise
and EMI while maintaining high efficiency and reducing
the need for external snubbers.
Enable Input for Switching Regulator
The EN input is a logic level input. When EN is low
(grounded), the switching regulator is off and in its lowest
power state. When EN is low and VDDA is above the VDDA
UVLO threshold, the output of the switching regulator
soft-discharges into the VOUT pin through an internal
2kΩ resistor. When EN is a logic high (>1V) the switching
regulator is enabled.
The SC508 features programmable current limiting, which
is accomplished using the RDS(ON) of the lower MOSFET for
current sensing. The current limit is set by RLIM resistor
which connects from the ILIM pin to the drain of the lowside MOSFET. When the low-side MOSFET is on, an internal
10μA current flows from the ILIM pin and through the RLIM
resistor, creating a voltage drop across the resistor. While
the low-side MOSFET is on, the inductor current flows
through it and creates a voltage across the RDS(ON). The
voltage across the MOSFET is negative with respect to
PGND. If this MOSFET voltage drop exceeds the voltage
across RLIM, the voltage at the ILIM pin will be negative and
current limit will activate. The current limit then keeps the
low-side MOSFET on and prevents another high-side ontime, until the current in the low-side MOSFET reduces
enough to bring the ILIM pin voltage up to zero. This
method regulates the inductor valley current at the level
shown by ILIM in Figure 9.
Inductor Current
VOUT drifts up to due to leakage
current flowing into COUT
IPEAK
ILOAD
ILIM
Time
Figure 9 — Valley Current Limit
The current limit schematic with the RLIM resistor is shown
in Figure 10.
The EN input has internal resistors — 2MΩ pullup to
VDDA, and a 1MΩ pulldown to AGND. These resistors will
normally cause the EN voltage to be near the logic high
trip point as VDDA reaches the VDDA UVLO threshold.
To prevent undesired toggling of EN and erratic start-up
performance, the EN pin should not be allowed to float as
open-circuit.
17
SC508/SC508A
Applications Information (continued)
VIN
BST
CBST
Q1
+
CIN
ILIM
DL
VOUT
L
DH
LX
RLIM
PGND
Q2
D2
COUT
+
After the SS capacitor voltage reaches 1.5V, the SS capacitor continues to charge until the SS voltage is equal to
67% of VDDA. At this time the Power Good monitor compares the FB pin to the 600mV reference and sets the
PGOOD output high (open drain) if VOUT is in regulation.
The time between VOUT reaching the regulation point
and the PGOOD output going high is shown by the following equation.
&66 § u 9''$
·
u¨
9 ¸
ȝ$ ©
¹
W3*22'
Figure 10 — Valley Current Limit
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus peak ripple current. In this
situation the average current through the inductor is 10A
plus one-half the peak-to-peak ripple current.
The RLIM value is calculated by the next equation.
5/,0
5'621 u ,/,0
ȝ$
The internal 10μA current source is temperature compensated at 4100ppm in order to provide tracking with the
RDSON.
Soft-Start of PWM Regulator
The SC508 has a programmable soft-start time that is controlled by an external capacitor at the SS pin. During the
soft-start time, the controller sources 3μA from the SS pin
to charge the capacitor. During the start-up process
(Figure 11), 40% of the voltage ramp at the SS pin is used
as the reference for the FB comparator. The PWM comparator issues an on-time pulse when the FB voltage is less
than 40% of the SS voltage, which forces the output
voltage to follow the SS ramp. The output voltage reaches
regulation when the SS pin voltage exceeds 1.5V and the
FB reaches the 600mV threshold. The time between the
first LX pulse and VOUT reaching the regulation point is
the soft-start time (tSS). The calculation for the soft-start
time is shown by the following equation.
t SS
CSS u 1.5 V
3PA
The time from the rising edge of the EN pin to the PGOOD
output going high is shown by the following equation.
W(1B*22'
&66 § u 9''$ ·
u¨
¸
ȝ$ ©
¹
After the Power Good Start-up Delay Time is completed,
the SS pin is internally pulled up to the VDDA supply.
The soft-start cycle and Power Good timing can be seen in
the Figure 11.
EN
CSS charging
current 3uA
VSS = 3.35V
VSS = 1.5V
SS
VOUT in regulation
FB
tSS
tPGOOD
PGOOD
Figure 11 — Soft-start Cycle and Power Good timing
Pre-Bias Start-up
SC508 can support soft-start with an output pre-bias. The
SS ramp time is the same as a normal start-up when the
output voltage starts from zero. Under a pre-bias start-up,
the DH and DL drivers inhibit switching until 40% of the
18
SC508/SC508A
Applications Information (continued)
ramp at the SS pin equals the pre-bias FB voltage level.
Pre-bias start-up is achieved by turning off the lower
MOSFET when the inductor current reaches zero during
the soft-start cycle. This method prevents the output
voltage from decreasing.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires an external pull-up resistor. During startup, PGOOD is held low and is not allowed to transition
high until the FB pin is in regulation and the SS pin has
reached 67% of VDDA. The time from EN going high to
PGOOD going high is typically 11ms for CSS = 10nF.
When the voltage at the FB pin is 10% below the nominal
voltage, PGOOD is pulled low. Once PGOOD pulls low
there is typically 2% hysteresis to prevent chatter on the
PGOOD output.
PGOOD will transition low if the FB voltage exceeds +20%
of nominal (720mV), which is also the over-voltage shutdown threshold. PGOOD also pulls low if the EN pin is low
and VDDA is present.
Output Over-Voltage Protection
Over-voltage protection (OVP) becomes active as soon as
the device is enabled. The OVP threshold is set at 600mV
+20% (720mV). There is a 5μs delay built into the OVP
detector to prevent false transitions. When VFB exceeds the
OVP threshold, DL is driven high and the low-side MOSFET
is turned on. DL remains high and the controller remains
off while the device goes through the automatic fault
recovery cycle. When the automatic recovery cycle is
completed, the device will attempt a new soft-start cycle.
At the start of the soft-start cycle, the DL output will go
low for typically 30usec while the controller initializes the
soft-start sequence. PGOOD is also low after an OVP
event.
Output Under-Voltage Protection
When VFB falls 25% below its nominal voltage (falls to
450mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate the MOSFETs. The controller stays off while the
device goes through the automatic fault recovery cycle.
Automatic Fault Recovery
The SC508 includes an automatic recovery feature (hiccup
mode upon fault). If the switcher output is shut down due
to a fault condition, the device uses the SS capacitor as a
timer. Upon fault detection the SS pin is pulled low and
then begins charging through the internal 3μA current
source. When the SS capacitor reaches 67% of VDDA, the
SS pin is again pulled low, after which the SS capacitor
begins another charging cycle. The SS capacitor will be
used for 15 cycles of charging from 0 to 67% of VDDA.
(For Over-voltage and Over-Temperature faults, the count
will be 16 cycles instead of 15.) During these cycles the
switcher is off and there is no MOSFET switching.
During the next charging cycle, the normal soft-start
routine is implemented and the MOSFETs begin switching. Switching continues until the Power Good Start-up
Delay Time is reached. If the switcher output is still in a
fault condition, the switcher will again shut down and
force 15 cycles of SS charging (16 cycles in the case of an
Over-voltage or Over-Temperature fault) before attempting another soft-start. The long delay between soft-start
cycles reduces the average power loss in the power
components.
The automatic recovery timing is shown in Figure 12.
fault
applied
1 soft-start cycle
1 soft-start cycle
tEN_PGOOD
tEN_PGOOD
15 cycles
15 cycles
tHICCUP = 15 x tEN_PGOOD
tHICCUP = 15 x tEN_PGOOD
tEN_PGOOD
67% x VDDA
SS
Figure 12 — Automatic Recovery Timing
The control of the low-side MOSFET during an Overvoltage
fault is handled differently from other faults. If the fault
was due to an over-voltage condition, the DL output will
remain high during 16 SS charging cycles. For all other
faults, the DL output will remain low. However, if the FB
pin exceeds the Over-voltage threshold, the charging of
the SS capacitor will not occur, and the DL output will
remain high. If the FB pin falls below the OVP threshold,
16 SS charging cycles will occur while DL remains high.
When the next start-up cycle commences, DL will drive
19
SC508/SC508A
Applications Information (continued)
low for typically 30us as the controller re-initializes the
internal soft-start routine.
Note that LDO faults will not be automatically recovered
by the hiccup restart feature, refer to the LDO Thermal
Limitations section.
VDDA UVLO and POR
The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhibits switching and tri-states the DH/DL drivers until VDDA
rises above 3.9V. When VDDA exceeds 3.9V, an internal
POR (Power-On Reset) resets the fault latch and the softstart circuitry and then the SC508 is ready to begin a softstart cycle. The switcher will shut off if VDDA falls below
3.6V. VDDP does not have UVLO protection.
LDO Regulator
When the LDO is providing bias power to the device, a
minimum 0.1μF capacitor referenced to AGND is required,
along with a minimum 1μF capacitor referenced to PGND
to filter the gate drive pulses. Refer to the PCB Layout
Guidelines section.
ENL Pin and VIN UVLO
The ENL pin is also used for the VIN under-voltage lockout
(VIN UVLO) for the switcher. The VIN UVLO voltage is programmable via a resistor divider at the VIN, ENL and AGND
pins. The VIN UVLO function has a typical threshold of 1.56V
on the VIN rising edge. The falling edge threshold is 1.52V.
Timing is important when driving ENL with logic and not
using the VIN UVLO capability. The ENL pin must transition
from high to low within 2 switching cycles to avoid the
PWM output turning off. If ENL goes below the VIN UVLO
threshold and stays above 1V, then the switcher will turn
off but the LDO will remain on.
Note that it is possible to operate the switcher with the
LDO disabled, but the ENL pin must be below the logic
low threshold (0.4V maximum), otherwise the VIN UVLO
function will disable the switcher.
The next table summarizes the function of the ENL and EN
pins, with respect to the rising edge of ENL.
EN
ENL
LDO status
Switcher status
low
high
low
high
low
high
low, < 0.4V
low, < 0.4V
high, < 1.52V
high, < 1.52V
high, > 1.56V
high, > 1.56V
off
off
on
on
on
on
off
on
off
off
off
on
Figure 13 shows the ENL voltage thresholds and their
effect on LDO and Switcher operation.
ENL voltage
LDO on
Switcher on if EN = high
1.56V
VIN UVLO hysteresis
1.52V
LDO on
Switcher off by VIN UVLO
ENL low
threshold
(min 0.4V)
LDO off
Switcher on if EN = high
AGND
Figure 13 — ENL Thresholds
ENL Logic Control of PWM Operation
When the ENL input exceeds the VIN UVLO threshold of
1.56V, internal logic checks the PGOOD signal. If PGOOD
is high, the switcher is already running and the LDO will
start without affecting the switcher. If PGOOD is low, the
device disables PWM switching until the LDO output has
reached 90% of its final value. This delay prevents the
additional current needed by the DH and DL gate drives
from overloading the LDO at start-up.
LDO Start-up
Before LDO start-up, the device checks the status of the
following signals to ensure proper operation can be
maintained.
20
SC508/SC508A
Applications Information (continued)
1. ENL pin
2. VLDO output
3. VIN input voltage
When the ENL pin is high and VIN voltage is available, the
LDO will begin start-up. During the initial phase when
VLDO is below 1V, the LDO initiates a current-limited startup (typically 20mA). This protects the LDO from thermal
damage if the VLDO pin is shorted to ground. As VLDO
exceeds 1V, the start-up current gradually increases to
80mA. When VLDO reaches 4.5V, the LDO current limit
increases to 200mA and the LDO output rises quickly to
5.0V. The LDO start-up profile is shown in Figure 14.
VLDO
voltage regulating with
200mA current limit
increasing current
1.0V
20mA constant current
Figure 14 — LDO Start-Up
LDO Thermal Limitations
The LDO is not protected by the Over-Temperature shutdown feature. If the LDO output is loaded externally, the
resulting power loss can cause overheating and failure of
the LDO.
In typical applications where the LDO is used to power
only the SC508 and the external MOSFETs, the current
supplied by the LDO is typically below 30mA and temperature rise is acceptable.
The LDO output is protected against heavy overloading or
short circuits as shown in Figure 14. When the LDO load is
enough to keep the LDO output below 1V, the availablecurrent from the LDO is typically 20mA, which limits the
power loss and prevents LDO overheating.
LDO Switch-Over Operation
The SC508 includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
After the switcher completes soft-start and the PGOOD
delay, the switch-over logic waits for 32 switching cycles
before it starts the switch-over. There are two methods of
completing the switch-over of VLDO to VOUT.
In the first method, the LDO is already in regulation when
the DC-DC converter is enabled. As soon as the PGOOD
output goes high, the 32 cycle count is started. The voltages at the VLDO and VOUT pins are then compared; if the
two voltages are within ±300mV of each other, the VLDO
pin connects to the VOUT pin using an internal switch,
and the LDO is turned off.
5V
4.5V
by using the more efficient DC-DC converter to power the
IC, avoiding the less efficient LDO regulator when possible.
The switch-over function connects the VLDO pin directly
to the VOUT pin through an internal switch. When the
switch-over is complete the LDO is turned off, which
reduces operating power loss. If the LDO output is used to
bias the SC508, then after switch-over the device is selfpowered from the switching regulator with the LDO
turned off.
In the second method, the DC-DC converter is already
running and the LDO is enabled. In this case the 32 cycle
count is started as soon as the LDO reaches 90% of its final
value. At this time, the VLDO and VOUT pins are compared,
and if within ±300mV the switch-over occurs and the LDO
is turned off.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that
are inherent to its construction, as shown in Figure 15.
Switchover
control
Switchover
MOSFET
VLDO
VOUT
Parasitic diode
Parasitic diode
VDDA
Figure 15— Switch-over MOSFET Parasitic Diodes
21
SC508/SC508A
Applications Information (continued)
It is important to prevent forward bias of these diodes.
The following two conditions must be satisfied in order for
the parasitic diodes to stay off.
•
•
VDDA > VLDO
VDDA > VOUT
If either VLDO or VOUT is higher than VDDA, the respective
diode will turn on and the SC508 operating current will
then flow through this diode. This has the potential of
damaging the device.
Using the Internal LDO to Bias the SC508
The following steps must be followed when using the
internal LDO to bias the device.
•
•
•
Connect VDDA and VDDP to VLDO before
enabling the LDO.
During the initial start-up the LDO, when the
LDO output is less than 1V, the external load
should not exceed 10mA. Above 1V, any external load on VLDO should not exceed 40mA until
the LDO voltage has reached 4.5V.
Review any external loads connected to the
LDOoutput to prevent overheating of the LDO.
When the switch-over feature is used and the VDDA/VDDP
power comes from the VOUT pin, the EN and ENL inputs
must be used carefully. Do not connect the EN pin directly
to VDDA or another supply voltage. If this is done, driving
the ENL pin low (to AGND) will turn off the LDO and the
LDO switch-over MOSFET, but the switcher will continue
operating. VOUT will feed into the LDO output and the
VDDA/VDDP supplies through the internal parasitic diode.
This can potentially damage the device, and also prevents
the switcher from shutting off until the VDDA supply drops
below the VDDA UVLO threshold. For these applications a
dedicated logic signal is required to drive EN low and
disable the switcher. This signal can be combined with
the ENL signal if needed, as long as the EN pin does not
exceed Absolute Maximum Ratings.
LDO Usage at Low Input Voltage
Applications requiring steady-state or transient operation
at low input voltages (VIN below 6.5V) may use the internal
LDO to bias the VDDA/VDDP pins within limitations. There
are limitations to both startup and normal operation as
explained below.
When starting up using the internal LDO, switcher operation is inhibited until the LDO output reaches 4.5V. During
this time, the LDO start-up is implemented using a current
source. At low VIN it is important to not apply an external
load to the LDO, in order to allow the LDO output to reach
the 4.5V threshold and allow switching to begin.
Once switching begins, LDO operation transitions from
current-source operation to voltage regulation. The
minimum operating VIN is then limited by the RDSON of the
internal LDO MOSFET. The current required to power the
SC508 and external MOSFET gates causes a voltage drop
from the VIN pin to the VLDO pin. The VLDO pin must stay
above 4.5V, otherwise the LDO control will revert back to
current-source operation, causing more voltage drop at
the LDO output. The RDSON of the LDO mosfet at low VIN is
typically 24 ohms at 25°C.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor
ripple current must be specified.
The maximum input voltage (VINMAX) is the highest specified
input voltage. The minimum input voltage ( VINMIN) is determined by the lowest input voltage including the voltage
drops due to connectors, fuses, switches, and PCB traces.
The following parameters define the design.
•
•
•
•
Nominal output voltage (VOUT )
Static or DC output tolerance
Transient response
Maximum load current (IOUT )
There are two values of load current to evaluate — continuous load current and peak load current. Continuous
load current relates to thermal stresses which drive the
selection of the inductor and input capacitors. Peak load
current determines instantaneous component stresses and
filtering requirements such as inductor saturation, output
capacitors, and design of the current limit circuit.
22
SC508/SC508A
Applications Information (continued)
The following values are used in this design.
•
•
•
•
VIN = 28V + 10%
VOUT = 1.8V + 4%
fSW = 220kHz
Load = 8A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the
power conversion efficiency.
The desired switching frequency is 220kHz.
A resistor, RTON is used to program the on-time (indirectly
setting the frequency) using the following equation.
R TON
(TON 10ns) u VIN
28pF u VOUT
To select RTON, use the maximum value for VIN, and for TON
use the value associated with maximum VIN.
T ON
V OUT
V INMAX u f SW
TON = 266 ns at 30.8VIN, 1.8VOUT, 220kHz
Substituting for RTON results in the following solution.
RTON = 156kΩ, use RTON = 154kΩ
Inductor Selection
In order to determine the inductance, the ripple current
must first be defined. Low inductor values result in smaller
size but create higher ripple current which can reduce
efficiency. Higher inductor values will reduce the ripple
current/voltage and for a given DC resistance are more
efficient. However, larger inductance translates directly
into larger packages and higher cost. Cost, size, output
ripple, and efficiency are all used in the selection process.
The ripple current will also set the boundary for powersave operation. The switching will typically enter powersave mode when the load current decreases to 1/2 of the
ripple current. For example, if ripple current is 4A then
Power-save operation will typically start for loads less than
2A. If ripple current is set at 40% of maximum load current,
then power-save will start for loads less than 20% of
maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25% to 60% of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the DH on-time, voltage across the inductor is
(VIN - VOUT ). The following equation for determining inductance is shown.
L
( VIN VOUT ) u TON
IRIPPLE
In this example the inductor ripple current is set approximately equal to 50% of the maximum load current. Thus
ripple current target will be 50% x 8A or 4A.
To find the minimum inductance needed, use the VIN and
TON values that correspond to VINMAX.
/
u QV
$
ȝ+
A slightly smaller value of 1.8µH is selected. This will
increase the maximum IRIPPLE to 4.3A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
721B9,10,1
IRIPPLE
S) u 5 721 u 9287
QV
9,10,1
QV
( VIN VOUT ) u TON
L
,5,33/(B9,10,1
u QV
ȝ+
$
23
SC508/SC508A
Applications Information (continued)
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is controlled by the output ripple requirement and the DC tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is for the output voltage regulation to be
±4% under static conditions. The internal 600mV reference tolerance is 1%. Allowing 1% tolerance from the FB
resistor divider, this allows 2% tolerance due to VOUT ripple.
Since this 2% error comes from 1/2 of the ripple voltage,
the allowable ripple is 4%, or 72mV for a 1.8V output.
The maximum ripple current of 4.3A creates a ripple
voltage across the ESR. The maximum ESR value allowed
is shown by the following equations.
(650$;
95,33/(
The following can be used to calculate the needed capacitance for a given dILOAD/dt. Peak inductor current is shown
by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 8 + 1/2 x 4.3 = 10.2A
P9
$
,5,33/(0$;
Rate of change of Load Current
ESRMAX = 16.7 mΩ
The output capacitance is chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor
current is at the peak, determines the required capacitance. If the load release is instantaneous (load changes
from maximum to zero in < 1µs), the output capacitor
must absorb all the inductor’s stored energy. This will
cause a peak voltage on the capacitor according to the
following equation.
COUTMIN
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 600mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately
-VOUT. This causes a down-slope or falling di/dt in the
inductor. If the load di/dt is not faster than the -di/dt in
the inductor, then the inductor current will tend to track
the falling load current. This will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used.
1
§
·2
L¨ IOUT u IRIPPLEMAX ¸
2
©
¹
2
VPEAK VOUT
COUT
2
COUTMIN = 272µF
2
ILPK u
ILPK
I
MAX u dt
VOUT dlLOAD
2 VPK VOUT
Example
dlLOAD
dt
2 .5 A
Ps
The preceding rate of load change would cause the output
current to move from 8A to zero in 3.2µs.
2
1
§
·2
1.8PH¨ 8 u 4.3 ¸
2
©
¹
1.98 1.80
IMAX = maximum load release = 8A
Lu
Assuming a peak voltage VPEAK of 1.98 (180mV rise upon
load release), and a 8A load release, the required capacitance is shown by the next equation.
COUTMIN
dlLOAD
dt
COUT
10.2 u
10.2
8
u 1Ps
1.8 2.5
2 u 1.98 1.8
1.8PH u
COUT = 198µF
Note that COUT is much smaller in this example, 198µF
compared to 272µF based on a worst-case load release. To
meet the two design criteria of minimum 272µF and
24
SC508/SC508A
Applications Information (continued)
maximum 16.7mΩ ESR, select a capacitor rated at 330µF
and 6mΩ ESR.
It is recommended that an additional small capacitor with
a value of 1 to 10µF be placed in parallel with COUT in order
to filter high frequency switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect operation. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also imperative to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small capacitor across the upper feedback resistor, as
shown in Figure 16. This capacitor should be left unpopulated unless it can be confirmed that double-pulsing
exists. Adding the CTOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional connection on the PCB should be available for this capacitor.
One simple way to solve this problem is to add trace resistance in the high current output path. A side effect of
adding trace resistance is decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and discharging during the switching cycle. For most applications the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching frequency. The formula for minimum ESR is shown by the
following equation.
ESR MIN
3
2 u S u C OUT u f sw
Using Ceramic Output Capacitors
CTOP
VOUT
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
To FB pin
R1
R2
Figure 16 — Capacitor Coupling to FB Pin
NOTE: The CTOP capacitor can moderately affect the DC output voltage, refer to the section on VOUT voltage selection.
When using high ESR value capacitors, the feedback
voltage ripple lags the phase node voltage by 90 degrees
and the converter is easily stabilized. When using ceramic
output capacitors, the ESR value is normally too small to
meet the above ESR criteria. As a result, the feedback
voltage ripple is 180 degrees from the phase node leading
to unstable operation. In this application it is necessary to
add a small virtual ESR network that is composed of two
capacitors and one resistor, as shown by RL, CL, and CC in
Figure 17.
25
SC508/SC508A
Applications Information (continued)
RL
+- D x VIN
L
DCR
L
VL
CL
RL
R1
CC
COUT
R2
FB
pin
DCR
VOUT
VOUT
VL
CL
CC
CC
R1
R1
COUT
COUT
R2
FB
pin
FB
pin
R2
Figure 17 — Virtual ESR Ramp Circuit
Figure 19 — FB Voltage by Output Voltage
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across C L and the output ripple
voltage. They are defined in the following equations.
The magnitude of the FB ripple contribution due to output
voltage ripple is shown by the following equation.
9)%'9287
,/ u '&5 V u / '&5
6 u 5/&/
9F /
',/
& u I6:
'9287
Figure 18 shows the equivalent circuit for calculating the
magnitude of the ripple contribution at the FB pin due to CL.
L
+-
D x VIN
DCR
RL
VL
CL
FB
pin
CC
R1
'9287 u
5
5
5
6 u &&
The purpose of this network is to couple the inductor
current ripple information into the feedback voltage such
that the feedback voltage has 90 degrees phase lag to the
switching node similar to the case of using standard high
ESR capacitors. This is illustrated in Figure 20.
VOUT
FB contribution by
output voltage ripple
LX
FB contribution
by CL
R2
Combined FB
Figure 18 — FB Voltage by CL Voltage
The magnitude of the FB ripple contribution due to CL is
shown by the following equation.
VFBc L
Vc L u
R1 // R2 u S u C C
R1 // R2 u S u C C 1
Figure 19 shows the equivalent circuit for calculating the
magnitude of the ripple contribution due to the output
voltage ripple.
IL
Figure 20 — FB voltage in Phaser Diagram
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from CL , is controlled by
the value of R1, R2 and CC . If the corner frequency of (R1//
R2) x CC is too high, the ripple magnitude at the FB pin will
be smaller, which can lead to double-pulsing. Conversely,
if the corner frequency of (R1// R2) x CC is too low, the ripple
magnitude at FB pin will be higher. Since the SC508 regulates to the valley of the ripple voltage at the FB pin, a high
ripple magnitude is undesirable as it significantly impacts
the output voltage regulation. As a result, it is desirable to
26
SC508/SC508A
Applications Information (continued)
select a corner frequency for (R1// R2) x CC to achieve
enough, but not excessive, ripple magnitude and phase
margin. The component values for R1, R2, and CC should
be calculated using the following procedure.
Select CL (typical 10nF) and RL to match with L and DCR
time constant using the following equation.
5/
/
'&5 u &/
Select CC by using the following equation.
&& |
u
5 5 u S u IVZ
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is
from 10pF to 1nF.
Dropout Performance
The output voltage adjust range for continuous-conduction operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times.
The duty-factor limitation is shown by the following
equation.
DUTY
TON(MIN)
TON(MIN) TOFF(MAX )
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions it trips when the feedback pin is 600mV, + 1%.
The on-time pulse from the SC508 in the design example
is calculated to give a pseudo-fixed frequency of 220kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ½ of the output ripple appears as a DC regulation error. For example, if the output ripple is 50mV with
VIN = 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
80mV with VIN = 25V, then the measured DC output will be
40mV above the comparator trip. The best way to minimize this effect is to minimize the output ripple.
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors contributes up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Switching Frequency Variations
The switching frequency will vary depending on line and
load conditions. The line variations are a result of fixed
propagation delays in the on-time one-shot, as well as
unavoidable delays in the external MOSFET switching. As
VIN increases, these factors make the actual DH on-time
slightly longer than the ideal on-time. The net effect is
that frequency tends to falls slightly with increasing input
voltage.
The switching frequency also varies with load current as a
result of the power losses in the MOSFETs and the inductor. For a conventional PWM constant-frequency converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
27
SC508/SC508A
Applications Information (continued)
MOSFETs and inductor. A adaptive on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). Because the on-time is
essentially constant for a given VOUT/VIN combination, to
offset the losses the off-time will reduce slightly as load
increases. The net effect is that switching frequency
increases slightly with increasing load.
PCB Layout Guidelines
A switch-mode converter requires good PCB layout which
is essential to achieving high performance. The following
guidelines will provide an optimum PCB layout.
The device layout recommendations consist of four parts.
•
•
•
•
Grounding for PGND and AGND
Power components
Low-noise analog circuits
Bypass capacitors
Grounding for PGND and AGND
A ground plane layer for PGND is recommended
to minimize the effects of switching noise, resistive losses, and to maximize heat removal from
the power components.
A separate ground plane or island should be used
for AGND and all associated components. The
AGND island should avoid overlapping switching
signals on other layers (DH/DL/BST/LX).
Connect PGND and AGND together with a zero
ohm resistor or copper trace. Make the connection near the AGND and PGND pins of the IC.
•
•
•
•
•
Low-noise Analog Circuits
Low-noise analog circuits are sensitive circuits that are
referenced to AGND. Due to their high impedance and
sensitivity to noise, it is important that these circuits be
located as far as possible from the switching signals.
•
•
•
•
•
Power Components
Use short, wide traces between the following
power components.
Input capacitors and high-side MOSFETs
High-side and Low-side MOSFETs and inductor (LX connection). Use wide copper
traces to provide high current carrying capacity and for heat dissipation.
Inductor and output capacitors.
All PGND connections — the input capacitors, low-side MOSFETs, output capacitors,
and the PGND pin of the SC508.
An inner layer ground plane is recommended.
Each power component requires a short, low
impedance connection to the PGND plane.
Place vias to the PGND plane directly near the
component pins.
Use short wide traces for the pin connections
from the SC508 (LX, DH, DL and BST). Do not
route these traces near the sensitive low-noise
analog signals (FB, SS, TON, VOUT ).
Avoid overlapping of the DL trace with LX/DH/
BST. This helps reduce transient peaks on the
gate of the low-side MOSFET during the turn-on
of the high-side MOSFET.
•
•
Use a plane or solid area for AGND. Place all
components connected to AGND above this
area.
Use short direct traces for the AGND connections to all components.
Place vias to the AGND plane directly near
the component pins.
Proper routing of the VOUT sense trace is essential
since it feeds into the FB resistor divider. Noise
on the FB waveform will cause instability and
multiple pulsing.
Connect the VOUT sense trace directly to
the output capacitor or a ceramic bypass
capacitor.
Route this trace over to the VOUT pin, carefully avoiding all switching signals and
power components.
Route this trace in a quiet layer if possible.
Route this trace away from the switching traces and components, even if the
trace is longer. Avoid shorter trace routing
through the power switching area.
If a bypass capacitor is used at the IC side
of the VOUT sense trace, it should be placed
near the FB resistor divider.
All components connected to the FB pin must
be located near the pin. The FB traces should be
28
SC508/SC508A
Applications Information (continued)
•
•
•
kept small and not routed near any noisy switching connections or power components.
Place the SS capacitor near the SS pin with a
short direct connection to the AGND plane.
Place the RLIM resistor near the IC. For an accurate
ILIM current sense connection, route the RLIM trace
directly to the drain of the low-side MOSFET (LX).
Use an inner routing layer if needed.
Place the RTON resistor near the TON pin. Route
R TON to the TON pin and to AGND using short
traces and avoid all switching signals.
Bypass Capacitors
The device requires bypass capacitors for the following
pins.
•
•
•
•
VDDA pin with respect to AGND. This 0.1μF
minimum capacitor must be placed and routed
close to the IC pins, on the same layer as the IC.
This capacitor also functions as bypass for the
LDO output, since the VDDA and VLDO pins are
adjacent.
VDDP with respect to PGND. This 1μF minimum
capacitor must be placed and routed close to
the IC pins and on the same layer as the IC.
BST pin with respect to LX. This 0.1μF minimum
capacitor must be placed near the IC, on either
side of the PCB. Use short traces for the routing
between the capacitor and the IC.
VIN pin with respect to AGND. This 0.1μF
minimum capacitor must be placed and routed
close to the IC pins. This capacitor provides
noise filtering for the input to the internal LDO.
29
SC508/SC508A
Outline Drawing — MLPQ-UT20 3x3
A
D
PIN 1
INDICATOR
(LASER MARK)
DIMENSIONS
INCHES
MILLIMETERS
DIM
MIN NOM MAX MIN NOM MAX
B
E
A2
A
aaa C
C
A1
SEATING
PLANE
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
.020
.000
-
.024
.002
(.006)
.006 .008 .010
.114 .118 .122
.061 .067 .071
.114 .118 .122
.061 .067 .071
.016 BSC
.012 .016 .020
20
.003
.004
0.50
0.00
-
0.60
0.05
(0.1524)
0.15 0.20 0.25
2.90 3.00 3.10
1.55 1.70 1.80
2.90 3.00 3.10
1.55 1.70 1.80
0.40 BSC
0.30 0.40 0.50
20
0.08
0.10
D1
e
LxN
E/2
E1
2
1
N
D/2
bxN
bbb
C A B
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS .
3. DAP is 1.90 x 190mm.
30
SC508/SC508A
Land Pattern — MLPQ-UT20 3x3
H
R
(C)
DIMENSIONS
K
G
Y
X
P
Z
DIM
INCHES
MILLIMETERS
C
G
H
K
P
R
X
Y
Z
(.114)
(2.90)
.083
.067
.067
.016
.004
.008
.031
.146
2.10
1.70
1.70
0.40
0.10
0.20
0.80
3.70
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
31
SC508/SC508A
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Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
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湘ICP备2023018690号
