SX1243
DATASHEET
WIRELESS & SENSING
SX1243 - Low Cost Low Current Integrated Transmitter
310 to 928MHz Frequency Agile
GENERAL DESCRIPTION
APPLICATIONS
The SX1243 is an ultra-low-cost, fully integrated FSK or
OOK transmitter suitable for operation between 310 and
450 MHz, 860 and 870 MHz, as well as 902 and 928 MHz.
For applications where economy is paramount, the SX1243
may be used without the requirement for configuration via
an MCU. However, in conjunction with a microcontroller the
communication link parameters may be re-configured.
Including, output power, modulation format and operating
channel.
The SX1243 offers integrated radio performance with cost
efficiency and is suited for operation in North America FCC
Part 15.231, FCC Part 15.247 FHSS and Digital Modulation
Techniques, 15.249, and Europe EN 300 220.
ORDERING INFORMATION
Part Number
Temperature Range
Package
MOQ / Multiple
SX1243IULTRT
-40 °C to +85 °C
DFN-UT8
3000 pieces
Garage Door Openers
Low-Cost Consumer Electronic Applications
Remote Keyless Entry (RKE)
Remote Control / Security Systems
KEY PRODUCT FEATURES
+10 dBm or 0 dBm Configurable output power
Bit rates up to 100 kbps
OOK and FSK modulation.
1.8 to 3.7 V supply range.
Low BOM Fully Integrated Tx
Fractional-N PLL with 1.5 kHz typical step
Frequency agility for FHSS modulation
FCC CFR Part 15.247 Digital Modulation Techniques
Pb-Free, Halogen Free, RoHS/WEEE compliant product.
NRESET
RFOUT
1
8
PA
DATA
2
7
CP
GND
XTAL
M/N
3
PFD
4
Sigma
/Delta
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TX_READY
6
CTRL
1.8 to 3.7 V
5
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VDD
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Table of contents
Section
1.
2.
3.
4.
5.
6.
7.
8.
Page
Circuit Description ....................................................................................................................................................................... 3
1.1.
General Description ............................................................................................................................................................ 3
1.2.
Block Diagram .................................................................................................................................................................... 3
1.3.
Marking Diagram ................................................................................................................................................................ 4
1.4. Pin Description, DFN8 Encapsulation ..................................................................................................................................... 5
Electrical Characteristics ............................................................................................................................................................. 6
2.1.
ESD Notice ......................................................................................................................................................................... 6
2.2.
Absolute Maximum Ratings ................................................................................................................................................ 6
2.3.
Operating Range ................................................................................................................................................................ 6
2.4. Electrical Specifications ........................................................................................................................................................... 7
Digital Specification ..................................................................................................................................................................... 9
Application Modes of the SX1243 ............................................................................................................................................. 10
4.1.
Transmitter Modes............................................................................................................................................................ 10
4.2.
Mode Selection Flowchart ................................................................................................................................................ 11
4.3. Application Mode: Power & Go ............................................................................................................................................. 12
4.4.
Application Mode: Advanced ............................................................................................................................................ 12
4.4.1.
Advanced Mode: Configuration................................................................................................................................. 12
4.4.2.
Frequency Hopping Spread Spectrum...................................................................................................................... 12
4.5. Frequency Band Coverage ................................................................................................................................................... 13
4.6. Power Consumption .............................................................................................................................................................. 14
SX1243 Configuration ............................................................................................................................................................... 15
5.1.
TWI Access....................................................................................................................................................................... 15
5.2.
APPLICATION Configuration Parameters ........................................................................................................................ 17
5.3.
FREQUENCY Configuration Parameters ......................................................................................................................... 17
5.4.
Test Parameters ............................................................................................................................................................... 18
5.5.
Status Parameters ............................................................................................................................................................ 18
5.6. Recovery Command .............................................................................................................................................................. 19
Application Information.............................................................................................................................................................. 20
6.1.
Crystal Specification ......................................................................................................................................................... 20
6.2.
Evaluation Module ............................................................................................................................................................ 20
6.3.
NRESET Pin ..................................................................................................................................................................... 22
6.4.
TX_READY Pin................................................................................................................................................................. 22
6.5.
Low Power Optimization ................................................................................................................................................... 22
6.5.1.
2 Connections: CTRL, DATA .................................................................................................................................... 22
6.5.2.
3 Connections: CTRL, DATA, TX_READY ............................................................................................................... 22
SX1243 Packaging.................................................................................................................................................................... 23
7.1.
Package Outline Drawing ................................................................................................................................................. 23
7.2.
Thermal Impedance.......................................................................................................................................................... 23
7.3.
Land Pattern ..................................................................................................................................................................... 24
7.4.
Tape & Reel Specification ................................................................................................................................................ 24
Revision History ........................................................................................................................................................................ 25
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SX1243
Integrated Transmitter IC
DATASHEET
WIRELESS & SENSING
This product datasheet contains a detailed description of the SX1243 performance and functionality.
1. Circuit Description
1.1. General Description
The SX1243 is a fully-integrated multi-band, single chip transmitter IC capable of FSK and OOK modulation of an input
data stream.
It contains a frequency synthesizer which is a fractional-N sigma-delta PLL. For frequency modulation (FSK), the
modulation is made inside the PLL bandwidth. For amplitude modulation (OOK), the modulation is performed by turning on
and off the output PA.
The frequency reference used by the PLL is generated by a 22, 24 or 26 MHz crystal oscillator, depending on the
frequency band of interest.
The Power Amplifier (PA), connected to the RFOUT pin, can deliver 0 dBm or +10 dBm in a 50 Ω load. Each of these two
output powers need a specific matching network when efficiency needs to be optimized.
The circuit can be configured via a simplified TWI interface, constituted of pin CTRL and DATA. The pins of this interface
are also used to transmit the modulating data to the chip.
Another key feature of the SX1243 is its low current consumption in Transmit and Sleep modes and its wide voltage
operating range from 1.8 V to 3.7 V. This makes the SX1243 suitable for low-cost battery chemistries or energy harvesting
applications.
1.2. Block Diagram
The figure below shows the simplified block diagram of the SX1243 die mounted in a DFN8 package.
NRESET
RFOUT
1
8
PA
DATA
2
7
CP
GND
XTAL
TX_READY
M/N
3
PFD
6
4
Sigma
/Delta
5
CTRL
1.8 to 3.7 V
VDD
Figure 1. SX1243 Simplified Block Diagram and BOM
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1.3. Marking Diagram
Figure 2. Marking Diagram
- nnn = Relates to the part number
- yw = Date code
- xxx = Lot No
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1.4. Pin Description, DFN8 Encapsulation
Table 1
Description of the SX1243 DFN8 Pinouts
Number
Name
Type
Function in ‘Power & Go’ Modes
Function in ‘Advanced’ Mode
0
GND
I
Exposed Pad, Ground
1
NRESET
I
Reset (Optional, can be left floating)
2
DATA
I/O
3
GND
I
Ground
4
XTAL
I/O
Reference Crystal
5
VBAT
I
Power Supply 1.8V to 3.7V
6
CTRL
I
7
TX_READY
O
Transmitter Ready Flag (Optional, can be left floating)
8
RFOUT
O
Transmitter RF Output
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Transmit Data
Config Selection
Page 5
Transmit or Configuration Data
Configuration Data Clock
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Integrated Transmitter IC
DATASHEET
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2. Electrical Characteristics
2.1. ESD Notice
The SX1243 is an electrostatic discharge sensitive device. It satisfies Class 2 of the JEDEC standard
JESD22-A114-B (Human Body Model) on all pins.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 2
Absolute Maximum Ratings
Symbol
Description
Min
Max
Unit
VDDmr
Supply Voltage
-0.5
3.9
V
Tmr
Temperature
-55
115
°C
Tjunc
Junction Temperature
-55
125
°C
Tstor
Storage Temperature
-55
150
°C
2.3. Operating Range
Operating ranges define the limits for functional operation and the parametric characteristics of the device as described in
this section. Functionality outside these limits is not implied.
Table 3
Operating Range
Symbol
Description
Min
Max
Unit
VDDop
Supply voltage
1.8
3.7
V
Top
Operational temperature range
-40
85
°C
Clop
Load capacitance on digital ports
-
25
pF
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Integrated Transmitter IC
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2.4. Electrical Specifications
The table below gives the electrical specifications of the transmitter under the following conditions: Supply voltage VBAT =
3.3 V, temperature = 25 °C, fXOSC = 26 MHz, fRF = 915 MHz, 2-FSK modulation with Fdev=+/-10 kHz, bit rate = 10 kbit/s
and output power = +10 dBm terminated in a matched 50 Ohm impedance, unless otherwise specified.
Table 4
Symbol
Transmitter Specifications
Description
Conditions
Min
Typ
-
125
Max
Unit
Current Consumption
IDDSL
Supply current in Sleep mode
nA
IDDT_315
Supply current in Transmit mode
at 315 MHz*
RFOP=+10dBm 50% OOK
RFOP=+10dBm FSK
RFOP=0dBm FSK
-
11
15
9
-
mA
mA
mA
IDDT_915
Supply current in Transmit mode
at 915 MHz*
RFOP=+10dBm FSK
RFOP=0dBm
FSK
-
17.5
10.5
-
mA
mA
RF and Baseband Specifications
FBAND
Accessible Frequency Bands
Band 0, with FXOSC=22 MHz
310
-
450
MHz
See details in Table 7.
Band 0, with FXOSC=24 MHz
312
-
450
MHz
Band 0, with FXOSC=26 MHz
338
-
450
MHz
Band 1, with FXOSC=26 MHz
860
902
-
870
928
MHz
MHz
10
-
200
kHz
FDA
Frequency deviation, FSK
BRF
Bit rate, FSK
Permissible Range
0.5
-
100
kbps
BRO
Bit rate, OOK
Permissible Range
0.5
-
10
kbps
OOK_B
OOK Modulation Depth
-
45
-
dB
RFOP
RF output power in 50 Ohms
in either frequency band
High Power Setting
Low Power Setting*
7
-3
10
0
-
dBm
dBm
RFOPFL
RF output power flatness
From 315 to 390 MHz, 50 Ohms load
-
2
-
dB
DRFOPV
Variation in RF output power with
supply voltage
2.5 V to 3.3 V
1.8 V to 3.7 V
-
-
3
7
dB
dB
PHN
Transmitter phase noise
At offset:
100 kHz
350 kHz
550 kHz
1.15 MHz
-
-84
-94
-96
-105
-
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
STEP_22
RF frequency step
FXOSC = 22 MHz, Band 0
-
1.34277
-
kHz
STEP_24
RF frequency step
FXOSC = 24 MHz, Band 0
-
1.46484
-
kHz
STEP_26
RF frequency step
FXOSC = 26 MHz, Band 0
FXOSC = 26 MHz, Band 1
-
1.58691
3.17383
-
kHz
kHz
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Symbol
Description
FXOSC
Crystal Oscillator Frequency
DFXOSC
Frequency Variation of the XOSC
Conditions
Min
Typ
Max
Unit
-
22
24
26
-
MHz
MHz
MHz
No crystal contribution
-
-
+/-25
ppm
XTAL dependant, with spec’d XTAL
-
650
2000
us
Timing Specifications
TS_TR
Time from Sleep to Tx mode
TS_HOP0
Channel hop time in Band 0
315 to 390 MHz
-
250
500
us
TS_HOP1
Channel hop time in Band 1
Maximum hop of 26 MHz***
-
200
400
us
TOFFT
Timer from Tx data activity to
Sleep
Programmable
-
2
20
-
ms
ms
RAMP
PA Ramp up and down time
-
20
-
us
T_START
Time before CTRL pin mode
selection.
-
200 us
+ TS_OSC
-
ms
Time from power on to sampling of
CTRL **
* With different matching networks
** The oscillator startup time, TS_OSC, depends on the electrical characteristics of the crystal
*** From the last CTRL falling edge of the Frequency change instruction to transmitter ready (PA ramp up finished)
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3. Digital Specification
The following table gives the operating specifications for the digital inputs and outputs of the SX1243.
Table 5
Digital Signals Specification
Symbol
Description
VIH
Min
Typ
Max
Unit
Digital input level high
0.8
-
-
VBAT
VIL
Digital input level low
-
-
0.2
VBAT
VOH
Digital output level high
Imax = 1 mA
0.9
-
-
VBAT
VOL
Digital output level low
Imax = -1 mA
-
-
0.1
VBAT
fCTRL
CTRL Clock Frequency
-
-
10
MHz
tch
CTRL Clock High time
45
-
-
ns
tcl
CTRL Clock Low time
45
-
-
ns
trise
CTRL Clock rise time
-
-
5
ns
tfall
CTRL Clock Fall time
-
-
5
ns
tsetup
DATA Setup time
From Data transition to CTRL rising
edge
45
-
-
ns
thold
DATA hold time
From CTRL rising edge to DATA
transition
45
-
-
ns
t0, t2
Time at “1” on DATA during
Recovery command
See Figure 10 and Figure 11
-
-
5
us
t1
Time at “0” on DATA during
Recovery command
See Figure 11
5
-
-
us
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4. Application Modes of the SX1243
Pins CTRL and DATA are used for both configuring the circuit and sending the data to be transmitted over the air. Two
different modes are associated to these pins, “Power&Go” and “Advanced” modes.
4.1. Transmitter Modes
Automatic Mode operation is described in Figure 3. Here we see that a rising edge on the DATA pin activates the
transmitter start-up process. DATA must be held high for the start-up time (TS_TR) of the SX1243. During this time the
SX1243 undergoes an optimized, self-calibrating trajectory from Sleep mode to Transmit mode. Once this time has
elapsed, the SX1243 is ready to transmit. Any logical signal subsequently applied to the DATA pin is then transmitted.
Figure 3. ‘Power & Go’ Mode: Transmitter Timing Operation
The transition back to Sleep mode is managed automatically. The SX1243 waits for TOFFT (2 or 20 ms) of inactivity on
DATA before returning to Sleep mode.
In Forced Transmit Mode the circuit can be forced to wake up and go to TX mode by sending an APPLICATION
instruction through the TWI interface, and setting the Mode bit DA(15) to ‘1’. Once in Transmit the circuit will transmit over
the air the data stream presented on the DATA pin. The circuit will stay in transmit mode until a new APPLICATION
instruction is sent with DA(15) to ‘0’.
Figure 4. Forced Transmit Mode Description
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4.2. Mode Selection Flowchart
Circuit Start-up
Wait T_Start
Logic ‘0’
Check
CTRL Pin
Power & Go 1
868.3 MHz
FSK, Fdev=+/-19.2kHz
+10dBm
Logic ‘1’
Power & Go 2
433.92 MHz
OOK
+10dBm
CTRL Clock signal
Advanced Mode
Full register flexibility
Automatic or forced Transmit
Figure 5. SX1243 Mode Selection
Note:
Advanced mode is entered only if DATA is held low during CTRL’s rising edge.
When powering up the circuit (microcontroller and SX1243), the logic level of the CTRL pin is sampled after T_START, as
described on Figure 6. During T_START, the microcontroller IO driving the CTRL pin must be configured as an output,
driving the CTRL pin to the desired state.
Figure 6. Power-up Timing
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4.3. Application Mode: Power & Go
The default ‘Power & Go’ application mode sees the SX1243 configured as detailed in Table 6. By changing the logical
state of the CTRL pin at Power-up or Reset, two distinct configuration modes can be selected. The Power & Go application
modes hence permit microcontroller-less operation.
Table 6
Configuration in Power & Go Mode
CTRL Pin
Configuration
Mode
‘Low’
FSK 868.3 MHz, +10 dBm, Fdev=+/-19.2 kHz
Power&Go 1
‘High’
OOK 433.92 MHz, +10 dBm
Power&Go 2
4.4. Application Mode: Advanced
4.4.1. Advanced Mode: Configuration
As described on Figure 5, Advanced mode is entered when accessing the Two Wire Interface (TWI) bus of the SX1243.
Upon communication to the register at up to 10 MHz of clocking speed, complete flexibility on the use of the chip is
obtained.
Once all register settings are selected (see registers detailed description in section [5]), the SX1243 can be used either in
Automatic mode by simply toggling the DATA pin, or in Forced Transmit mode to optimize timings for instance.
4.4.2. Frequency Hopping Spread Spectrum
Frequency hopping is supported in Advanced mode. After sending the data stream in the first channel, the user can send
a Frequency change instruction containing the new channel frequency. The circuit will automatically ramp down the PA,
lock the PLL to the new frequency, and turn the Power Amplifier back on. The user can then send his packet data on the
new channel. Timings are detailed hereafter:
t < TOFFT
(2 or 20 ms)
TWI
instruction
DATA
Frequency change
CTRL
Frequency change
t < TOFFT
(2 or 20 ms)
RFOUT
5th falling
edge on CTRL
24th falling
edge on CTRL
TS_HOPi
Tx Channel A
Tx Channel B
Figure 7. Frequency Hopping Description
Notes: - During any TWI access, the input of the modulator is inhibited
- The time between two Frequency change instructions shall be greater than TS_HOPi
- FHSS modulation, as described under FCC part 15.247, is supported by the SX1243; also note that the large
Frequency Deviation settings available on the SX1243 make it suitable for “Digitally Modulated Systems”, as
described under FCC Part 15.247 (a)(2)
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4.5. Frequency Band Coverage
The SX1243 offers several combinations or frequency references and frequency outputs, allowing for maximum flexibility
and design of multi-band products:
Table 7
Frequency Selection Table
Reference
Frequency
FXOSC
Band Setting
DA(13)
22 MHz
Upper / Lower
Frequency
Bounds
310 to 450 MHz
Fstep
6
22x10
Fstep = ----------------= 1.34277kHz
14
2
0
24 MHz
Frf &
Fdev
Frf = DF ( 18 ;0 ) × Fstep
312 to 450 MHz
6
24x10
Fstep = ----------------= 1.46484kHz
14
2
Fdev = DA ( 12 ;5 ) × Fstep
6
338 to 450 MHz
26x10
= 1.58691kHz
Fstep = ----------------14
2
860 to 870 MHz
and
902 to 928 MHz
26x10
Fstep = ----------------= 3.17383kHz
13
2
26 MHz
1
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4.6. Power Consumption
The following typical power consumption figures are observed on the SX1243 kits. Note that the transmitter efficiency
depends on the impedance matching quality, and can be PCB design dependant.
The PA matching may be different in each frequency band.
Table 8
Power Consumption in Tx mode
Typical Current
Drain
Frequency Band
Conditions
310 to 450 MHz
Pout=+10dBm, OOK modulation with 50% duty cycle
Pout=+10dBm, FSK modulation
Pout=0dBm, FSK modulation
860 to 870 MHz
Pout=+10dBm, FSK modulation
Pout=0dBm, FSK modulation
16.5 mA
10 mA
902 to 928 MHz
Pout=+10dBm, FSK modulation
Pout=0dBm, FSK modulation
17.5 mA
10.5 mA
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11 mA
15 mA
9 mA
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5. SX1243 Configuration
The SX1243 has several configuration parameters which can be selected through the serial interface.
5.1. TWI Access
As long as CTRL is kept stable, the DATA pin is considered by the circuit as the input for the data to be transmitted over the
air (Power&Go modes).
Programming of the configuration register is triggered by a rising edge on the CTRL line. Upon detection of this rising edge,
the data applied to the DATA pin is accepted as register configuration information, the data bits are clocked on subsequent
rising edges of the clocking signal applied to the CTRL pin. The timing for SX1243 configuration register ‘write’ is shown in
Figure 8. Note that, once triggered, all 24 clock cycle must be issued to the SX1243.
CTRL
DATA
1st
2nd
23rd
24th
DATA pin is an input
Figure 8. TWI Configuration Register ‘Write’.
The registers may, similarly, be read using the timing of Figure 9.
CTRL
DATA
1st
2nd
8th
24th
DATA pin is an output
DATA pin is an input
Figure 9. TWI Configuration Register ‘Read’.
The first rising edge on CTRL which initiates the ADVANCED mode must occur at least 1 ms after the circuit has been
powered up or reset.
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Table 9
TWI Instruction Table
Byte 0
Byte 1
Byte 2
Instruction
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0
(0000)
DA(15:0)
0 0 0 1 1
0 0 1 0
Write Application bits
DF(18:0)
(0)(0010)(0010)
Write Frequency bits
DT(10:0)
Write Test bits (pad protected)
0 0 1 1
(0011)
DA(15:0)
Read Application bits
0 1 0 0
(0100)
DF(15:0)
Read the 16 least significant Frequency bits
0 1 0 1
(0101)
0 1 1 0
(0110)
0 1 1 1
(0111)
1
DS(12:5)
DS(4:0)
DF(18: Read Chip version, Status and 3 most significant
16)
Frequency bits
DS(28:13)
(1111)(1)
Read Bist signature
DT(10:0)
Read Test bits
x
Discarded, not an instruction
All 1
Recovery instruction
Notes - The first “0” transmitted to the SX1243 is required to initialize communication
- The following 3 bits (highlighted in blue) determine the type of instruction
- The forthcoming bits (highlighted in green) define a protection pattern; any error in these bits voids the instruction
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5.2. APPLICATION Configuration Parameters
Name
Mode
Number
DA(15)
Description
Power
&Go 1
Power
&Go 2
0
Mode:
0 Æ Automatic mode
1 Æ Forced transmit mode
Modul
DA(14)
Modulation scheme:
0
1
1
0
0x06
Fdev=
+/-19.2kHz
Unused
1
1
0
1
100
100
0 Æ FSK
1 Æ OOK
Band
DA(13)
Fdev
DA(12:5)
Band 0, 310 to 450 MHz
Band 1, 860 to 870 MHz and 902 to 928 MHz
RF Frequency deviation in FSK mode only
See Table 7 for details
Pout
DA(4)
Output power range:
0 Æ 0 dBm
1 Æ 10 dBm
TOFFT
DA(3)
Period of inactivity on DATA before SX1243
enters Sleep mode in Automatic mode:
0 Æ 2 ms
1 Æ 20 ms
RES
DA(2:0)
Reserved
Table 10 APPLICATION Configuration Parameters
Note:
All changes to the APPLICATION parameters must be performed when the device is in Sleep mode, with the
exception of DA(15). Mode can be sequentially written to “1”, and then “0” while the device is in Transmit mode, to
speed up the turn off process and circumvent the TOFFT delay.
5.3. FREQUENCY Configuration Parameters
Name
Frf
Number
DF(18:0)
Description
Power
&Go 1
Power
&Go 2
RF operating frequency
0x42CAD
0x42C1C
See Table 7 for details
Frf=868.3 MHz
With 26 MHz
reference
Frf=433.92 MHz
With 26 MHz
reference
Table 11 FREQUENCY Configuration Parameters
If done in Sleep mode, the Frequency change instruction will be applied next time the SX1243 is turned on. If Frequency
change occurs during transmission, the automated Frequency Hopping sequence described in section [4.4.2] will take
place.
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5.4. Test Parameters
Ten Test bits DT(9:0) exist in the SX1243. They are only use for the industrial test of the device, and therefore they are pad
protected. It means that their value cannot be modified without applying a specific logical level to some of the SX1243 pads
during a write access.
5.5. Status Parameters
DS(12:5) are read-only bits, organized as follows:
Name
Number
Default
Advanced
Mode
Description
Power
&Go 1
RES
DS(28:13)
Reserved
Chip
Version
DS(12:5)
Chip identification number
RES
DS(4:2)
Reserved
-
TX_READY
DS(1)
TX_READY, see section [6.5.1]
0 Æ Transmitter not Ready
1 Æ Transmitter is Ready
-
RES
DS(0)
Reserved
-
Power
&Go 2
“0001 0001” --> V1A
Table 12 Status Read-Only Parameters
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5.6. Recovery Command
In the event of spurious activity (less than 24 clock cycles received) on the CTRL pin, control over the TWI interface can be
recovered in two possible ways:
t2
Recovery Command
DATA
CTRL
1st rising
edge on CTRL
24th rising
edge on CTRL
Figure 10. Quick Recovery Command
t1
t0
DATA
CTRL
1st rising edge
24th rising edge
Figure 11. Pulsed Recovery Command
Notes - If t2 < 5 us, the SX1243 will not turn into Tx mode during the recovery command (if not previously in Tx mode)
- If t1 < 5 us, with t0 > 5 us, the SX1243 will not turn into Tx mode in the second scenario of recovery command
- During the Pulsed recovery command, t0 timing does not have any upper limit
- If t1 or t2 exceeds 5us, the recovery command will still be successful, but the transmitter will momentarily turn on
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6. Application Information
6.1. Crystal Specification
The SX1243 is designed to operate with a low-cost 22, 24 or 26 MHz crystal
Table 13 SX1243 Quartz Crystal Reference Oscillator Specification
Symbol
Description
Min
Typ
Max
Unit
FXOSC
Crystal Frequency
-
22
24
26
-
MHz
LM
Crystal Motional Inductance
-
14.970
13.700
12.655
-
mH
CM
Crystal Motional Capacitance
-
3.495
3.209
2.962
-
fF
RS
Crystal Serial Resistance
-
20
100
Ohms
C0
Crystal Shunt Capacitance
-
1.0
7.0
pF
CL
Load Capacitance
-
15
-
pF
6.2. Evaluation Module
Figure 12. Evaluation Board Schematic
The evaluation module, presented in Figure 12, allows for the seamless evaluation of the SX1243 circuit. Several BOM
options are offered to evaluate the performance in all frequency bands.
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The SX1243 reference design uses a tiny footprint of 16 x 6 mm, allowing for compact implementations on 2-layer PC
Boards.
Figure 13. Evaluation Board Layout Top, Bottom Views
The following BOMs guarantee that the SX1243 product will be able to meet all regional regulatory requirements, with
significant margin (more than 10dB) on the rejection of harmonics and spurs.
Label
L1
L2
L3
L4
C1
C2
C3
C4
C5
C6
C7
C8
Decoupling
C9
R5
Delayed
C10
POR
L5
Antenna
C11
Match
C12
Inductor count
Capacitor count
Resistor count
PA Matching and
Harmonic Filtering
Usage
350 MHz
120nH
39nH
15nH
0 Ohm
2.2pF
100pF
8.2pF
3.3pF
8.2pF
100pF
100nF
-
433 MHz
120nH
33nH
15nH
0 Ohm
0.5pF
100pF
8.2pF
2.2pF
8.2pF
100pF
100nF
-
915 MHz
868 MHz @+10dBm
22nH
22nH
12nH
12nH
4.7nH
6.8nH
8.2nH
0 Ohm
0.5pF
33pF
18pF
1.8pF
5.6pF
1.5pF
1.8pF
2.2pF
18pF
100pF
100pF
100nF
100nF
-
915 MHz
@0dBm
22nH
12nH
6.8nH
6.8nH
0.5pF
18pF
5.6pF
2.2pF
18pF
100pF
100nF
-
Type
Tolerance
LQG15xxx
NPO
Standard tolerance
NPO
X7R
-
Antenna dependant
3
7
1
3
7
1
4
7
0
3
6
1
4
7
0
Figure 14. Evaluation Board BOMs
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Notes - The matching centered at 350 MHz offers a flat performance from 315 to 390 MHz, but could be modified to
slightly improve efficiency at any frequency inbetween
- The 915 MHz @10dBm BOM is dedicated to systems running under CFR Part 15.247, either Frequency Hopping
Spread Spectrum or Digital Modulation Techniques operation
- The 915 MHz @0dBm BOM is dedicated to systems running under CFR Part 15.249
6.3. NRESET Pin
When required, the pin NRESET can be controlled externally, to allow for:
either a delayed Power On Reset (POR) cycle of the SX1243, allowing for the companion micro to reset and assign its
port directions. This is achieved by connecting a R/C time constant to the NRESET pin.
or an On-the-go Reset of the SX1243 at any moment in time, if required by the application. This is achieved by pulling
the NRESET pin low for more than 100 microseconds, then releasing it to high impedance (normal termination).
6.4. TX_READY Pin
For timing critical applications, TX_READY pin can be useful to know precisely when the transmitter is ready for operation
and therefore save energy. As an option TX_READY can be connected to inform the companion device that the PA ramp
up phase has been terminated, hence the SX1243 is ready for data transmission.
6.5. Low Power Optimization
The SX1243 is designed to reduce the cost of the RF transmitter functionnality. To this end, a single DATA signal can be
enough to operate the transmitter, in any of the two Power & Go modes. In this situation, TS_START and TOFFT timings,
tabulated in Section 2.4, must be respected, leading to significant periods of time during which the transmitter is On and no
valuable information is transmitted.
For more demanding applications where energy usage is critical, the SX1243 offers hardware and software support to
accurately control the transmitter On time, and therefore save energy:
6.5.1. 2 Connections: CTRL, DATA
If the two signals of the TWI interface can be controlled by the host microcontroller, Tx On time and energy usage can be
optimized as follows:
At the device turn on, instead of waiting for TS_TR (2ms max, but XTAL dependant), the status flag TX_READY can be
polled on the TWI interface. As soon as the TX_READY flag is set, the microcontroller can start toggling DATA to
transmit the useful packet. This method is only valid in Forced Tx mode.
At the device turn off, the user can immediately turn off the transmitter after the transmission of packet, assuming that
the Forced Transmit mode was used.
6.5.2. 3 Connections: CTRL, DATA, TX_READY
In applications where the number of connections between the microcontroller and the RF chip is less critical, TX_READY
pin can be connected to either a GPIO port, or an external interrupt port of the micro. The two optimizations described in
the former subsection will also be possible.
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7. SX1243 Packaging
7.1. Package Outline Drawing
Figure 15. Package Outline Drawing
7.2. Thermal Impedance
The thermal impedance of this package, calculated from a package in still air, on a 4-layer FR4 PCB, as per the Jedec
standard, is Theta ja = 67 °C/W typ.
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7.3. Land Pattern
Figure 16. Land Pattern
7.4. Tape & Reel Specification
Figure 17. Tape & Reel Specification, DFN Package
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8. Revision History
Table 14 Revision History
Revision
Date
1
January 2012 First FINAL release
Add Tape and Reel specification
Add Minimum Order Quantity
Add Thermal Impedance of the package
2
February 2012
Add digital pins specifications
Typographical corrections
Modify section [6.5.1]
3
May 2012
Adjust Electrical specifications
4
January 2013 Add Marking Diagram
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© Semtech 2013
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes
no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper
installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to
parameters beyond the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF
SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S
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Contact information
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E-mail: sales@semtech.com
Internet: http://www.semtech.com
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