SX1276/77/78/79
WIRELESS & SENSING PRODUCTS
DATASHEET
SX1276/77/78/79 - 137 MHz to 1020 MHz Low Power Long Range Transceiver
GENERAL DESCRIPTION
KEY PRODUCT FEATURES
The SX1276/77/78/79 transceivers feature the LoRa® long
range modem that provides ultra-long range spread
spectrum communication and high interference immunity
whilst minimising current consumption.
Using Semtech’s patented LoRa modulation technique
SX1276/77/78/79 can achieve a sensitivity of over -148dBm
using a low cost crystal and bill of materials. The high
sensitivity combined with the integrated +20 dBm power
amplifier yields industry leading link budget making it
optimal for any application requiring range or robustness.
LoRa provides significant advantages in both blocking and
selectivity over conventional modulation techniques, solving
the traditional design compromise between range,
interference immunity and energy consumption.
These devices also support high performance (G)FSK
modes for systems including WMBus, IEEE802.15.4g. The
SX1276/77/78/79 deliver exceptional phase noise,
selectivity, receiver linearity and IIP3 for significantly lower
current consumption than competing devices.
ORDERING INFORMATION
Part Number
Delivery
MOQ / Multiple
SX1276IMLTRT
T&R
3000 pieces
SX1277IMLTRT
T&R
3000 pieces
SX1278IMLTRT
T&R
3000 pieces
SX1279IMLTRT
T&R
3000 pieces
SX1276WS1
Wafer Form
1 Wafer (2000 dies)
1. For Wafer deliveries, refer to the corresponding “Wafer Delivery
Specification”
LoRa® Modem
168 dB maximum link budget
+20 dBm - 100 mW constant RF output vs. V supply
+14 dBm high efficiency PA
Programmable bit rate up to 300 kbps
High sensitivity: down to -148 dBm
Bullet-proof front end: IIP3 = -11 dBm
Excellent blocking immunity
Low RX current of 9.9 mA, 200 nA register retention
Fully integrated synthesizer with a resolution of 61 Hz
FSK, GFSK, MSK, GMSK, LoRa® and OOK modulation
Built-in bit synchronizer for clock recovery
Preamble detection
127 dB Dynamic Range RSSI
Automatic RF Sense and CAD with ultra-fast AFC
Packet engine up to 256 bytes with CRC
Built-in temperature sensor and low battery indicator
APPLICATIONS
Automated Meter Reading.
Home and Building Automation.
Wireless Alarm and Security Systems.
Industrial Monitoring and Control
Long range Irrigation Systems
QFN 28 Package - Operating Range [-40;+85°C]
Pb-free, Halogen free, RoHS/WEEE compliant product
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Table of contents
Section
1.
2.
Page
General Description ................................................................................................................................................. 9
1.1.
Simplified Block Diagram ................................................................................................................................. 9
1.2.
Product Versions ............................................................................................................................................10
1.3.
Pin Diagram ................................................................................................................................................... 10
1.4.
Pin Description ...............................................................................................................................................11
1.5.
Package Marking ............................................................................................................................................12
Electrical Characteristics .......................................................................................................................................
2.1.
ESD Notice ....................................................................................................................................................
2.2.
Absolute Maximum Ratings ...........................................................................................................................
2.3.
Operating Range............................................................................................................................................
2.4.
Thermal Properties ........................................................................................................................................
2.5.
13
13
13
13
13
Chip Specification ..........................................................................................................................................14
2.5.1. Power Consumption .................................................................................................................................. 14
2.5.2. Frequency Synthesis................................................................................................................................. 14
2.5.3. FSK/OOK Mode Receiver .........................................................................................................................16
2.5.4. FSK/OOK Mode Transmitter ..................................................................................................................... 17
2.5.5. Electrical Specification for LoRa Modulation ............................................................................................. 19
2.5.6. Digital Specification ................................................................................................................................... 22
3.
SX1276/77/78/79 Features.................................................................................................................................... 23
3.1.
LoRa® Modem............................................................................................................................................... 24
3.2.
FSK/OOK Modem .......................................................................................................................................... 24
4.
SX1276/77/78/79 Digital Electronics ..................................................................................................................... 25
4.1.
The LoRa® Modem........................................................................................................................................ 25
4.1.1. Link Design Using the LoRa® Modem ......................................................................................................26
4.1.2. LoRa® Digital Interface .............................................................................................................................34
4.1.3. Operation of the LoRa® Modem ............................................................................................................... 36
4.1.4. Frequency Settings ................................................................................................................................... 36
4.1.5. Frequency Error Indication ........................................................................................................................ 37
4.1.6. LoRa AFC.................................................................................................................................................. 37
4.1.7. Digital IO Pin Mapping............................................................................................................................... 45
4.1.8. Modem Status Indicators........................................................................................................................... 46
4.2.
FSK/OOK Modem .......................................................................................................................................... 46
4.2.1. Bit Rate Setting ......................................................................................................................................... 46
4.2.2. FSK/OOK Transmission ............................................................................................................................ 47
4.2.3. FSK/OOK Reception ................................................................................................................................. 48
4.2.4. Operating Modes in FSK/OOK Mode ........................................................................................................ 54
4.2.5. Startup Times ............................................................................................................................................56
4.2.6. Receiver Startup Options .......................................................................................................................... 59
4.2.7. Receiver Restart Methods......................................................................................................................... 60
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Table of contents
Section
Page
4.2.8. Top Level Sequencer ................................................................................................................................ 61
4.2.9. Data Processing in FSK/OOK Mode ......................................................................................................... 65
4.2.10. FIFO ........................................................................................................................................................ 66
4.2.11. Digital IO Pins Mapping ...........................................................................................................................69
4.2.12. Continuous Mode ....................................................................................................................................70
4.2.13. Packet Mode ........................................................................................................................................... 71
4.2.14. io-homecontrol® Compatibility Mode ...................................................................................................... 79
4.3.
5.
SPI Interface ..................................................................................................................................................80
SX1276/77/78/79 Analog & RF Frontend Electronics............................................................................................
5.1.
Power Supply Strategy ..................................................................................................................................
5.2.
Low Battery Detector .....................................................................................................................................
5.3.
Frequency Synthesis .....................................................................................................................................
5.3.1. Crystal Oscillator .......................................................................................................................................
5.3.2. CLKOUT Output ........................................................................................................................................
5.3.3. PLL ............................................................................................................................................................
5.3.4. RC Oscillator .............................................................................................................................................
5.4.
81
81
81
81
81
82
82
82
Transmitter Description ..................................................................................................................................83
5.4.1. Architecture Description ............................................................................................................................ 83
5.4.2. RF Power Amplifiers.................................................................................................................................. 83
5.4.3. High Power +20 dBm Operation ............................................................................................................... 84
5.4.4. Over Current Protection ............................................................................................................................85
5.5.
Receiver Description...................................................................................................................................... 85
5.5.1. Overview ................................................................................................................................................... 85
5.5.2. Receiver Enabled and Receiver Active States.......................................................................................... 85
5.5.3. Automatic Gain Control In FSK/OOK Mode .............................................................................................. 85
5.5.4. RSSI in FSK/OOK Mode ........................................................................................................................... 86
5.5.5. RSSI and SNR in LoRa Mode ................................................................................................................... 87
5.5.6. Channel Filter ............................................................................................................................................ 88
5.5.7. Temperature Measurement....................................................................................................................... 89
6.
Description of the Registers................................................................................................................................... 90
6.1.
Register Table Summary ............................................................................................................................... 90
6.2.
FSK/OOK Mode Register Map .......................................................................................................................93
6.3.
Band Specific Additional Registers .............................................................................................................. 106
6.4.
LoRa Mode Register Map ............................................................................................................................ 108
7.
Application Information ........................................................................................................................................ 116
7.1.
Crystal Resonator Specification................................................................................................................... 116
7.2.
Reset of the Chip ......................................................................................................................................... 116
7.2.1. POR......................................................................................................................................................... 116
7.2.2. Manual Reset 117
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Table of contents
Section
Page
7.3.
Top Sequencer: Listen Mode Examples ...................................................................................................... 117
7.3.1. Wake on Preamble Interrupt ................................................................................................................... 117
7.3.2. Wake on SyncAddress Interrupt ..............................................................................................................120
7.4.
Top Sequencer: Beacon Mode ....................................................................................................................123
7.4.1. Timing diagram........................................................................................................................................ 123
7.4.2. Sequencer Configuration......................................................................................................................... 123
7.5.
Example CRC Calculation ........................................................................................................................... 125
7.6.
Example Temperature Reading ...................................................................................................................126
8.
Packaging Information ......................................................................................................................................... 128
8.1.
Package Outline Drawing ............................................................................................................................ 128
8.2.
Recommended Land Pattern ....................................................................................................................... 129
8.3.
Tape & Reel Information .............................................................................................................................. 130
8.4.
Wafer Delivery ............................................................................................................................................. 130
9.
Revision History................................................................................................................................................... 131
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Table of contents
Section
Page
Table 1. SX1276/77/78/79 Device Variants and Key Parameters .................................................................................10
Table 2. Pin Description ................................................................................................................................................11
Table 3. Absolute Maximum Ratings .............................................................................................................................13
Table 4. Operating Range .............................................................................................................................................13
Table 5. Thermal Properties ..........................................................................................................................................13
Table 6. Power Consumption Specification ...................................................................................................................14
Table 7. Frequency Synthesizer Specification ..............................................................................................................14
Table 8. FSK/OOK Receiver Specification ....................................................................................................................16
Table 9. Transmitter Specification .................................................................................................................................17
Table 10. LoRa Receiver Specification .........................................................................................................................19
Table 11. Digital Specification .......................................................................................................................................22
Table 12. Example LoRa® Modem Performances, 868MHz Band ...............................................................................25
Table 13. Range of Spreading Factors ..........................................................................................................................27
Table 14. Cyclic Coding Overhead ................................................................................................................................27
Table 15. LoRa Bandwidth Options ...............................................................................................................................28
Table 16. LoRa® Operating Mode Functionality ...........................................................................................................36
Table 17. LoRa CAD Consumption Figures ..................................................................................................................45
Table 18. DIO Mapping LoRa® Mode ...........................................................................................................................46
Table 19. Bit Rate Examples .........................................................................................................................................47
Table 20. Preamble Detector Settings ...........................................................................................................................53
Table 21. RxTrigger Settings to Enable Timeout Interrupts ..........................................................................................54
Table 22. Basic Transceiver Modes ..............................................................................................................................54
Table 23. Receiver Startup Time Summary ..................................................................................................................57
Table 24. Receiver Startup Options ..............................................................................................................................60
Table 25. Sequencer States ..........................................................................................................................................61
Table 26. Sequencer Transition Options .......................................................................................................................62
Table 27. Sequencer Timer Settings .............................................................................................................................63
Table 28. Status of FIFO when Switching Between Different Modes of the Chip .........................................................67
Table 29. DIO Mapping, Continuous Mode ...................................................................................................................69
Table 30. DIO Mapping, Packet Mode ..........................................................................................................................69
Table 31. CRC Description ...........................................................................................................................................77
Table 32. Frequency Bands ..........................................................................................................................................82
Table 33. Power Amplifier Mode Selection Truth Table ................................................................................................83
Table 34. High Power Settings ......................................................................................................................................84
Table 35. Operating Range, +20dBm Operation ...........................................................................................................84
Table 36. Operating Range, +20dBm Operation ...........................................................................................................84
Table 37. Trimming of the OCP Current ........................................................................................................................85
Table 38. LNA Gain Control and Performances ............................................................................................................86
Table 39. RssiSmoothing Options .................................................................................................................................86
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Table of contents
Section
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Page
Available RxBw Settings ................................................................................................................................88
Registers Summary .......................................................................................................................................90
Register Map .................................................................................................................................................93
Low Frequency Additional Registers ...........................................................................................................106
High Frequency Additional Registers ..........................................................................................................107
Crystal Specification ....................................................................................................................................116
Listen Mode with PreambleDetect Condition Settings .................................................................................119
Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................119
Listen Mode with SyncAddress Condition Settings .....................................................................................122
Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................122
Beacon Mode Settings ................................................................................................................................124
Revision History ...........................................................................................................................................131
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Table of contents
Section
Page
Figure 1. Block Diagram .................................................................................................................................................9
Figure 2. Pin Diagrams .................................................................................................................................................10
Figure 3. Marking Diagram ...........................................................................................................................................12
Figure 4. SX1276/77/78/79 Block Schematic Diagram ................................................................................................23
Figure 5. LoRa® Modem Connectivity ..........................................................................................................................26
Figure 6. LoRa® Packet Structure ................................................................................................................................29
Figure 7. Interrupts Generated in the Case of Successful Frequency Hopping Communication. ................................33
Figure 8. LoRa® Data Buffer ........................................................................................................................................34
Figure 9. LoRa® Modulation Transmission Sequence. ................................................................................................38
Figure 10. LoRa® Receive Sequence. ........................................................................................................................39
Figure 11. LoRa® CAD Flow ........................................................................................................................................43
Figure 12. CAD Time as a Function of Spreading Factor .............................................................................................44
Figure 13. Consumption Profile of the LoRa CAD Process ..........................................................................................45
Figure 14. OOK Peak Demodulator Description ...........................................................................................................49
Figure 15. Floor Threshold Optimization ......................................................................................................................50
Figure 16. Bit Synchronizer Description .......................................................................................................................51
Figure 17. Startup Process ...........................................................................................................................................56
Figure 18. Time to RSSI Sample ..................................................................................................................................57
Figure 19. Tx to Rx Turnaround ...................................................................................................................................58
Figure 20. Rx to Tx Turnaround ...................................................................................................................................58
Figure 21. Receiver Hopping ........................................................................................................................................59
Figure 22. Transmitter Hopping ....................................................................................................................................59
Figure 23. Timer1 and Timer2 Mechanism ...................................................................................................................63
Figure 24. Sequencer State Machine ...........................................................................................................................64
Figure 25. SX1276/77/78/79 Data Processing Conceptual View .................................................................................65
Figure 26. FIFO and Shift Register (SR) ......................................................................................................................66
Figure 27. FifoLevel IRQ Source Behavior ...................................................................................................................67
Figure 28. Sync Word Recognition ...............................................................................................................................68
Figure 29. Continuous Mode Conceptual View ............................................................................................................70
Figure 30. Tx Processing in Continuous Mode .............................................................................................................70
Figure 31. Rx Processing in Continuous Mode ............................................................................................................71
Figure 32. Packet Mode Conceptual View ...................................................................................................................72
Figure 33. Fixed Length Packet Format .......................................................................................................................73
Figure 34. Variable Length Packet Format ...................................................................................................................74
Figure 35. Unlimited Length Packet Format .................................................................................................................74
Figure 36. Manchester Encoding/Decoding .................................................................................................................78
Figure 37. Data Whitening Polynomial .........................................................................................................................79
Figure 38. SPI Timing Diagram (single access) ...........................................................................................................80
Figure 39. TCXO Connection .......................................................................................................................................81
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Table of contents
Section
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Page
RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................83
Temperature Sensor Response ..................................................................................................................89
POR Timing Diagram ................................................................................................................................116
Manual Reset Timing Diagram ..................................................................................................................117
Listen Mode: Principle ...............................................................................................................................117
Listen Mode with No Preamble Received .................................................................................................118
Listen Mode with Preamble Received .......................................................................................................118
Wake On PreambleDetect State Machine .................................................................................................119
Listen Mode with no SyncAddress Detected .............................................................................................120
Listen Mode with Preamble Received and no SyncAddress .....................................................................120
Listen Mode with Preamble Received & Valid SyncAddress ....................................................................121
Wake On SyncAddress State Machine .....................................................................................................121
Beacon Mode Timing Diagram ..................................................................................................................123
Beacon Mode State Machine ....................................................................................................................123
Example CRC Code ..................................................................................................................................125
Example Temperature Reading ................................................................................................................126
Example Temperature Reading (continued) .............................................................................................127
Package Outline Drawing ..........................................................................................................................128
Recommended Land Pattern ....................................................................................................................129
Tape and Reel Information ........................................................................................................................130
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1. General Description
The SX1276/77/78/79 incorporates the LoRa spread spectrum modem which is capable of achieving significantly longer
range than existing systems based on FSK or OOK modulation. At maximum data rates of LoRa the sensitivity is 8dB
better than FSK, but using a low cost bill of materials with a 20ppm XTAL LoRa can improve receiver sensitivity by more
than 20dB compared to FSK. LoRa also provides significant advances in selectivity and blocking performance, further
improving communication reliability. For maximum flexibility the user may decide on the spread spectrum modulation
bandwidth (BW), spreading factor (SF) and error correction rate (CR). Another benefit of the spread modulation is that
each spreading factor is orthogonal - thus multiple transmitted signals can occupy the same channel without interfering.
This also permits simple coexistence with existing FSK based systems. Standard GFSK, FSK, OOK, and GMSK
modulation is also provided to allow compatibility with existing systems or standards such as wireless MBUS and IEEE
802.15.4g.
The SX1276 and SX1279 offer bandwidth options ranging from 7.8 kHz to 500 kHz with spreading factors ranging from 6 to
12, and covering all available frequency bands. The SX1277 offers the same bandwidth and frequency band options with
spreading factors from 6 to 9. The SX1278 offers bandwidths and spreading factor options, but only covers the lower UHF
bands.
1.1. Simplified Block Diagram
Figure 1. Block Diagram
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1.2. Product Versions
The features of the four product variants are detailed in the following table.
Table 1
SX1276/77/78/79 Device Variants and Key Parameters
Part Number
Frequency Range
Spreading Factor
Bandwidth
Effective Bitrate
Est. Sensitivity
SX1276
137 - 1020 MHz
6 - 12
7.8 - 500 kHz
.018 - 37.5 kbps
-111 to -148 dBm
SX1277
137 - 1020 MHz
6-9
7.8 - 500 kHz
0.11 - 37.5 kbps
-111 to -139 dBm
SX1278
137 - 525 MHz
6- 12
7.8 - 500 kHz
.018 - 37.5 kbps
-111 to -148 dBm
SX1279
137 - 960MHz
6- 12
7.8 - 500 kHz
.018 - 37.5 kbps
-111 to -148 dBm
1.3. Pin Diagram
22 GND
23 GND
24 VBAT_RF
25 VR_PA
26 GND
27 PA_BOOST
28 RFO_LF
22 RFO_HF
23 GND
24 VBAT_RF
25 VR_PA
26 GND
27 PA_BOOST
28 RFO_LF
The following diagram shows the pin arrangement of the QFN package, top view.
1 RFI_LF
21 RFI_HF
1 RFI_LF
21 GND
2 VR_ANA
20 RXTX/RFMOD
2 VR_ANA
20 RXTX/RFMOD
3 VBAT_ANA
19 NSS
3 VBAT_ANA
19 NSS
18 MOSI
4 VR_DIG
5 XTA
17 MISO
5 XTA
17 MISO
6 XTB
16 SCK
6 XTB
16 SCK
7 NRESET
15 GND
7 NRESET
15 GND
SX1276/77/79
14 VBAT_DIG
13 DIO5
18 MOSI
12 DIO4
11 DIO3
10 DIO2
9 DIO1
0 GND
8 DIO0
14 VBAT_DIG
13 DIO5
12 DIO4
10 DIO2
9 DIO1
8 DIO0
11 DIO3
0 GND
4 VR_DIG
SX1278
Figure 2. Pin Diagrams
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1.4. Pin Description
Table 2
Pin Description
Number
Name
Type
Description
SX1276/77/79/(78)
SX1276/77/79/(78)
SX1276/77/79/(78)
0
GROUND
-
Exposed ground pad
1
RFI_LF
I
RF input for bands 2&3
2
VR_ANA
-
Regulated supply voltage for analogue circuitry
3
VBAT_ANA
-
Supply voltage for analogue circuitry
4
VR_DIG
-
Regulated supply voltage for digital blocks
5
XTA
I/O
XTAL connection or TCXO input
6
XTB
I/O
XTAL connection
7
NRESET
I/O
Reset trigger input
8
DIO0
I/O
Digital I/O, software configured
9
DIO1/DCLK
I/O
Digital I/O, software configured
10
DIO2/DATA
I/O
Digital I/O, software configured
11
DIO3
I/O
Digital I/O, software configured
12
DIO4
I/O
Digital I/O, software configured
13
DIO5
I/O
Digital I/O, software configured
14
VBAT_DIG
-
Supply voltage for digital blocks
15
GND
-
Ground
16
SCK
I
SPI Clock input
17
MISO
O
SPI Data output
18
MOSI
I
SPI Data input
19
NSS
I
SPI Chip select input
20
RXTX/RF_MOD
O
Rx/Tx switch control: high in Tx
21
RFI_HF (GND)
I (-)
RF input for band 1 (Ground)
22
RFO_HF (GND)
O (-)
RF output for band 1 (Ground)
23
GND
-
Ground
24
VBAT_RF
-
Supply voltage for RF blocks
25
VR_PA
-
Regulated supply for the PA
26
GND
-
Ground
27
PA_BOOST
O
Optional high-power PA output, all frequency bands
28
RFO_LF
O
RF output for bands 2&3
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1.5. Package Marking
Figure 3. Marking Diagram
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2. Electrical Characteristics
2.1. ESD Notice
The SX1276/77/78/79 is a high performance radio frequency device. It satisfies:
Class 2 of the JEDEC standard JESD22-A114 (Human Body Model) on all pins.
Class III of the JEDEC standard JESD22-C101 (Charged Device Model) on all pins
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 3
Absolute Maximum Ratings
Symbol
Description
Min
Max
Unit
VDDmr
Supply Voltage
-0.5
3.9
Tmr
Temperature
-55
+115
°C
Tj
Junction temperature
-
+125
°C
Pmr
RF Input Level
-
+10
dBm
Min
Max
Note
V
Specific ratings apply to +20 dBm operation (see Section 3.4.3).
2.3. Operating Range
Table 4
Operating Range
Symbol
Description
Unit
VDDop
Supply voltage
1.8
3.7
V
Top
Operational temperature range
-40
+85
°C
Clop
Load capacitance on digital ports
-
25
pF
ML
RF Input Level
-
+10
dBm
Note
A specific supply voltage range applies to +20 dBm operation (see Section 3.4.3).
2.4. Thermal Properties
Table 5
Thermal Properties
Symbol
Description
Min
Typ
Max
Unit
THETA_JA
Package ja (Junction to ambient)
-
22.185
-
°C/W
THETA_JC
Package jc (Junction to case ground paddle)
-
0.757
-
°C/W
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2.5. Chip Specification
The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage
VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 169/434/868/915 MHz (see specific indication), Pout =
+13dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50
Ohm impedance, shared Rx and Tx path matching, unless otherwise specified.
Note
Specification whose symbol is appended with “_LF” corresponds to the performance in Band 2 and/or Band 3, as
described in section 3.3.3. “_HF” refers to the upper Band 1
2.5.1. Power Consumption
Table 6 Power Consumption Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
-
0.2
1
uA
IDDSL
Supply current in Sleep mode
IDDIDLE
Supply current in Idle mode
RC oscillator enabled
-
1.5
-
uA
IDDST
Supply current in Standby mode
Crystal oscillator enabled
-
1.6
1.8
mA
IDDFS
Supply current in Synthesizer
mode
FSRx
-
5.8
-
mA
IDDR
Supply current in Receive mode
LnaBoost Off, band 1
LnaBoost On, band 1
Bands 2&3
-
10.8
11.5
12.0
-
mA
IDDT
Supply current in Transmit mode
with impedance matching
RFOP = +20 dBm, on PA_BOOST
RFOP = +17 dBm, on PA_BOOST
RFOP = +13 dBm, on RFO_LF/HF pin
RFOP = + 7 dBm, on RFO_LF/HF pin
-
120
87
29
20
-
mA
mA
mA
mA
2.5.2. Frequency Synthesis
Table 7 Frequency Synthesizer Specification
Symbol
Description
Conditions
Band 3
Band 2
Band 1
Typ
Max
Unit
137
410
862 (*779)
-
175 (*160)
525 (*480)
1020 (*960)
MHz
FR
Synthesizer frequency range
FXOSC
Crystal oscillator frequency
-
32
-
MHz
TS_OSC
Crystal oscillator wake-up time
-
250
-
us
TS_FS
Frequency synthesizer wake-up
time to PllLock signal
-
60
-
us
Rev. 7 - May 2020
©2020 Semtech Corporation
Programmable
(*for SX1279)
Min
From Standby mode
Page 14
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WIRELESS & SENSING PRODUCTS
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200 kHz step
1 MHz step
5 MHz step
7 MHz step
12 MHz step
20 MHz step
25 MHz step
-
20
20
50
50
50
50
50
-
us
us
us
us
us
us
us
TS_HOP
Frequency synthesizer hop time
at most 10 kHz away from the
target frequency
FSTEP
Frequency synthesizer step
FSTEP = FXOSC/219
-
61.0
-
Hz
FRC
RC Oscillator frequency
After calibration
-
62.5
-
kHz
BRF
Bit rate, FSK
Programmable values (1)
1.2
-
300
kbps
BRA
Bit rate Accuracy, FSK
ABS(wanted BR - available BR)
-
-
250
ppm
BRO
Bit rate, OOK
Programmable
1.2
-
32.768
kbps
BR_L
Bit rate, LoRa Mode
From SF6, BW=500kHz to
SF12, BW=7.8kHz
0.018
-
37.5
kbps
FDA
Frequency deviation, FSK (1)
Programmable
FDA + BRF/2 =< 250 kHz
0.6
-
200
kHz
Note: For Maximum Bit rate, the maximum modulation index is 0.5.
Rev. 7 - May 2020
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2.5.3. FSK/OOK Mode Receiver
All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a
PN15 sequence. Sensitivities are reported for a 0.1% BER (with Bit Synchronizer enabled), unless otherwise specified.
Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR,
IIP2, IIP3 and AMR tests is set 3 dB above the receiver sensitivity level.
Table 8
FSK/OOK Receiver Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
Direct tie of RFI and RFO pins,
shared Rx, Tx paths FSK sensitivity, highest LNA gain.
Bands 2&3
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-121
-117
-107
-108
-95
-
dBm
dBm
dBm
dBm
dBm
Split RF paths, the RF switch
insertion loss is not accounted for.
Bands 2&3
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-123
-119
-109
-110
-97
-
dBm
dBm
dBm
dBm
dBm
Direct tie of RFI and RFO pins,
shared Rx, Tx paths FSK sensitivity, highest LNA gain.
Band 1
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-119
-115
-105
-105
-92
-
dBm
dBm
dBm
dBm
dBm
Split RF paths, LnaBoost is turned
on, the RF switch insertion loss is
not accounted for.
Band 1
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-123
-119
-109
-109
-96
-
dBm
dBm
dBm
dBm
dBm
RFS_O
OOK sensitivity, highest LNA gain
shared Rx, Tx paths
BR = 4.8 kb/s
BR = 32 kb/s
-
-117
-108
-
dBm
dBm
CCR
Co-Channel Rejection, FSK
-
-9
-
dB
-
50
56
60
-
dB
dB
dB
RFS_F_LF
RFS_F_HF
ACR
Adjacent Channel Rejection
FDA = 5 kHz, BR=4.8kb/s
Offset = +/- 25 kHz or +/- 50kHz
Band 1
Band 2
Band 3
BI_HF
Blocking Immunity, Band 1
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
71
76
84
-
dB
dB
dB
BI_LF
Blocking Immunity, Bands 2&3
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
71
72
78
-
dB
dB
dB
Rev. 7 - May 2020
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WIRELESS & SENSING PRODUCTS
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IIP2
2nd order Input Intercept Point
Unwanted tones are 20 MHz
above the LO
Highest LNA gain
-
+55
-
dBm
IIP3_HF
3rd order Input Intercept point
Unwanted tones are 1MHz and
1.995 MHz above the LO
Band 1
Highest LNA gain G1
LNA gain G2, 5dB sensitivity hit
-
-11
-6
-
dBm
dBm
Band 2
Highest LNA gain G1
LNA gain G2, 2.5dB sensitivity hit
-
-22
-15
-
dBm
dBm
-
-15
-11
-
dBm
dBm
2.7
-
250
kHz
-
50
-
dB
-
57
-
dB
-
-127
0
-
dBm
dBm
IIP3_LF
3rd order Input Intercept point
Unwanted tones are 1MHz and
1.995 MHz above the LO
Band 3
Highest LNA gain G1
LNA gain G2, 2.5dB sensitivity hit
BW_SSB
Single Side channel filter BW
Programmable
IMR
Image Rejection
Wanted signal 3dB over sensitivity
BER=0.1%
IMA
Image Attenuation
DR_RSSI
RSSI Dynamic Range
AGC enabled
*
RxBw = 83 kHz (Single Side Bandwidth)
**
RxBw = 50 kHz (Single Side Bandwidth)
***
RxBw = 250 kHz (Single Side Bandwidth)
Min
Max
2.5.4. FSK/OOK Mode Transmitter
Table 9 Transmitter Specification
Symbol
Description
RF_OP
RF output power in 50 ohms
on RFO pin (High efficiency PA).
ΔRF_
OP_V
RF output power stability on RFO
pin versus voltage supply.
RF_OPH
RF output power in 50 ohms, on
PA_BOOST pin (Regulated PA).
RF_OPH_
MAX
Max RF output power, on
PA_BOOST pin
ΔRF_
OPH_V
RF output power stability on PA_BOOST pin versus voltage supply.
ΔRF_T
RF output power stability versus
temperature on PA_BOOST pin.
Rev. 7 - May 2020
©2020 Semtech Corporation
Conditions
Programmable with steps
Max
Min
VDD = 2.5 V to 3.3 V
VDD = 1.8 V to 3.7 V
Programmable with 1dB steps
Max
Min
High power mode
VDD = 2.4 V to 3.7 V
From T = -40 °C to +85 °C
Page 17
Min
Typ
Max
Unit
-
+14
-1
-
dBm
dBm
-
3
8
-
dB
dB
-
+17
+2
-
dBm
dBm
-
+20
-
dBm
-
+/-1
-
dB
-
+/-1
-
dB
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169 MHz, Band 3
433 MHz, Band 2
PHN
Transmitter Phase Noise
868/915 MHz, Band 1
10kHz Offset
50kHz Offset
400kHz Offset
1MHz Offset
-
-118
-118
-128
-134
-
dBc/
Hz
10kHz Offset
50kHz Offset
400kHz Offset
1MHz Offset
-
-110
-110
-122
-129
-
dBc/
Hz
10kHz Offset
50kHz Offset
400kHz Offset
1MHz Offset
-
-103
-103
-115
-122
-
dBc/
Hz
dBm
ACP
Transmitter adjacent channel
power (measured at 25 kHz offset)
BT=1. Measurement conditions as
defined by EN 300 220-1 V2.3.1
-
-
-37
TS_TR
Transmitter wake up time, to the
first rising edge of DCLK
Frequency Synthesizer enabled, PaRamp = 10us, BR = 4.8 kb/s
-
120
-
Rev. 7 - May 2020
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2.5.5. Electrical Specification for LoRa Modulation
The table below gives the electrical specifications for the transceiver operating with LoRa modulation. Following conditions
apply unless otherwise specified:
Supply voltage = 3.3 V
Temperature = 25° C
fXOSC = 32 MHz
bandwidth (BW) = 125 kHz
Spreading Factor (SF) = 12
Error Correction Code (EC) = 4/6
Packet Error Rate (PER)= 1%
CRC on payload enabled
Output power = 13 dBm in transmission
Payload length = 64 bytes
Preamble Length = 12 symbols (programmed register PreambleLength=8)
With matched impedances
Table 10 LoRa Receiver Specification
Symbol
Description
Conditions
Min.
Typ
Max
Unit
Bands 2&3, BW=7.8 to 62.5 kHz
Bands 2&3, BW = 125 kHz
Bands 2&3, BW = 250 kHz
Bands 2&3, BW = 500 kHz
-
11.0
11.5
12.4
13.8
-
mA
mA
mA
mA
Band 1, BW=7.8 to 62.5 kHz
Band 1, BW = 125 kHz
Band 1, BW = 250 kHz
Band 1, BW = 500 kHz
-
9.9
10.3
11.1
12.6
-
mA
mA
mA
mA
IDDR_L
Supply current in receiver LoRa
mode, LnaBoost off
IDDT_L
Supply current in transmitter mode
RFOP = 13 dBm
RFOP = 7 dBm
-
28
20
-
mA
mA
IDDT_H_L
Supply current in transmitter mode
with an external impedance
transformation
Using PA_BOOST pin
RFOP = 17 dBm
-
90
-
mA
BI_L
Blocking immunity,
CW interferer
offset = +/- 1 MHz
offset = +/- 2 MHz
offset = +/- 10 MHz
-
89
94
100
-
dB
dB
dB
IIP2_L
2nd order Input Intercept Point
Unwanted tones are 20 MHz above
the LO
Highest LNA gain
-
+55
-
dBm
IIP3_L_HF
3rd order Input Intercept point
Band 1
Unwanted tones are 1MHz and 1.995 Highest LNA gain G1
MHz above the LO
LNA gain G2, 5dB sensitivity hit
-
-11
-6
-
dBm
dBm
Rev. 7 - May 2020
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WIRELESS & SENSING PRODUCTS
Symbol
DATASHEET
Description
Conditions
Min.
Typ
Max
-
-22
-15
-
Unit
IIP3_L_LF
Band 2
3rd order Input Intercept point
Unwanted tones are 1MHz and 1.995 Highest LNA gain G1
LNA gain G2,2.5dB sensitivity hit
MHz above the LO
RFS_L10_HF
RF sensitivity, Long-Range Mode,
highest LNA gain, LnaBoost for Band
1, using split Rx/Tx path
10.4 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 11
-
-131
-134
-138
-146
-
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, LnaBoost for Band
1, using split Rx/Tx path
62.5 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-121
-126
-129
-132
-135
-137
-139
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, LnaBoost for Band
1, using split Rx/Tx path
125 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-118
-123
-126
-129
-132
-133
-136
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, LnaBoost for Band
1, using split Rx/Tx path
250 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-115
-120
-123
-125
-128
-130
-133
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RFS_L500_HF
RF sensitivity, Long-Range Mode,
highest LNA gain, LnaBoost for Band
1, using split Rx/Tx path
500 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-111
-116
-119
-122
-125
-128
-130
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RFS_L7.8_LF
RF sensitivity, Long-Range Mode,
highest LNA gain, Band 2 or 3, using
split Rx/Tx path
7.8 kHz bandwidth
SF = 12
SF = 11
-
-148
-145
-
dBm
dBm
RFS_L10_LF
RF sensitivity, Long-Range Mode,
highest LNA gain, Band 3,
10.4 kHz bandwidth
SF = 6
SF = 7
SF = 8
-
-132
-136
-138
-
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, Band 3,
62.5 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-123
-128
-131
-134
-135
-137
-140
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RFS_L62_HF
RFS_L125_HF
RFS_L250_HF
RFS_L62_LF
Rev. 7 - May 2020
©2020 Semtech Corporation
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dBm
dBm
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WIRELESS & SENSING PRODUCTS
Symbol
DATASHEET
Min.
Typ
Max
Unit
RF sensitivity, Long-Range Mode,
highest LNA gain, Band 3,
125 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-121
-125
-128
-131
-134
-136
-137
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, Band 3
250 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-118
-122
-125
-128
-131
-133
-134
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, Band 3
500 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-112
-118
-121
-124
-127
-129
-130
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
CCR_LCW
Co-channel rejection
Single CW tone = Sens +6 dB
1% PER
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
5
9.5
12
14.4
17
19.5
-
dB
dB
dB
dB
dB
dB
CCR_LL
Co-channel rejection
Interferer is a LoRa signal using
same BW and same SF.
Pw = Sensitivity + 3 dB
RFS_L125_LF
RFS_L250_LF
RFS_L500_LF
ACR_LCW
IMR_LCW
FERR_L
Description
Adjacent channel rejection
Conditions
-6
dB
Interferer is 1.5*BW_L from the
wanted signal center frequency
1% PER, Single CW tone =
Sens + 3 dB
SF = 7
SF = 12
-
60
72
-
dB
dB
Image rejection after calibration.
1% PER, Single CW tone =
Sens +3 dB
-
66
-
dB
Maximum tolerated frequency offset
between transmitter and receiver, no
sensitivity degradation, SF6 thru 12
All BW, +/-25% of BW
The tighter limit applies (see
below)
Maximum tolerated frequency offset
between transmitter and receiver, no
sensitivity degradation, SF10 thru 12
SF = 12
SF = 11
SF = 10
Rev. 7 - May 2020
©2020 Semtech Corporation
Page 21
+/-25%
-50
-100
-200
-
BW
50
100
200
ppm
ppm
ppm
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2.5.6. Digital Specification
Conditions: Temp = 25° C, VDD = 3.3 V, FXOSC = 32 MHz, unless otherwise specified.
Table 11 Digital Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
VIH
Digital input level high
0.8
-
-
VDD
VIL
Digital input level low
-
-
0.2
VDD
VOH
Digital output level high
Imax = 1 mA
0.9
-
-
VDD
VOL
Digital output level low
Imax = -1 mA
-
-
0.1
VDD
FSCK
SCK frequency
-
-
10
MHz
tch
SCK high time
50
-
-
ns
tcl
SCK low time
50
-
-
ns
trise
SCK rise time
-
5
-
ns
tfall
SCK fall time
-
5
-
ns
tsetup
MOSI setup time
From MOSI change to SCK rising
edge.
30
-
-
ns
thold
MOSI hold time
From SCK rising edge to MOSI
change.
20
-
-
ns
tnsetup
NSS setup time
From NSS falling edge to SCK rising
edge.
30
-
-
ns
tnhold
NSS hold time
From SCK falling edge to NSS rising
edge, normal mode.
100
-
-
ns
tnhigh
NSS high time between SPI
accesses
20
-
-
ns
T_DATA
DATA hold and setup time
250
-
-
ns
Rev. 7 - May 2020
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3. SX1276/77/78/79 Features
This section gives a high-level overview of the functionality of the SX1276/77/78/79 low-power, highly integrated
transceiver. The following figure shows a simplified block diagram of the SX1276/77/78/79.
Figure 4. SX1276/77/78/79 Block Schematic Diagram
SX1276/77/78/79 is a half-duplex, low-IF transceiver. Here the received RF signal is first amplified by the LNA. The LNA
inputs are single ended to minimize the external BoM and for ease of design. Following the LNA inputs, the conversion to
differential is made to improve the second order linearity and harmonic rejection. The signal is then down-converted to inphase and quadrature (I&Q) components at the intermediate frequency (IF) by the mixer stage. A pair of sigma delta ADCs
then perform data conversion, with all subsequent signal processing and demodulation performed in the digital domain.
The digital state machine also controls the automatic frequency correction (AFC), received signal strength indicator (RSSI)
and automatic gain control (AGC). It also features the higher-level packet and protocol level functionality of the top level
sequencer (TLS), only available with traditional FSK and OOK modulation schemes.
The frequency synthesizers generate the local oscillator (LO) frequency for both receiver and transmitter, one covering the
lower UHF bands (up to 525 MHz), and the other one covering the upper UHF bands (from 779 MHz). The PLLs are
optimized for user-transparent low lock time and fast auto-calibrating operation. In transmission, frequency modulation is
performed digitally within the PLL bandwidth. The PLL also features optional pre-filtering of the bit stream to improve
spectral purity.
SX1276/77/78/79 feature three distinct RF power amplifiers. Two of those, connected to RFO_LF and RFO_HF, can deliver
up to +14 dBm, are unregulated for high power efficiency and can be connected directly to their respective RF receiver
inputs via a pair of passive components to form a single antenna port high efficiency transceiver. The third PA, connected to
the PA_BOOST pin and can deliver up to +20 dBm via a dedicated matching network. Unlike the high efficiency PAs, this
high-stability PA covers all frequency bands that the frequency synthesizer addresses.
SX1276/77/78/79 also include two timing references, an RC oscillator and a 32 MHz crystal oscillator.
Rev. 7 - May 2020
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WIRELESS & SENSING PRODUCTS
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All major parameters of the RF front end and digital state machine are fully configurable via an SPI interface which gives
access to SX1276/77/78/79’s configuration registers. This includes a mode auto sequencer that oversees the transition
and calibration of the SX1276/77/78/79 between intermediate modes of operation in the fastest time possible.
The SX1276/77/78/79 are equipped with both standard FSK and long range spread spectrum (LoRa®) modems.
Depending upon the mode selected either conventional OOK or FSK modulation may be employed or the LoRa® spread
spectrum modem.
3.1. LoRa® Modem
The LoRa® modem uses a proprietary spread spectrum modulation technique. This modulation, in contrast to legacy
modulation techniques, permits an increase in link budget and increased immunity to in-band interference. At the same
time the frequency tolerance requirement of the crystal reference oscillator is relaxed - allowing a performance increase for
a reduction in system cost. For a detailed description of the design trade-offs and operation of the SX1276/77/78/79 please
consult Section 4.1 of the datasheet.
3.2. FSK/OOK Modem
In FSK/OOK mode the SX1276/77/78/79 supports standard modulation techniques including OOK, FSK, GFSK, MSK and
GMSK. The SX1276/77/78/79 is especially suited to narrow band communication thanks the low-IF architecture employed
and the built-in AFC functionality. For full information on the FSK/OOK modem please consult Section 2.1 of this document.
Rev. 7 - May 2020
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4. SX1276/77/78/79 Digital Electronics
4.1. The LoRa® Modem
The LoRa® modem uses spread spectrum modulation and forward error correction techniques to increase the range and
robustness of radio communication links compared to traditional FSK or OOK based modulation. Examples of the
performance improvement possible, for several possible settings, are summarised in the table below. Here the spreading
factor and error correction rate are design variables that allow the designer to optimise the trade-off between occupied
bandwidth, data rate, link budget improvement and immunity to interference.
Table 12 Example LoRa® Modem Performances, 868MHz Band
Bandwidth
(kHz)
Spreading Factor
Coding rate
Nominal Rb
(bps)
Sensitivity
indication
(dBm)
6
12
6
12
6
12
6
12
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
782
24
1562
49
4688
146
9380
293
-131
-147
-128
-144
-121
-139
-118
-136
10.4
20.8
62.5
125
Frequency
Reference
TCXO
XTAL
Notes - for all bandwidths lower than 62.5 kHz, it is advised to use a TCXO as a frequency reference. This is required to
meet the frequency error tolerance specifications given in the Electrical Specification
- Higher spreading factors and longer transmission times impose more stringent constraints on the short term
frequency stability of the reference. Please get in touch with a Semtech representative to implement extremely low
sensitivity products.
For European operation the range of crystal tolerances acceptable for each sub-band (of the ERC 70-03) is given in the
specifications table. For US based operation a frequency hopping mode is available that automates both the LoRa® spread
spectrum and frequency hopping spread spectrum processes.
Another important facet of the LoRa® modem is its increased immunity to interference. The LoRa® modem is capable of cochannel GMSK rejection of up to 20 dB. This immunity to interference permits the simple coexistence of LoRa® modulated
systems either in bands of heavy spectral usage or in hybrid communication networks that use LoRa® to extend range
when legacy modulation schemes fail.
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4.1.1. Link Design Using the LoRa® Modem
4.1.1.1. Overview
The LoRa® modem is setup as shown in the following figure. This configuration permits the simple replacement of the FSK
modem with the LoRa® modem via the configuration register setting RegOpMode. This change can be performed on the fly
(in Sleep operating mode) thus permitting the use of both standard FSK or OOK in conjunction with the long range
capability. The LoRa® modulation and demodulation process is proprietary, it uses a form of spread spectrum modulation
combined with cyclic error correction coding. The combined influence of these two factors is an increase in link budget and
enhanced immunity to interference.
Figure 5. LoRa® Modem Connectivity
A simplified outline of the transmit and receive processes is also shown above. Here we see that the LoRa® modem has an
independent dual port data buffer FIFO that is accessed through an SPI interface common to all modes. Upon selection of
LoRa® mode, the configuration register mapping of the SX1276/77/78/79 changes. For full details of this change please
consult the register description of Section 4.
So that it is possible to optimise the LoRa® modulation for a given application, access is given to the designer to three
critical design parameters. Each one permitting a trade off between link budget, immunity to interference, spectral
occupancy and nominal data rate. These parameters are spreading factor, modulation bandwidth and error coding rate.
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4.1.1.2. Spreading Factor
The spread spectrum LoRa® modulation is performed by representing each bit of payload information by multiple chips of
information. The rate at which the spread information is sent is referred to as the symbol rate (Rs), the ratio between the
nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information.
The range of values accessible with the LoRa® modem are shown in the following table.
Table 13 Range of Spreading Factors
SpreadingFactor
(RegModulationCfg)
Spreading Factor
(Chips / symbol)
LoRa Demodulator
SNR
6
7
8
9
10
11
12
64
128
256
512
1024
2048
4096
-5 dB
-7.5 dB
-10 dB
-12.5 dB
-15 dB
-17.5 dB
-20 dB
Note that the spreading factor, SpreadingFactor, must be known in advance on both transmit and receive sides of the link
as different spreading factors are orthogonal to each other. Note also the resulting signal to noise ratio (SNR) required at
the receiver input. It is the capability to receive signals with negative SNR that increases the sensitivity, so link budget and
range, of the LoRa receiver.
Spreading Factor 6
SF = 6 Is a special use case for the highest data rate transmission possible with the LoRa modem. To this end several
settings must be activated in the SX1276/77/78/79 registers when it is in use. These settings are only valid for SF6 and
should be set back to their default values for other spreading factors:
Set SpreadingFactor = 6 in RegModemConfig2
The header must be set to Implicit mode.
Set the bit field DetectionOptimize of register RegLoRaDetectOptimize to value "0b101".
Write 0x0C in the register RegDetectionThreshold.
4.1.1.3. Coding Rate
To further improve the robustness of the link the LoRa® modem employs cyclic error coding to perform forward error
detection and correction. Such error coding incurs a transmission overhead - the resultant additional data overhead per
transmission is shown in the table below.
Table 14 Cyclic Coding Overhead
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CodingRate
(RegTxCfg1)
Cyclic Coding
Rate
Overhead Ratio
1
2
3
4
4/5
4/6
4/7
4/8
1.25
1.5
1.75
2
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Forward error correction is particularly efficient in improving the reliability of the link in the presence of interference. So that
the coding rate (and so robustness to interference) can be changed in response to channel conditions - the coding rate can
optionally be included in the packet header for use by the receiver. Please consult Section 4.1.1.6 for more information on
the LoRa® packet and header.
4.1.1.4. Signal Bandwidth
An increase in signal bandwidth permits the use of a higher effective data rate, thus reducing transmission time at the
expense of reduced sensitivity improvement. There are of course regulatory constraints in most countries on the
permissible occupied bandwidth. Contrary to the FSK modem which is described in terms of the single sideband
bandwidth, the LoRa® modem bandwidth refers to the double sideband bandwidth (or total channel bandwidth). The range
of bandwidths relevant to most regulatory situations is given in the LoRa® modem specifications table (see Section 2.5.5).
Table 15 LoRa Bandwidth Options
Note
Bandwidth
(kHz)
Spreading Factor
Coding rate
Nominal Rb
(bps)
7.8
10.4
15.6
20.8
31.2
41.7
62.5
125
250
500
12
12
12
12
12
12
12
12
12
12
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
18
24
37
49
73
98
146
293
586
1172
In the lower band (169 MHz), the 250 kHz and 500 kHz bandwidths are not supported.
4.1.1.5. LoRa® Transmission Parameter Relationship
With a knowledge of the key parameters that can be controlled by the user we define the LoRa® symbol rate as:
Rs = BW
--------2 SF
where BW is the programmed bandwidth and SF is the spreading factor. The transmitted signal is a constant envelope
signal. Equivalently, one chip is sent per second per Hz of bandwidth.
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4.1.1.6. LoRa® Packet Structure
The LoRa® modem employs two types of packet format, explicit and implicit. The explicit packet includes a short header
that contains information about the number of bytes, coding rate and whether a CRC is used in the packet. The packet
format is shown in the following figure.
The LoRa® packet comprises three elements:
A preamble.
An optional header.
The data payload.
Figure 6. LoRa® Packet Structure
Preamble
The preamble is used to synchronize receiver with the incoming data flow. By default the packet is configured with a 12
symbol long sequence. This is a programmable variable so the preamble length may be extended, for example in the
interest of reducing to receiver duty cycle in receive intensive applications. However, the minimum length suffices for all
communication. The transmitted preamble length may be changed by setting the register PreambleLength from 6 to 65535,
yielding total preamble lengths of 6+4 to 65535+4 symbols, once the fixed overhead of the preamble data is considered.
This permits the transmission of a near arbitrarily long preamble sequence.
The receiver undertakes a preamble detection process that periodically restarts. For this reason the preamble length
should be configured identical to the transmitter preamble length. Where the preamble length is not known, or can vary, the
maximum preamble length should be programmed on the receiver side.
Header
Depending upon the chosen mode of operation two types of header are available. The header type is selected by the
ImplicitHeaderModeOn bit found within the RegModemConfig1 register.
Explicit Header Mode
This is the default mode of operation. Here the header provides information on the payload, namely:
The payload length in bytes.
The forward error correction code rate
The presence of an optional 16-bits CRC for the payload.
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The header is transmitted with maximum error correction code (4/8). It also has its own CRC to allow the receiver to
discard invalid headers.
Implicit Header Mode
In certain scenarios, where the payload, coding rate and CRC presence are fixed or known in advance, it may be
advantageous to reduce transmission time by invoking implicit header mode. In this mode the header is removed from the
packet. In this case the payload length, error coding rate and presence of the payload CRC must be manually configured
on both sides of the radio link.
Note
With SF = 6 selected, implicit header mode is the only mode of operation possible.
Explicit Header Mode:
In Explicit Header Mode, the presence of the CRC at the end of the payload in selected only on the transmitter side through
the bit RxPayloadCrcOn in the register RegModemConfig1.
On the receiver side, the bit RxPayloadCrcOn in the register RegModemConfig1 is not used and once the payload has
been received, the user should check the bit CrcOnPayload in the register RegHopChannel. If the bit CrcOnPayload is at
‘1’, the user should then check the Irq Flag PayloadCrcError to make sure the CRC is valid.
If the bit CrcOnPayload is at ‘0’, it means there was no CRC on the payload and thus the IRQ Flag PayloadCrcError will not
be trigged even if the payload has errors.
Explicit Header
Value of the bit
RxPayloadCrcOn
Transmitter
Receiver
CRC Status
0
0
CRC is not checked
0
1
CRC is not checked
1
0
CRC is checked
1
1
CRC is checked
Implicit Header Mode;
In Implicit Header Mode, it is necessary to set the bit RxPayloadCrcOn in the register RegModemConfig1 on both sides
(TX and RX)
Implicit Header
Value of the bit
RxPayloadCrcOn
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Transmitter
Receiver
CRC Status
0
0
CRC is not checked
0
1
CRC is always
wrong
1
0
CRC is not checked
1
1
CRC is checked
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Low Data Rate Optimization
Given the potentially long duration of the packet at high spreading factors the option is given to improve the robustness of
the transmission to variations in frequency over the duration of the packet transmission and reception. The bit
LowDataRateOptimize increases the robustness of the LoRa link at these low effective data rates. Its use is mandated
when the symbol duration exceeds 16ms. Note that both the transmitter and the receiver must have the same setting for
LowDataRateOptimize.
Payload
The packet payload is a variable-length field that contains the actual data coded at the error rate either as specified in the
header in explicit mode or in the register settings in implicit mode. An optional CRC may be appended. For more
information on the payload and how it is loaded from the data buffer FIFO please see Section 4.1.2.3.
4.1.1.7. Time on air
For a given combination of spreading factor (SF), coding rate (CR) and signal bandwidth (BW) the total on-the-air
transmission time of a LoRa® packet can be calculated as follows. From the definition of the symbol rate it is convenient to
define the symbol rate:
1Ts = ----Rs
The LoRa packet duration is the sum of the duration of the preamble and the transmitted packet. The preamble length is calculated as
follows:
T preamble = n preamble + 4,25 T sym
where npreamble is the programmed preamble length, taken from the registers RegPreambleMsb and RegPreambleLsb.The
payload duration depends upon the header mode that is enabled. The following formula gives the number of payload
symbols.
8PL – 4SF + 28 + 16CRC – 20IH
n payload = 8 + max ceil ---------------------------------------------------------------------------------------- CR + 4 0
4 SF – 2DE
With the following dependencies:
PL is the number of Payload bytes (1 to 255)
SF is the spreading factor (6 to 12)
IH=0 when the header is enabled, IH=1 when no header is present
DE=1 when LowDataRateOptimize=1, DE=0 otherwise
CR is the coding rate (1 corresponding to 4/5, 4 to 4/8)
The Payload duration is then the symbol period multiplied by the number of Payload symbols
T payload = n payload T s
The time on air, or packet duration, in simply then the sum of the preamble and payload duration.
T packet = T preamble + T payload
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4.1.1.8. Frequency Hopping with LoRa®
Frequency hopping spread spectrum (FHSS) is typically employed when the duration of a single packet could exceed
regulatory requirements relating to the maximum permissible channel dwell time. This is most notably the case in US
operation where the 902 to 928 MHz ISM band which makes provision for frequency hopping operation. To ease the
implementation of FHSS systems the frequency hopping mode of the LoRa® modem can be enabled by setting
FreqHoppingPeriod to a non-zero value in register RegHopPeriod.
Principle of Operation
The principle behind the FHSS scheme is that a portion of each LoRa® packet is transmitted on each hopping channel from
a look up table of frequencies managed by the host microcontroller. After a predetermined hopping period the transmitter
and receiver change to the next channel in a predefined list of hopping frequencies to continue transmission and reception
of the next portion of the packet. The time which the transmission will dwell in any given channel is determined by
FreqHoppingPeriod which is an integer multiple of symbol periods:
HoppingPeriod = Ts FreqHoppingPeriod
The frequency hopping transmission and reception process starts at channel 0. The preamble and header are transmitted
first on channel 0. At the beginning of each transmission the channel counter FhssPresentChannel (located in the register
RegHopChannel) is incremented and the interrupt signal FhssChangeChannel is generated. The new frequency must then
be programmed within the hopping period to ensure it is taken into account for the next hop, the interrupt
ChangeChannelFhss is then to be cleared by writing a logical ‘1’.
FHSS Reception always starts on channel 0. The receiver waits for a valid preamble detection before starting the
frequency hopping process as described above. Note that in the eventuality of header CRC corruption, the receiver will
automatically request channel 0 and recommence the valid preamble detection process.
Timing of Channel Updates
The interrupt requesting the channel change, FhssChangeChannel, is generated upon transition to the new frequency. The
frequency hopping process is illustrated in the diagram below:
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Figure 7. Interrupts Generated in the Case of Successful Frequency Hopping Communication.
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4.1.2. LoRa® Digital Interface
The LoRa® modem comprises three types of digital interface, static configuration registers, status registers and a FIFO
data buffer. All are accessed through the SX1276/77/78/79’s SPI interface - full details of each type of register are given
below. Full listings of the register addresses used for SPI access are given in Section 4.4.
4.1.2.1. LoRa® Configuration Registers
Configuration registers are accessed through the SPI interface. Registers are readable in all device mode including Sleep.
However, they should be written only in Sleep and Standby modes. Please note that the automatic top level
sequencer (TLS modes) are not available in LoRa® mode and the configuration register mapping changes as
shown in Table 41. The content of the LoRa® configuration registers is retained in FSK/OOK mode. For the functionality of
mode registers common to both FSK/OOK and LoRa® mode, please consult the Analog and RF Front End section of this
document (Section 3).
4.1.2.2. Status Registers
Status registers provide status information during receiver operation.
4.1.2.3. LoRa® Mode FIFO Data Buffer
Overview
The SX1276/77/78/79 is equipped with a 256 byte RAM data buffer which is uniquely accessible in LoRa mode. This RAM
area, herein referred to as the FIFO Data buffer, is fully customizable by the user and allows access to the received, or to
be transmitted, data. All access to the LoRa® FIFO data buffer is done via the SPI interface. A diagram of the user defined
memory mapping of the FIFO data buffer is shown below. These FIFO data buffer can be read in all operating modes
except sleep and store data related to the last receive operation performed. It is automatically cleared of old content upon
each new transition to receive mode.
Figure 8. LoRa® Data Buffer
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Principle of Operation
Thanks to its dual port configuration, it is possible to simultaneously store both transmit and receive information in the FIFO
data buffer. The register RegFifoTxBaseAddr specifies the point in memory where the transmit information is stored.
Similarly, for receiver operation, the register RegFifoRxBaseAddr indicates the point in the data buffer where information
will be written to in event of a receive operation.
By default, the device is configured at power up so that half of the available memory is dedicated to Rx
(RegFifoRxBaseAddr initialized at address 0x00) and the other half is dedicated for Tx (RegFifoTxBaseAddr initialized at
address 0x80).
However, due to the contiguous nature of the FIFO data buffer, the base addresses for Tx and Rx are fully configurable
across the 256 byte memory area. Each pointer can be set independently anywhere within the FIFO. To exploit the
maximum FIFO data buffer size in transmit or receive mode, the whole FIFO data buffer can be used in each mode by
setting the base addresses RegFifoTxBaseAddr and RegFifoRxBaseAddr at the bottom of the memory (0x00).
The FIFO data buffer is cleared when the device is put in SLEEP mode, consequently no access to the FIFO data buffer is
possible in sleep mode. However, the data in the FIFO data buffer are retained when switching across the other LoRa®
modes of operation, so that a received packet can be retransmitted with minimum data handling on the controller side. The
FIFO data buffer is not self-clearing (unless if the device is put in sleep mode) and the data will only be “erased” when a
new set of data is written into the occupied memory location.
The FIFO data buffer location to be read from, or written to, via the SPI interface is defined by the address pointer
RegFifoAddrPtr. Before any read or write operation it is hence necessary to initialize this pointer to the corresponding base
value. Upon reading or writing to the FIFO data buffer (RegFifo) the address pointer will then increment automatically.
The register RegRxNbBytes defines the size of the memory location to be written in the event of a successful receive
operation. The register RegPayloadLength indicates the size of the memory location to be transmitted. In implicit header
mode, the register RegRxNbBytes is not used as the number of payload bytes is known. Otherwise, in explicit header
mode, the initial size of the receive buffer is set to the packet length in the received header. The register
RegFifoRxCurrentAddr indicates the location of the last packet received in the FIFO so that the last packet received can be
easily read by pointing the register RegFifoAddrPtr to this register.
It is important to notice that all the received data will be written to the FIFO data buffer even if the CRC is invalid, permitting
user defined post processing of corrupted data. It is also important to note that when receiving, if the packet size exceeds
the buffer memory allocated for the Rx, it will overwrite the transmit portion of the data buffer.
4.1.2.4. Interrupts in LoRa Mode
Two registers are used to control the IRQ in LoRa mode, the register RegIrqFlagsMask which is used to mask the
interrupts and the register RegIrqFlags which indicates which IRQ has been trigged.
In the register RegIrqFlagsMask, setting a bit to ‘1’ will mask the interrupt, meaning this interrupt is disactivated. By default
all the interrupt are available.
In the register RegIrqFlags, a ‘1’ indicates a given IRQ has been trigged and then the IRQ must be clear by writing a ‘1’.
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4.1.3. Operation of the LoRa® Modem
4.1.3.1. Operating Mode Control
The operating modes of the LoRa® modem are accessed by enabling LoRa® mode (setting the LongRangeMode bit of
RegOpMode). Depending upon the operating mode selected the range of functionality and register access is given by the
following table:
Table 16 LoRa® Operating Mode Functionality
Operating Mode
SLEEP
STANDBY
Description
Low-power mode. In this mode only SPI and configuration registers are accessible. Lora FIFO is not
accessible.
Note that this is the only mode permissible to switch between FSK/OOK mode and LoRa mode.
both Crystal oscillator and Lora baseband blocks are turned on.RF part and PLLs are disabled
FSTX
This is a frequency synthesis mode for transmission. The PLL selected for transmission is locked and active
at the transmit frequency. The RF part is off.
FSRX
This is a frequency synthesis mode for reception. The PLL selected for reception is locked and active at the
receive frequency. The RF part is off.
TX
When activated the SX1276/77/78/79 powers all remaining blocks required for transmit, ramps the PA,
transmits the packet and returns to Standby mode.
RXCONTINUOUS
When activated the SX1276/77/78/79 powers all remaining blocks required for reception, processing all
received data until a new user request is made to change operating mode.
RXSINGLE
When activated the SX1276/77/78/79 powers all remaining blocks required for reception, remains in this
state until a valid packet has been received and then returns to Standby mode.
CAD
When in CAD mode, the device will check a given channel to detect LoRa preamble signal
It is possible to access any mode from any other mode by changing the value in the RegOpMode register.
4.1.4. Frequency Settings
Recalling that the frequency step is given by:
F XOSC
F STEP = --------------19
2
In order to set LO frequency values following registers are available.
FRF is a 24-bit register which defines carrier frequency. The carrier frequency relates to the register contents by following
formula:
F RF = F STEP Frf (23,0)
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4.1.5. Frequency Error Indication
The SX1276/77/78/79 derives its RF center frequency from a crystal reference oscillator which has a finite frequency
precision. Errors in reference frequency will manifest themselves as errors of the same proportion from the RF center
frequency.
In LoRa receive mode the SX1276/77/78/79 is capable of measuring the frequency offset between the receiver centre
frequency and that of an incoming LoRa signal. The modem is intolerant of frequency offsets in the region of +/- 25% of the
bandwidth and will accurately report the error over this same range.
In LoRa mode the frequency error, LoRaFeiValue, indicator is a 2’s compliment 20-bit value accessible from registers 0x28
to 0x2A. To convert this value to a frequency error in Hertz, the following conversion should be applied:
24
LoRaFeiValue 2 - -------BW
F ErrHz = --------------------------------------------------- 6
500
32 10
Where BW is the LoRa modem bandwidth in kHz. It can also be useful to express this same quantity as the equivalent
PPM (parts per million) of frequency error.
6
10
F Errppm = F Err – Hz --------F RF
Where FRF is the programmed RF centre frequency of the SX1276 at the time the FEI measurement was made.
4.1.6. LoRa AFC
To use the LoRaFeiValue information to correct a frequency offset and perform automatic frequency correction two
additional steps are necessary:
1) Retune the RF centre frequency This is done by simply reprogramming to the following corrected centre frequency:
F RF
F Errppm
F RF new = F RF – --------6
10
2) In addition to this the LoRa modem nust be made aware of the subtle difference in data rate caused by the shift in
frequency error. This is done by first scaling the frequency error:
offset = 0,95 F Errppm
The scaled is then converted to an 8 bit 2’s compliment number which is written to register 0x27.
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LoRa® Modem State Machine Sequences
The sequence for transmission and reception of data to and from the LoRa® modem, together with flow charts of typical
sequences of operation, are detailed below.
Data Transmission Sequence
In transmit mode power consumption is optimized by enabling RF, PLL and PA blocks only when packet data needs to be
transmitted. Figure 9 shows a typical LoRa® transmit sequence.
Figure 9. LoRa® Modulation Transmission Sequence.
Static configuration registers can only be accessed in Sleep mode, Standby mode or FSTX mode.
The LoRa® FIFO can only be filled in Standby mode.
Data transmission is initiated by sending TX mode request.
Upon completion the TxDone interrupt is issued and the radio returns to Standby mode.
Following transmission the radio can be manually placed in Sleep mode or the FIFO refilled for a subsequent Tx
operation.
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LoRa® Transmit Data FIFO Filling
In order to write packet data into FIFO user should:
1 Set FifoPtrAddr to FifoTxPtrBase.
2 Write PayloadLength bytes to the FIFO (RegFifo)
Data Reception Sequence
Figure 10 shows typical LoRa® receive sequences for both single and continuous receiver modes of operation.
Figure 10. LoRa® Receive Sequence.
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The LoRa receive modem can work in two distinct mode
1.
Single receive mode
2.
Continuous receive mode
Those two modes correspond to different use cases and it is important to understand the subtle differences between them.
Single Reception Operating Mode
In this mode, the modem searches for a preamble during a given period of time. If a preamble hasn’t been found at the end
of the time window, the chip generates the RxTimeout interrupt and goes back to Standby mode. The length of the
reception window (in symbols) is defined by the RegSymbTimeout register and should be in the range of 4 (minimum time
for the modem to acquire lock on a preamble) up to 1023 symbols.
At the end of the payload, the RxDone interrupt is generated together with the interrupt PayloadCrcError if the payload
CRC is not valid. However, even when the CRC is not valid, the data are written in the FIFO data buffer for post processing.
Following the RxDone interrupt the radio goes to Standby mode.
The modem will also automatically return in Standby mode when the interrupts RxDone is generated. Therefore, this mode
should only be used when the time window of arrival of the packet is known. In other cases, the RX continuous mode
should be used.
In Rx single mode, low-power is achieved by turning off PLL and RF blocks as soon as a packet has been received. The
flow is as follows:
1 Set FifoAddrPtr to FifoRxBaseAddr.
2 Static configuration register device can be written in either Sleep mode, Standby mode or FSRX mode.
3 A single packet receive operation is initiated by selecting the operating mode RXSINGLE.
4 The receiver will then await the reception of a valid preamble. Once received, the gain of the receive chain is set.
Following the ensuing reception of a valid header, indicated by the ValidHeader interrupt in explicit mode. The packet
reception process commences. Once the reception process is complete the RxDone interrupt is set. The radio then returns
automatically to Standby mode to reduce power consumption.
5 The receiver status register PayloadCrcError should be checked for packet payload integrity.
6 If a valid packet payload has been received then the FIFO should be read (See Payload Data Extraction below). Should
a subsequent single packet reception need to be triggered, then the RXSINGLE operating mode must be re-selected to
launch the receive process again - taking care to reset the SPI pointer (FifoAddrPtr) to the base location in memory
(FifoRxBaseAddr).
Continuous Reception Operating Mode
In continuous receive mode, the modem scans the channel continuously for a preamble. Each time a preamble is detected
the modem tracks it until the packet is received and then carries on waiting for the next preamble.
If the preamble length exceeds the anticipated value set by the registers RegPreambleMsb and RegPreambleLsb (measured in
symbol periods) the preamble will be dropped and the search for a preamble restarted. However, this scenario will not be
flagged by any interrupt. In continuous RX mode, opposite to the single RX mode, the RxTimeout interrupt will never occur
and the device will never go in Standby mode automatically.
It is also important to note that the demodulated bytes are written in the data buffer memory in the order received. Meaning,
the first byte of a new packet is written just after the last byte of the preceding packet. The RX modem address pointer is
never reset as long as this mode is enabled. It is therefore necessary for the companion microcontroller to handle the
address pointer to make sure the FIFO data buffer is never full.
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In continuous mode the received packet processing sequence is given below.
1 Whilst in Sleep or Standby mode select RXCONT mode.
2 Upon reception of a valid header CRC the RxDone interrupt is set. The radio remains in RXCONT mode waiting for the
next RX LoRa® packet.
3 The PayloadCrcError flag should be checked for packet integrity.
4 If packet has been correctly received the FIFO data buffer can be read (see below).
5 The reception process (steps 2 - 4) can be repeated or receiver operating mode exited as desired.
In continuous mode status information are available only for the last packet received, i.e. the corresponding registers
should be read before the next RxDone arrives.
Rx Single and Rx Continuous Use Cases
The LoRa single reception mode is used mainly in battery operated systems or in systems where the companion
microcontroller has a limited availability of timers. In such systems, the use of the timeout present in Rx Single reception
mode allows the end user to limit the amount of time spent in reception (and thus limiting the power consumption) while not
using any of the companion MCU timers (the MCU can then be in sleep mode while the radio is in the reception mode). The
RxTimeout interrupt generated at the end of the reception period is then used to wake-up the companion MCU. One of the
advantages of the RxSingle mode is that the interrupt RxTimeout will not be triggered if the device is currently receiving
data, thus giving the priority to the reception of the data over the timeout. However, if during the reception, the device loses
track of the data due to external perturbation, the device will drop the reception, flag the interrupt RxTimeout and go in
StandBy mode to decrease the power consumption of the system.
On the other hand, The LoRa continuous reception mode is used in systems which do not have power restrictions or on
system where the use of a companion MCU timer is preferred over the radio embedded timeout system. In RxContinuous
mode, the radio will track any LoRa signal present in the air and carry on the reception of packets until the companion MCU
sets the radio into another mode of operation. Upon reception the interrupt RxDone will be trigged but the device will stay in
Rx Mode, ready for the reception of the next packet.
Payload Data Extraction from FIFO
In order to retrieve received data from FIFO the user must ensure that ValidHeader, PayloadCrcError, RxDone and
RxTimeout interrupts in the status register RegIrqFlags are not asserted to ensure that packet reception has terminated
successfully (i.e. no flags should be set).
In case of errors the steps below should be skipped and the packet discarded. In order to retrieve valid received data from
the FIFO the user must:
RegRxNbBytes Indicates the number of bytes that have been received thus far.
RegFifoAddrPtr is a dynamic pointer that indicates precisely where the Lora modem received data has been written up
to.
Set RegFifoAddrPtr to RegFifoRxCurrentAddr. This sets the FIFO pointer to the location of the last packet received in
the FIFO. The payload can then be extracted by reading the register RegFifo, RegRxNbBytes times.
Alternatively, it is possible to manually point to the location of the last packet received, from the start of the current
packet, by setting RegFifoAddrPtr to RegFifoRxByteAddr minus RegRxNbBytes. The payload bytes can then be read
from the FIFO by reading the RegFifo address RegRxNbBytes times.
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Packet Filtering based on Preamble Start
The LoRa modem does automatically filter received packets based upon any addressing. However the SX1276/77/78/79
permit software filtering of the received packets based on the contents of the first few bytes of payload. A brief example is
given below for a 4 byte address, however, the address length can be selected by the designer.
The objective of the packet filtering process is to determine the presence, or otherwise, of a valid packet designed for the
receiver. If the packet is not for the receiver then the radio returns to sleep mode in order to improve battery life.
The software packet filtering process follows the steps below:
Each time the RxDone interrupt is received, latch the RegFifoRxByteAddr[7:0] register content in a variable, this
variable will be called start_address. The RegFifoRxByteAddr[7:0] register of the SX1276/77/78/79 gives in real time
the address of the last byte written in the data buffer + 1 (or the address at which the next byte will be written) by the
receive LoRa modem. So by doing this, we make sure that the variable start_address always contains the start address
of the next packet.
Upon reception of the interrupt ValidHeader, start polling the RegFifoRxByteAddr[7:0] register until it begins to
increment. The speed at which this register will increment depends on the Spreading factor, the error correction code
and the modulation bandwidth. (Note that this interrupt is still generated in implicit mode).
As soon as RegFifoRxByteAddr[7:0] >= start address + 4, the first 4 bytes (address) are stored in the FIFO data buffer.
These can be read and tested to see if the packet is destined for the radio and either remaining in Rx mode to receive
the packet or returning to sleep mode if not.
Receiver Timeout Operation
In LoRa® Rx Single mode, a receiver timeout functionality is available that permits the receiver to listen for a
predetermined period of time before generating an interrupt signal to indicate that no valid packets have been received.
The timer is absolute and commences as soon as the radio is placed in single receive mode. The interrupt itself, RxTimeout,
can be found in the interrupt register RegIrqFlags. In Rx Single mode, the device will return to Standby mode as soon as
the interrupt occurs. The user must then clear the interrupt or go into Sleep mode before returning into Rx Single mode.
The programmed timeout value is expressed as a multiple of the symbol period and is given by:
TimeOut = LoraRxTimeout Ts
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Channel Activity Detection
The use of a spread spectrum modulation technique presents challenges in determining whether the channel is already in
use by a signal that may be below the noise floor of the receiver. The use of the RSSI in this situation would clearly be
impracticable. To this end the channel activity detector is used to detect the presence of other LoRa® signals. Figure 11
shows the channel activity detection (CAD) process:
Figure 11. LoRa® CAD Flow
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Principle of Operation
The channel activity detection mode is designed to detect a LoRa preamble on the radio channel with the best possible
power efficiency. Once in CAD mode, the SX1276/77/78/79 will perform a very quick scan of the band to detect a LoRa
packet preamble.
During a CAD the following operations take place:
The PLL locks
The radio receiver and the PLL turn off, and the modem digital processing starts.
The radio receiver captures LoRa preamble symbol of data from the channel. The radio current consumption during that
phase corresponds to the specified Rx mode current
The modem searches for a correlation between the radio captured samples and the ideal preamble waveform. This
correlation process takes a little bit less than a symbol period to perform. The radio current consumption during that
phase is greatly reduced.
Once the calculation is finished the modem generates the CadDone interrupt. If the correlation was successful,
CadDetected is generated simultaneously.
The chip goes back to Standby mode.
If a preamble was detected, clear the interrupt, then initiate the reception by putting the radio in RX single mode or RX
continuous mode.
The time taken for the channel activity detection is dependent upon the LoRa modulation settings used. For a given
configuration the typical CAD detection time is shown in the graph below, expressed as a multiple of the LoRa symbol
period. Of this period the radio is in receiver mode for (2SF + 32) / BW seconds. For the remainder of the CAD cycle the
radio is in a reduced consumption state.
Figure 12. CAD Time as a Function of Spreading Factor
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To illustrate this process and the respective consumption in each mode, the CAD process follows the sequence of events
outlined below:
Figure 13. Consumption Profile of the LoRa CAD Process
The receiver is then in full receiver mode for just over half of the activity detection, followed by a reduced consumption
processing phase where the consumption varies with the LoRa bandwidth as shown in the table below.
Table 17 LoRa CAD Consumption Figures
Note
Bandwidth
(kHz)
Full Rx, IDDR_L
(mA)
Processing, IDDC_L
(mA)
7.8 to 41.7
62.5
125
250
500
11
11
11.5
12.4
13.8
5.2
5.6
6
6.8
8.3
These numbers can be slightly lower when using Band 2 and 3, on the low frequency port.
2.0.1. Digital IO Pin Mapping
Six of SX1276/77/78/79’s general purpose IO pins are available used in LoRa® mode. Their mapping is shown below and
depends upon the configuration of registers RegDioMapping1 and RegDioMapping2.
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Table 18 DIO Mapping LoRa® Mode
Operating
Mode
DIOx
Mapping
ALL
00
01
10
11
DIO5
DIO4
DIO3
DIO2
ModeReady
ClkOut
DIO1
DIO0
CadDetected
CadDone
PllLock
ValidHeader
FhssChangeChannel
RxTimeout
RxDone
FhssChangeChannel
FhssChangeChannel
ClkOut
PllLock
TxDone
PayloadCrcError
FhssChangeChannel
CadDetected
CadDone
-
-
-
-
-
-
2.0.2. Modem Status Indicators
The state of the LoRa modem is accessible with the ModemStatus bits in RegModemStat. They can mostly used for debug
in Rx mode and the useful indicators are:
Bit 0: Signal Detected indicates that a valid LoRa preamble has been detected
Bit 1: Signal Synchronized indicates that the end of Preamble has been detected, the modem is in lock
Bit 3: Header Info Valid toggles high when a valid Header (with correct CRC) is detected
2.1. FSK/OOK Modem
2.1.1. Bit Rate Setting
The bitrate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalently
chip) rate of the radio. In continuous transmit mode (Section 2.1.12) the data stream to be transmitted can be input directly
to the modulator via pin 10 (DIO2/DATA) in an asynchronous manner, unless Gaussian filtering is used, in which case the
DCLK signal on pin 9 (DIO1/DCLK) is used to synchronize the data stream. See section 2.1.2.3 for details on the Gaussian
filter.
In Packet mode or in Continuous mode with Gaussian filtering enabled, the Bit Rate (BR) is controlled by bits Bitrate in
RegBitrateMsb and RegBitrateLsb
FXOSC
BitRate = -----------------------------------------------------------------------BitRate (15,0) + BitrateFrac
------------------------------16
Note:
BitrateFrac bits have no effect (i.e may be considered equal to 0) in OOK modulation mode.
The quantity BitrateFrac is hence designed to allow very high precision (max. 250 ppm programing resolution) for any
bitrate in the programmable range. Table 19 below shows a range of standard bitrates and the accuracy to within which
they may be reached.
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Table 19 Bit Rate Examples
Type
Classical modem baud rates
(multiples of 1.2 kbps)
Classical modem baud rates
(multiples of 0.9 kbps)
Round bit rates
(multiples of 12.5, 25 and
50 kbps)
Watch Xtal frequency
BitRate
(15:8)
BitRate
(7:0)
(G)FSK
(G)MSK
OOK
Actual BR
(b/s)
0x68
0x2B
1.2 kbps
1.2 kbps
1200.015
0x34
0x15
2.4 kbps
2.4 kbps
2400.060
0x1A
0x0B
4.8 kbps
4.8 kbps
4799.760
0x0D
0x05
9.6 kbps
9.6 kbps
9600.960
0x06
0x83
19.2 kbps
19.2 kbps
19196.16
0x03
0x41
38.4 kbps
38415.36
0x01
0xA1
76.8 kbps
76738.60
0x00
0xD0
153.6 kbps
153846.1
0x02
0x2C
57.6 kbps
57553.95
0x01
0x16
115.2 kbps
115107.9
0x0A
0x00
12.5 kbps
12.5 kbps
12500.00
0x05
0x00
25 kbps
25 kbps
25000.00
0x80
0x00
50 kbps
50000.00
0x01
0x40
100 kbps
100000.0
0x00
0xD5
150 kbps
150234.7
0x00
0xA0
200 kbps
200000.0
0x00
0x80
250 kbps
250000.0
0x00
0x6B
300 kbps
299065.4
0x03
0xD1
32.768 kbps
32.768 kbps
32753.32
2.1.2. FSK/OOK Transmission
2.1.2.1. FSK Modulation
FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the
PLL. The high resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency deviation
FDEV is given by:
F DEV = F STEP Fdev (13,0)
To ensure correct modulation, the following limit applies:
BR
F DEV + ------- 250 kHz
2
Note
No constraint applies to the modulation index of the transmitter, but the frequency deviation must be set between
600 Hz and 200 kHz.
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2.1.2.2. OOK Modulation
OOK modulation is applied by switching on and off the power amplifier. Digital control and ramping are available to improve
the transient power response of the OOK transmitter.
2.1.2.3. Modulation Shaping
Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrow band response of the
transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp.
In FSK mode, a Gaussian filter with BT = 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta
modulator. If the Gaussian filter is enabled when the SX1276/77/78/79 is in Continuous mode, DCLK signal on pin 10
(DIO1/DCLK) will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section
2.1.12.2 for details.
When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and
off, to reduce spectral splatter.
Note
The transmitter must be restarted if the ModulationShaping setting is changed, in order to recalibrate the built-in
filter.
2.1.3. FSK/OOK Reception
2.1.3.1. FSK Demodulator
The FSK demodulator of the SX1276/77/78/79 is designed to demodulate FSK, GFSK, MSK and GMSK modulated
signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10:
2 F DEV
0,5 = ---------------------- 10
BR
The output of the FSK demodulator can be fed to the Bit Synchronizer to provide the companion processor with a
synchronous data stream in Continuous mode.
2.1.3.2. OOK Demodulator
The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes
are available, configured through bits OokThreshType in RegOokPeak.
The recommended mode of operation is the “Peak” threshold mode, illustrated in Figure 14:
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RSSI
[dBm]
‘’Peak -6dB’’ Threshold
‘’Floor’’ threshold defined by
OokFixedThresh
Noise floor of
receiver
Time
Zoom
Zoom
Decay in dB as defined in
OokPeakThreshStep
Fixed 6dB difference
Period as defined in
OokPeakThreshDec
Figure 14. OOK Peak Demodulator Description
In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of
an input signal, or during the reception of a logical ‘0’, the acquired peak value is decremented by one OokPeakThreshStep
every OokPeakThreshDec period.
When the RSSI output is null for a long time (for instance after a long string of “0” received, or if no transmitter is present),
the peak threshold level will continue falling until it reaches the “Floor Threshold”, programmed in OokFixedThresh.
The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in
applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized
accordingly.
Optimizing the Floor Threshold
OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals
(i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly.
Note that the noise floor of the receiver at the demodulator input depends on:
The noise figure of the receiver.
The gain of the receive chain from antenna to base band.
The matching - including SAW filter if any.
The bandwidth of the channel filters.
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It is therefore important to note that the setting of OokFixedThresh will be application dependent. The following procedure
is recommended to optimize OokFixedThresh.
Set SX1276/7/8/9 in OOK Rx mode
Adjust Bit Rate, Channel filter BW
Default OokFixedThresh setting
No input signal
Continuous Mode
Monitor DIO2/DATA pin
Increment
OokFixedThresh
Glitch activity
on DATA ?
Optimization complete
Figure 15. Floor Threshold Optimization
The new floor threshold value found during this test should be used for OOK reception with those receiver settings.
Optimizing OOK Demodulator for Fast Fading Signals
A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop
can be estimated, the following OOK demodulator parameters OokPeakThreshStep and OokPeakThreshDec can be
optimized as described below for a given number of threshold decrements per bit. Refer to RegOokPeak to access those
settings.
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Alternative OOK Demodulator Threshold Modes
In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors:
Fixed Threshold: The value is selected through OokFixedThresh
Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with
DC-free encoded data.
2.1.3.3. Bit Synchronizer
The bit synchronizer provides a clean and synchronized digital output based upon timing recovery information gleaned
from the received data edge transitions. Its output is made available on pin DIO1/DCLK in Continuous mode and can be
disabled through register settings. However, for optimum receiver performance, especially in Continuous receive mode, its
use is strongly advised.
The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in
RegBitrate.
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output
To pin DATA and
DCLK in continuous
mode
DCLK
Figure 16. Bit Synchronizer Description
To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied:
A preamble (0x55 or 0xAA) of at least 12 bits is required for synchronization, the longer the synchronization phase is the
better the ensuing packet detection rate will be.
The subsequent payload bit stream must have at least one edge transition (either rising or falling) every 16 bits during
data transmission.
The absolute error between transmitted and received bit rate must not exceed 6.5%.
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2.1.3.4. Frequency Error Indicator
This frequency error indicator measures the frequency error between the programmed RF centre frequency and the carrier
frequency of the modulated input signal to the receiver. When the FEI is performed, the frequency error is measured and
the signed result is loaded in FeiValue in RegFei, in 2’s complement format. The time required for an FEI evaluation is 4 bit
periods.
To ensure correct operation of the FEI:
The measurement must be launched during the reception of preamble.
The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth. i.e.
The whole modulated spectrum must be received.
The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth):
BW 20dB = 2 F DEV + BR
-------
2
The frequency error, in Hz, can be calculated with the following formula:
FEI = F STEP FeiValue
The FEI is enabled automatically upon the transition to receive mode and automatically updated every 4 bits.
2.1.3.5. AFC
The AFC is based on the FEI measurement, therefore the same input signal and receiver setting conditions apply. When
the AFC procedure is performed the AfcValue is directly subtracted from the register that defines the frequency of
operation of the chip, FRF. The AFC is executed each time the receiver is enabled, if AfcAutoOn = 1.
When the AFC is enabled (AfcAutoOn = 1), the user has the option to:
Clear the former AFC correction value, if AfcAutoClearOn = 1. Allowing the next frequency correction to be performed
from the initial centre frequency.
Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the centre
frequency experiences cumulative drift - such as the ageing of a crystal reference.
The SX1276/77/78/79 offers an alternate receiver bandwidth setting during the AFC phase allowing the accommodation of
larger frequency errors. The setting RegAfcBw sets the receive bandwidth during the AFC process. In a typical receiver
application the, once the AFC is performed, the radio will revert to the receiver communication or channel bandwidth
(RegRxBw) for the ensuing communication phase.
Note that the FEI measurement is valid only during the reception of preamble. The provision of the PreambleDetect flag
can hence be used to detect this condition and allow a reliable AFC or FEI operation to be triggered. This process can be
performed automatically by using the appropriate options in StartDemodOnPreamble found in the RegRxConfig register.
A detailed description of the receiver setup to enable the AFC is provided in section 2.1.6.
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2.1.3.6. Preamble Detector
The Preamble Detector indicates the reception of a carrier modulated with a 0101...sequence. It is insensitive to the
frequency offset, as long as the receiver bandwidth is large enough. The size of detection can be programmed from 1 to 3
bytes with PreambleDetectorSize in RegPreambleDetect as defined in the next table.
Table 20 Preamble Detector Settings
PreambleDetectorSize
# of Bytes
00
1
01
2 (recommended)
10
3
11
reserved
For normal operation, PreambleDetectTol should be set to be set to 10 (0x0A), with a qualifying preamble size of 2 bytes.
The PreambleDetect interrupt (either in RegIrqFlags1 or mapped to a specific DIO) then goes high every time a valid
preamble is detected, assuming PreambleDetectorOn=1.
The preamble detector can also be used as a gate to ensure that AFC and AGC are performed on valid preamble. See
section 2.1.6. for details.
2.1.3.7. Image Rejection Mixer
The SX1276/77/78/79 employs an image rejection mixer (IRM) which, uncalibrated, 35 dB image rejection. A low phase
noise PLL is used to perform calibration of the receiver chain. This increases the typical image rejection to 48 dB.
2.1.3.8. Image and RSSI Calibration
An automated process is implemented to calibrate the phase and gain imbalances of I and Q receive paths. This calibration
enhances image rejection and improves RSSI precision. It is launched under the following circumstances:
Automatically at Power On Reset or after a Manual Reset of the chip (refer to section 5.2), only for the Low Frequency
front-end, and is performed at 434MHz
Automatically when a pre-defined temperature change is observed, if the option is enabled. A selectable temperature
change, set with TempThreshold (5, 10, 15 or 20°C), is detected and reported in TempChange, if the temperature
monitoring is turned On with TempMonitorOff=0.This interrupt flag can be used by the application to launch a new
image calibration at a convenient time if AutoImageCalOn=0, or immediately when this temperature variation is
detected, if AutoImageCalOn=1
Upon user request, by setting bit ImageCalStart in RegImageCal, when the device is in Standby mode
Notes - The calibration procedure takes approximately 10ms. It is recommended to disable the fully automated
(temperature-dependent) calibration, to better control when it is triggered (and avoid unexpected packet losses)
- To perform the calibration, the radio must be temporarily returned to FSK/OOK mode
- The automatic IQ and RSSI calibration done at POR and Reset is only valid at 434 MHz (the value of RegFrf at
POR). To improve accuracy of RSSI and image rejection, this calibration should be replicated at the frequency (ies)
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of interest, for instance a calibration should be launched with Frf set to 868.3 MHz if the high frequency port
supports communication in this frequency band. Conversely if the product is used at 169 MHz, the calibration
should be repeated with Frf=169MHz
- FormerTemp and TempChange in SX1276/77/79 are frequency-specific and the IC keeps a copy of these
variables when switching between the low frequency and the high frequency domains (along with the
corresponding calibration values, stored in test registers)
- FormerTemp and TempChange cannot be read in Sleep mode (although they are saved). They should be read in
Standby mode
2.1.3.9. Timeout Function
The SX1276/77/78/79 includes a Timeout function, which allows it to automatically shut-down the receiver after a receive
sequence and therefore save energy.
Timeout interrupt is generated TimeoutRxRssi x 16 x Tbit after switching to Rx mode if the Rssi flag does not raise
within this time frame (RssiValue > RssiThreshold)
Timeout interrupt is generated TimeoutRxPreamble x 16 x Tbit after switching to Rx mode if the PreambleDetect flag
does not raise within this time frame
Timeout interrupt is generated TimeoutSignalSync x 16 x Tbit after switching to Rx mode if the SyncAddress flag does
not raise within this time frame
This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power
mode. To become active, these timeouts must also be enabled by setting the correct RxTrigger parameters in
RegRxConfig:
Table 21 RxTrigger Settings to Enable Timeout Interrupts
Receiver
Triggering Event
None
Rssi Interrupt
PreambleDetect
Rssi Interrupt & PreambleDetect
RxTrigger
(2:0)
000
001
110
111
Timeout on
Rssi
Off
Active
Off
Active
Timeout on
Preamble
Off
Off
Active
Active
Timeout on
SyncAddress
Active
2.1.4. Operating Modes in FSK/OOK Mode
The SX1276/77/78/79 has several working modes, manually programmed in RegOpMode. Fully automated mode
selection, packet transmission and reception is also possible using the Top Level Sequencer described in Section 2.1.8.
Table 22 Basic Transceiver Modes
Mode
Selected mode
Symbol
Enabled blocks
000
Sleep mode
Sleep
None
001
Standby mode
Stdby
Top regulator and crystal oscillator
010
Frequency synthesiser to Tx
frequency
FSTx
Frequency synthesizer at Tx frequency (Frf)
011
Transmit mode
Tx
Frequency synthesizer and transmitter
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Mode
Selected mode
DATASHEET
Symbol
Enabled blocks
100
Frequency synthesiser to Rx
frequency
FSRx
Frequency synthesizer at frequency for reception (Frf-IF)
101
Receive mode
Rx
Frequency synthesizer and receiver
When switching from a mode to another the sub-blocks are woken up according to a pre-defined optimized sequence.
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2.1.5. Startup Times
The startup time of the transmitter or the receiver is Dependant upon which mode the transceiver was in at the beginning.
For a complete description, Figure 17 below shows a complete startup process, from the lower power mode “Sleep”.
Current
Drain
IDDR (Rx) or IDDT (Tx)
IDDFS
IDDST
IDDSL
0
Timeline
TS_OSC
TS_OSC
+TS_FS
TS_OSC
+TS_FS
+TS_TR
FSTx
Sleep
mode
TS_OSC
+TS_FS
+TS_RE
Transmit
Stdby
mode
FSRx
Receive
Figure 17. Startup Process
TS_OSC is the startup time of the crystal oscillator which depends on the electrical characteristics of the crystal. TS_FS is
the startup time of the PLL including systematic calibration of the VCO.
Typical values of TS_OSC and TS_FS are given in Section 2.5.2.
2.1.5.1. Transmitter Startup Time
The transmitter startup time, TS_TR, is calculated as follows in FSK mode:
1
TS _ TR 5s 1.25 PaRamp Tbit
2
,
where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time.
In OOK mode, this equation can be simplified to the following:
1
TS _ TR 5s Tbit
2
2.1.5.2. Receiver Startup Time
The receiver startup time, TS_RE, only depends upon the receiver bandwidth effective at the time of startup. When AFC is
enabled (AfcAutoOn=1), AfcBw should be used instead of RxBw to extract the receiver startup time:
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Table 23 Receiver Startup Time Summary
RxBw if AfcAutoOn=0
RxBwAfc if AfcAutoOn=1
2.6 kHz
3.1 kHz
3.9 kHz
5.2 kHz
6.3 kHz
7.8 kHz
10.4 kHz
12.5 kHz
15.6 kHz
20.8 kHz
25.0 kHz
31.3 kHz
41.7 kHz
50.0 kHz
62.5 kHz
83.3 kHz
100.0 kHz
125.0 kHz
166.7 kHz
200.0 kHz
250.0 kHz
TS_RE
(+/-5%)
2.33 ms
1.94 ms
1.56 ms
1.18 ms
984 us
791 us
601 us
504 us
407 us
313 us
264 us
215 us
169 us
144 us
119 us
97 us
84 us
71 us
85 us
74 us
63 us
TS_RE or later after setting the device in Receive mode, any incoming packet will be detected and demodulated by the
transceiver.
2.1.5.3. Time to RSSI Evaluation
The first RSSI sample will be available TS_RSSI after the receiver is ready, in other words TS_RE + TS_RSSI after the
receiver was requested to turn on.
Timeline
0
FSRx
TS_RE
TS_RE
+TS_RSSI
Rssi IRQ
Rssi sample
ready
Rx
Figure 18. Time to RSSI Sample
TS_RSSI depends on the receiver bandwidth, as well as the RssiSmoothing option that was selected. The formula used to
calculate TS_RSSI is provided in section 3.5.4.
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2.1.5.4. Tx to Rx Turnaround Time
Timeline
0
Tx Mode
TS_HOP
+TS_RE
1. set new Frf (*)
2. set Rx mode
Rx Mode
(*) Optional
Figure 19. Tx to Rx Turnaround
Note
The SPI instruction times are omitted, as they can generally be very small as compared to other timings (up to
10MHz SPI clock).
2.1.5.5. Rx to Tx
Timeline
0
Rx Mode
TS_HOP
+TS_TR
1. set new Frf (*)
2. set Tx mode
Tx Mode
(*) Optional
Figure 20. Rx to Tx Turnaround
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2.1.5.6. Receiver Hopping, Rx to Rx
Two methods are possible:
First method
Timeline
0
TS_HOP
+TS_RE
Rx Mode,
Channel A
Rx Mode,
Channel B
1. set new Frf
2. set RestartRxWithPllLock
Second method
Timeline
0
~TS_HOP
Rx Mode,
Channel A
1. set FastHopOn=1
2. set new Frf (*)
3. wait for TS_HOP
Rx Mode,
Channel B
(*) RegFrfLsb must be written to
trigger a frequency change
Figure 21. Receiver Hopping
The second method is quicker, and should be used if a very quick RF sniffing mechanism is to be implemented.
2.1.5.7. Tx to Tx
Timeline
~PaRamp
+TS_HOP
0
Tx Mode,
Channel A
1. set new Frf (*)
2. set FSTx mode
~PaRamp
+TS_HOP
+TS_TR
FSTx
Set Tx mode
Tx Mode,
Channel B
Figure 22. Transmitter Hopping
2.1.6. Receiver Startup Options
The SX1276/77/78/79 receiver can automatically control the gain of the receive chain (AGC) and adjust the receiver LO
frequency (AFC). Those processes are carried out on a packet-by-packet basis. They occur:
When the receiver is turned On.
When the receiver is automatically restarted after the reception of a valid packet, or after a packet collision.
When the Receiver is restarted upon user request, through the use of trigger bits RestartRxWithoutPllLock or
RestartRxWithPllLock, in RegRxConfig.
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Automatic restart capabilities are detailed in Section 2.1.7.
The receiver startup options available in SX1276/77/78/79 are described in Table 24.
Table 24 Receiver Startup Options
AgcAutoOn
AfcAutoOn
None
AGC
AGC & AFC
AGC
AGC & AFC
AGC
0
1
1
1
1
1
0
0
1
0
1
0
RxTrigger
(2:0)
000
001
001
110
110
111
AGC & AFC
1
1
111
Triggering Event Realized Function
None
Rssi Interrupt
PreambleDetect
Rssi Interrupt
&
PreambleDetect
When AgcAutoOn=0, the LNA gain is manually selected by choosing LnaGain bits in RegLna.
2.1.7. Receiver Restart Methods
The options for restart of the receiver are covered below. This is typically of use to prepare for the reception of a new signal
whose strength or carrier frequency is different from the preceding packet to allow the AGC or AFC to be re-evaluated.
2.1.7.1. Restart Upon User Request
In Receive mode the user can request a receiver restart - this can be useful in conjunction with the use of a Timeout
interrupt following a period of inactivity in the channel of interest. Two options are available:
No change in the Local Oscillator upon restart: the AFC is disabled, and the Frf register has not been changed through
SPI before the restart instruction: set bit RestartRxWithoutPllLock in RegRxConfig to 1.
Local Oscillator change upon restart: if AFC is enabled (AfcAutoOn=1), and/or the Frf register had been changed during
the last Rx period: set bit RestartRxWithPllLock in RegRxConfig to 1.
Note
ModeReady must be at logic level 1 for a new RestartRx command to be taken into account.
2.1.7.2. Automatic Restart after valid Packet Reception
The bits AutoRestartRxMode in RegSyncConfig control the automatic restart feature of the SX1276/77/78/79 receiver,
when a valid packet has been received:
If AutoRestartRxMode = 00, the function is off, and the user should manually restart the receiver upon valid packet
reception (see section 2.1.7.1).
If AutoRestartRxMode = 01, after the user has emptied the FIFO following a PayloadReady interrupt, the receiver will
automatically restart itself after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence
avoiding a false RSSI detection on the ‘tail’ of the previous packet.
If AutoRestartRxMode = 10 should be used if the next reception is expected on a new frequency, i.e. Frf is changed
after the reception of the previous packet. An additional delay is systematically added, in order for the PLL to lock at a
new frequency.
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2.1.7.3. Automatic Restart when Packet Collision is Detected
In receive mode the SX1276/77/78/79 is able to detect packet collision and restart the receiver. Collisions are detected by
a sudden rise in received signal strength, detected by the RSSI. This functionality can be useful in network configurations
where many asynchronous slaves attempt periodic communication with a single a master node.
The collision detector is enabled by setting bit RestartRxOnCollision to 1.
The decision to restart the receiver is based on the detection of RSSI change. The sensitivity of the system can be adjusted
in 1 dB steps by using register RssiCollisionThreshold in RegRxConfig.
2.1.8. Top Level Sequencer
Depending on the application, it is desirable to be able to change the mode of the circuit according to a predefined
sequence without access to the serial interface. In order to define different sequences or scenarios, a user-programmable
state machine, called Top Level Sequencer (Sequencer in short), can automatically control the chip modes.
NOTE THAT THIS FUNCTIONALITY IS ONLY AVAILABLE IN FSK/OOK MODE.
The Sequencer is activated by setting the SequencerStart bit in RegSeqConfig1 to 1 in Sleep or Standby mode (called
initial mode).
It is also possible to force the Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time.
Note
SequencerStart and Stop bit must never be set at the same time.
2.1.8.1. Sequencer States
As shown in the table below, with the aid of a pair of interrupt timers (T1 and T2), the sequencer can take control of the chip
operation in all modes.
Table 25 Sequencer States
Sequencer
State
SequencerOff State
Description
The Sequencer is not activated. Sending a SequencerStart command will launch it.
When coming from LowPowerSelection state, the Sequencer will be Off, whilst the chip will
return to its initial mode (either Sleep or Standby mode).
Idle State
The chip is in low-power mode, either Standby or Sleep, as defined by IdleMode in
RegSeqConfig1. The Sequencer waits only for the T1 interrupt.
Transmit State
The transmitter in on.
Receive State
The receiver in on.
PacketReceived
The receiver is on and a packet has been received. It is stored in the FIFO.
LowPowerSelection
Selects low power state (SequencerOff or Idle State)
RxTimeout
Defines the action to be taken on a RxTimeout interrupt.
RxTimeout interrupt can be a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync
interrupt.
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2.1.8.2. Sequencer Transitions
The transitions between sequencer states are listed in the forthcoming table.
Table 26 Sequencer Transition Options
Transition
Variable
IdleMode
Selects the chip mode during Idle state:
0: Standby mode
1: Sleep mode
FromStart
Controls the Sequencer transition when the SequencerStart bit is set to 1 in Sleep or Standby mode:
00: to LowPowerSelection
01: to Receive state
10: to Transmit state
11: to Transmit state on a FifoThreshold interrupt
LowPowerSelection
Selects Sequencer LowPower state after a to LowPowerSelection transition
0: SequencerOff state with chip on Initial mode
1: Idle state with chip on Standby or Sleep mode depending on IdleMode
Note: Initial mode is the chip LowPower mode at Sequencer start.
FromIdle
Controls the Sequencer transition from the Idle state on a T1 interrupt:
0: to Transmit state
1: to Receive state
FromTransmit
Controls the Sequencer transition from the Transmit state:
0: to LowPowerSelection on a PacketSent interrupt
1: to Receive state on a PacketSent interrupt
FromReceive
Controls the Sequencer transition from the Receive state:
000 and 111: unused
001: to PacketReceived state on a PayloadReady interrupt
010: to LowPowerSelection on a PayloadReady interrupt
011: to PacketReceived state on a CrcOk interrupt. If CRC is wrong (corrupted packet, with CRC on but
CrcAutoClearOn is off), the PayloadReady interrupt will drive the sequencer to RxTimeout state.
100: to SequencerOff state on a Rssi interrupt
101: to SequencerOff state on a SyncAddress interrupt
110: to SequencerOff state on a PreambleDetect interrupt
Irrespective of this setting, transition to LowPowerSelection on a T2 interrupt
FromRxTimeout
Controls the state-machine transition from the Receive state on a RxTimeout interrupt (and on
PayloadReady if FromReceive = 011):
00: to Receive state via ReceiveRestart
01: to Transmit state
10: to LowPowerSelection
11: to SequencerOff state
Note: RxTimeout interrupt is a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt.
FromPacketReceived
Controls the state-machine transition from the PacketReceived state:
000: to SequencerOff state
001: to Transmit on a FifoEmpty interrupt
010: to LowPowerSelection
011: to Receive via FS mode, if frequency was changed
100: to Receive state (no frequency change)
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2.1.8.3. Timers
Two timers (Timer1 and Timer2) are also available in order to define periodic sequences. These timers are used to
generate interrupts, which can trigger transitions of the Sequencer.
T1 interrupt is generated (Timer1Resolution * Timer1Coefficient) after T2 interrupt or SequencerStart. command.
T2 interrupt is generated (Timer2Resolution * Timer2Coefficient) after T1 interrupt.
The timers’ mechanism is summarized on the following diagram.
Sequencer Start
T2
interrupt
Timer2
Timer1
T1
interrupt
Figure 23. Timer1 and Timer2 Mechanism
Note
The timer sequence is completed independently of the actual Sequencer state. Thus, both timers need to be on to
achieve periodic cycling.
Table 27 Sequencer Timer Settings
Description
Variable
Timer1Resolution
Resolution of Timer1
00: disabled
01: 64 us
10: 4.1 ms
11: 262 ms
Timer2Resolution
Resolution of Timer2
00: disabled
01: 64 us
10: 4.1 ms
11: 262 ms
Timer1Coefficient
Multiplying coefficient for Timer1
Timer2Coefficient
Multiplying coefficient for Timer2
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2.1.8.4. Sequencer State Machine
The following graphs summarize every possible transition between each Sequencer state. The Sequencer states are
highlighted in grey. The transitions are represented by arrows. The condition activating them is described over the
transition arrow. For better readability, the start transitions are separated from the rest of the graph.
Transitory states are highlighted in light grey, and exit states are represented in red. It is also possible to force the
Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time.
Sequencer: Start transitions
Sequencer Off
&
Initial mode = Sleep or Standby
On SequencerStart bit rising edge
Start
On FifoThreshold
if FromStart = 11
If FromStart = 00
If FromStart = 01 If FromStart = 10
LowPower
Selection
Receive
Transmit
Sequencer: State machine
Standby if IdleMode = 0
Sleep if IdleMode = 1
If LowPowerSelection = 1
LowPower
Selection
If LowPowerSelection = 0
( Mode Initial mode )
Sequencer Off
Idle
On T1 if FromIdle = 0
If FromPacketReceived = 000
On T1 if FromIdle = 1
If FromPacketReceived = 010
Packet
Received
On PayloadReady
if FromReceive = 010
On T2
On PayloadReady if FromReceive = 011
(CRC failed and CrcAutoClearOn=0)
On RxTimeout
If FromRxTimeout = 10
RxTimeout
If FromPacketReceived = 100
Via FS mode if FromPacketReceived = 011
On PayloadReady if FromReceive = 001
On CrcOk if FromReceive = 011
Receive
On Rssi if FromReceive = 100
On SyncAdress if FromReceive = 101
On Preamble if FromReceive = 110
On PacketSent
if FromTransmit = 1
Via ReceiveRestart
if FromRxTimeout = 00
If FromRxTimeout = 11
Transmit
On PacketSent
if FromTransmit = 0
Sequencer Off
If FromRxTimeout = 01
Figure 24. Sequencer State Machine
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2.1.9. Data Processing in FSK/OOK Mode
2.1.9.1. Block Diagram
Figure below illustrates the SX1276/77/78/79 data processing circuit. Its role is to interface the data to/from the modulator/
demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers.
The circuit contains several control blocks which are described in the following paragraphs.
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Tx/Rx
CONTROL
Data
Rx
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Tx
Potential datapaths (data operation mode dependant)
Figure 25. SX1276/77/78/79 Data Processing Conceptual View
The SX1276/77/78/79 implements several data operation modes, each with their own data path through the data
processing. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.
2.1.9.2. Data Operation Modes
The SX1276/77/78/79 has two different data operation modes selectable by the user:
Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be
used if adequate external signal processing is available.
Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically
built with preamble, Sync word, and optional CRC and DC-free encoding schemes The reverse operation is performed
in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on
the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited.
Each of these data operation modes is fully described in the following s.
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2.1.10. FIFO
Overview and Shift Register (SR)
In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO
(First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management.
The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A
shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs
them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data
from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.
FIFO
byte1
byte0
8
Data Tx/Rx
SR (8bits)
1
MSB
LSB
Figure 26. FIFO and Shift Register (SR)
Note
When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from
all modes except from Tx)
The FIFO size is fixed to 64 bytes.
Interrupt Sources and Flags
FifoEmpty: FifoEmpty interrupt source is high when byte 0, i.e. whole FIFO, is empty. Otherwise it is low. Note that when
retrieving data from the FIFO, FifoEmpty is updated on NSS falling edge, i.e. when FifoEmpty is updated to low state
the currently started read operation must be completed. In other words, FifoEmpty state must be checked after each
read operation for a decision on the next one (FifoEmpty = 0: more byte(s) to read; FifoEmpty = 1: no more byte to
read).
FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR (in
Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will
also be cleared.
PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.
FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.
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FifoLevel
1
0
B
B+1
# of bytes in FIFO
Figure 27. FifoLevel IRQ Source Behavior
Notes - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be
dynamically updated by only changing the FifoThreshold parameter
- FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation
FIFO Clearing
Table below summarizes the status of the FIFO when switching between different modes
Table 28 Status of FIFO when Switching Between Different Modes of the Chip
From
Stdby
Sleep
Stdby/Sleep
Stdby/Sleep
Rx
Rx
Tx
To
Sleep
Stdby
Tx
Rx
Tx
Stdby/Sleep
Any
FIFO status
Not cleared
Not cleared
Not cleared
Cleared
Cleared
Not cleared
Cleared
Comments
To allow the user to write the FIFO in Stdby/Sleep before Tx
To allow the user to read FIFO in Stdby/Sleep mode after Rx
2.1.10.1. Sync Word Recognition
Overview
Sync word recognition (also called Pattern recognition) is activated by setting SyncOn in RegSyncConfig. The bit
synchronizer must also be activated in Continuous mode (automatically done in Packet mode).
The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync
word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 28 below.
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Rx DATA
Bit N-x =
(NRZ)
Sync_value[x]
DATASHEET
Bit N-1 =
Bit N =
Sync_value[1] Sync_value[0]
DCLK
SyncAddressMatch
Figure 28. Sync Word Recognition
During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and
the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync
word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be
processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.
Configuration
Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this
field is also used for Sync word generation in Tx mode.
Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word
generation in Tx mode.
Note
SyncValue choices containing 0x00 bytes are not allowed
Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in Section 2.1.13.
Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration
registers.
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2.1.11. Digital IO Pins Mapping
Six general purpose IO pins are available on the SX1276/77/78/79, and their configuration in Continuous or Packet mode
is controlled through RegDioMapping1 and RegDioMapping2.
Table 29 DIO Mapping, Continuous Mode
DIOx Mapping
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Sleep
Standby
FSRx/Tx
-
Rx
Tx
SyncAddress
Rssi / PreambleDetect
RxReady
TxReady
TxReady
-
Dclk
Rssi / PreambleDetect
-
-
Data
Data
Data
Data
Timeout
Rssi / PreambleDetect
-
-
TempChange / LowBat
ModeReady
ClkOut
ClkOut if RC
-
ModeReady
TempChange / LowBat
TempChange / LowBat
PllLock
TimeOut
ModeReady
ClkOut
PllLock
Rssi / PreambleDetect
ModeReady
Table 30 DIO Mapping, Packet Mode
DIOx Mapping
00
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
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Sleep
Standby
FSRx/Tx
TempChange / LowBat
FifoLevel
FifoEmpty
FifoFull
FifoFull
FifoLevel
FifoEmpty
FifoFull
FifoFull
FifoFull
FifoFull
FifoEmpty
FifoEmpty
FifoEmpty
TempChange / LowBat
ClkOut if RC
ClkOut
-
-
Tx
PacketSent
-
TempChange / LowBat
FifoLevel
FifoEmpty
FifoFull
FifoFull
RxReady
TimeOut
SyncAddress
FifoEmpty
FifoEmpty
FifoEmpty
Rx
PayloadReady
CrcOk
ModeReady
Page 69
FifoFull
FifoFull
FifoEmpty
TxReady
FifoEmpty
FifoEmpty
TempChange / LowBat
PllLock
TimeOut
Rssi / PreambleDetect
ClkOut
PllLock
Data
ModeReady
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2.1.12. Continuous Mode
2.1.12.1. General Description
As illustrated in Figure 29, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on
the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive.
DIO0
DIO1/DCLK
DIO2/DATA
DIO3
DIO4
DIO5
Tx/Rx
CONTROL
Data
Rx
SYNC
RECOG.
SPI
NSS
SCK
MOSI
MISO
Figure 29. Continuous Mode Conceptual View
2.1.12.2. Tx Processing
In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the
data is illustrated in Figure 30. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state
anytime outside the grayed out setup/hold zone.
T_DATA
T_DATA
DATA
(NRZ)
DCLK
Figure 30. Tx Processing in Continuous Mode
Note
the use of DCLK is required when the modulation shaping is enabled.
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2.1.12.3. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal
is provided.
Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on
DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as
illustrated below.
DATA (NRZ)
DCLK
Figure 31. Rx Processing in Continuous Mode
Note
In Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the
DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode).
2.1.13. Packet Mode
2.1.13.1. General Description
In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and
accessed via the SPI interface.
In addition, the SX1276/77/78/79 packet handler performs several packet oriented tasks such as Preamble and Sync word
generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, etc.
This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself.
Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption
and adding more flexibility for the software.
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DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
CONTROL
Data
Rx
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Tx
Figure 32. Packet Mode Conceptual View
Note
The Bit Synchronizer is automatically enabled in Packet mode.
2.1.13.2. Packet Format
Fixed Length Packet Format
Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater
than 0.
In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF
overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the
same packet length value.
The length of the payload is limited to 2047 bytes.
The length programmed in PayloadLength relates only to the payload which includes the message and the optional
address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte.
An illustration of a fixed length packet is shown below. It contains the following fields:
Preamble (1010...)
Sync word (Network ID)
Optional Address byte (Node ID)
Message data
Optional 2-bytes CRC checksum
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Optional DC free data coding
CRC checksum calculation
Preamble
Sync Word
0 to 65536 bytes 0 to 8 bytes
Address
byte
Message
Up to 2047 bytes
CRC
2-bytes
Payload
(min 1 byte)
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 33. Fixed Length Packet Format
Variable Length Packet Format
Variable length packet format is selected when bit PacketFormat is set to 1.
This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then
necessary for the transmitter to send the length information together with each packet in order for the receiver to operate
properly.
In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to
255 bytes. Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2
bytes, i.e. length + address or message byte.
An illustration of a variable length packet is shown below. It contains the following fields:
Preamble (1010...)
Sync word (Network ID)
Length byte
Optional Address byte (Node ID)
Message data
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Optional 2-bytes CRC checksum
Optional DC free data coding
CRC checksum calculation
Preamble
Sync Word
0 to 65536 bytes 0 to 8 bytes
Length
byte
Address
byte
Message
Up to 255 bytes
CRC
2-bytes
Payload
(min 2 bytes)
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 34. Variable Length Packet Format
Unlimited Length Packet Format
Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can
then transmit and receive packet of arbitrary length and PayloadLength register is not used in Tx/Rx modes for counting
the length of the bytes transmitted/received.
In Tx the data is transmitted depending on the TxStartCondition bit. On the Rx side the data processing features like
Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero
(SyncOn = 0). The CRC detection in Rx is also not supported in this mode of the packet handler, however CRC generation
in Tx is operational. The interrupts like CrcOk & PayloadReady are not available either.
An unlimited length packet shown below is made up of the following fields:
Preamble (1010...).
Sync word (Network ID).
Optional Address byte (Node ID).
Message data
Optional 2-bytes CRC checksum (Tx only)
DC free Data encoding
Preamble
0 to 65535
bytes
Sync Word
0 to 8 bytes
Address
byte
Message
unlimited length
Payload
Fields added by the packet handler in Tx and processed and removed in Rx
Message part of the payload
Optional User provided fields which are part of the payload
Figure 35. Unlimited Length Packet Format
2.1.13.3. Tx Processing
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In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload
available in the FIFO:
Add a programmable number of preamble bytes
Optional DC-free encoding of the data (Manchester or whitening)
Add a programmable Sync word
Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) and
appending the 2 bytes checksum.
Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO.
The transmission of packet data is initiated by the Packet Handler only if the chip is in Tx mode and the transmission
condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a
preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or
one until the condition is met to transmit the packet data.
The transmission condition itself is defined as:
if TxStartCondition = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the
preamble followed by the sync word and user payload
If TxStartCondition = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number
defined in RegFifoThresh + 1
If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of
packet starts immediately on enabling Tx
2.1.13.4. Rx Processing
In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:
Receiving the preamble and stripping it off
Detecting the Sync word and stripping it off
Optional DC-free decoding of data
Optionally checking the address byte
Optionally checking CRC and reflecting the result on CrcOk.
Only the payload (including optional address and length fields) is made available in the FIFO.
When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed
length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength
parameter.
In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The
internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater
than the maximum expected length of the received packet. If the received length is greater than the maximum length stored
in PayloadLength register the packet is discarded otherwise the complete packet is received.
If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed
length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues
otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the
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CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the
FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode.
If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by
setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC
fails.
2.1.13.5. Handling Large Packets
When PayloadLength exceeds FIFO size (64 bytes) whether in fixed, variable or unlimited length packet format, in addition
to PacketSent in Tx and PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below:
For Tx:
FIFO can be prefilled in Sleep/Standby but must be refilled “on-the-fly” during Tx with the rest of the payload.
1) Pre-fill FIFO (in Sleep/Standby first or directly in Tx mode) until FifoThreshold or FifoFull is set
2) In Tx, wait for FifoThreshold or FifoEmpty to be set (i.e. FIFO is nearly empty)
3) Write bytes into the FIFO until FifoThreshold or FifoFull is set.
4) Continue to step 2 until the entire message has been written to the FIFO (PacketSent will fire when the last bit of the
packet has been sent).
For Rx:
FIFO must be unfilled “on-the-fly” during Rx to prevent FIFO overrun.
1) Start reading bytes from the FIFO when FifoEmpty is cleared or FifoThreshold becomes set.
2) Suspend reading from the FIFO if FifoEmpty fires before all bytes of the message have been read
3) Continue to step 1 until PayloadReady or CrcOk fires
4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode
2.1.13.6. Packet Filtering
The SX1276/77/78/79 packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are
made available to the uC, reducing significantly system power consumption and software complexity.
Sync Word Based
Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As
previously described, the Sync word recognition block is configured (size, value) in RegSyncConfig and RegSyncValue(i)
registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx.
Every received packet which does not start with this locally configured Sync word is automatically discarded and no
interrupt is generated.
When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted.
Note
Sync Word values containing 0x00 byte(s) are forbidden
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Address Based
Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync
must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word)
and each node has its own ID (address).
Two address based filtering options are available:
AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then the
packet is accepted and processed, otherwise it is discarded.
AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress.
If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with
a constant is useful for implementing broadcast in a multi-node networks
Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in
the FIFO. In addition, NodeAddress and AddressFiltering only apply to Rx. On Tx side, if address filtering is expected, the
address byte should simply be put into the FIFO like any other byte of the payload.
As address filtering requires a Sync word match, both features share the same interrupt flag SyncAddressMatch.
Length Based
In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If
received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded.
Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the
FIFO.
To disable this function the user should set the value of the PayloadLength to 2047.
CRC Based
The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message.
On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the
message
On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received.
The result of the comparison is stored in bit CrcOk.
By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function
can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady
interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler
and only the payload is made available in the FIFO. Two CRC implementations are selected with bit CrcWhiteningType.
Table 31 CRC Description
Crc Type
CrcWhiteningType
Polynomial
CCITT
0 (default)
X16
IBM
1
X16
+
X12
+
X15
+
X5
+
X2
Seed Value
Complemented
+1
0x1D0F
Yes
+1
0xFFFF
No
A C code implementation of each CRC type is proposed in Application Section 5.
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2.1.13.7. DC-Free Data Mechanisms
The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted
signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also
introduces data dependencies in the normal operation of the demodulator. Thus it is useful if the transmitted data is random
and DC free.
For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening.
Note
Only one of the two methods can be enabled at a time.
Manchester Encoding
Manchester encoding/decoding is enabled if DcFree = 01 and can only be used in Packet mode.
The NRZ data is converted to Manchester code by coding '1' as “10” and '0' as “01”.
In this case, the maximum chip rate is the maximum bit rate given in the specifications and the actual bit rate is half the chip
rate.
Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync word are
kept NRZ. However, the chip rate from preamble to CRC is the same and defined by BitRate in RegBitRate (Chip Rate =
Bit Rate NRZ = 2 x Bit Rate Manchester).
Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the
FIFO.
1/BR ...Sync
RF chips @ BR
User/NRZ bits
Manchester OFF
User/NRZ bits
Manchester ON
1/BR
...
1
1
1
0
1
0
0
1
0
0
1
Payload...
0
1
1
0
1
0
...
...
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
...
...
1
1
1
0
1
0
0
1
0
1
0
1
1
1
t
...
Figure 36. Manchester Encoding/Decoding
Data Whitening
Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission.
The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence.
Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved.
The whitening/de-whitening process is enabled if DcFree = 10. A 9-bit LFSR is used to generate a random sequence. The
payload and 2-byte CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened
on the receiver side by XORing with the same random sequence.
Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the
FIFO.
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L F S R P o ly n o m ia l = X 9 + X 5 + 1
X8
X7
X6
X5
X4
X3
T ran sm it d ata
X2
X1
X0
W hite ne d d a ta
Figure 37. Data Whitening Polynomial
2.1.13.8. Beacon Tx Mode
In some short range wireless network topologies a repetitive message, also known as beacon, is transmitted periodically
by a transmitter. The Beacon Tx mode allows for the re-transmission of the same packet without having to fill the FIFO
multiple times with the same data.
When BeaconOn in RegPacketConfig2 is set to 1, the FIFO can be filled only once in Sleep or Stdby mode with the
required payload. After a first transmission, FifoEmpty will go high as usual, but the FIFO content will be restored when the
chip exits Transmit mode. FifoEmpty, FifoFull and FifoLevel flags are also restored.
This feature is only available in Fixed packet format, with the Payload Length smaller than the FIFO size. The control of the
chip modes (Tx-Sleep-Tx....) can either be undertaken by the microcontroller, or be automated in the Top Sequencer. See
example in Section 2.1.13.8.
The Beacon Tx mode is exited by setting BeaconOn to 0, and clearing the FIFO by setting FifoOverrun to 1.
2.1.14. io-homecontrol® Compatibility Mode
The SX1276/77/78/79 features a io-homecontrol® compatibility mode. Please contact your local Semtech representative
for details on its implementation.
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2.2. SPI Interface
The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to
CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.
Three access modes to the registers are provided:
SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and
a read byte is received for the read access. The NSS pin goes low at the beginning of the frame and goes high after the
data byte.
BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally
between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the
beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the
FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data
byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the
last byte transfer.
The figure below shows a typical SPI single access to a register.
Figure 38. SPI Timing Diagram (single access)
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the
rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.
The first byte is the address byte. It is comprises:
A wnr bit, which is 1 for write access and 0 for read access.
Then 7 bits of address, MSB first.
The second byte is a data byte, either sent on MOSI by the master in case of a write access or received by the master on
MISO in case of read access. The data byte is transmitted MSB first.
Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without a rising NSS
edge and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read
at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented for each
new byte received.
The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is
therefore a special case of FIFO / BURST mode with only 1 data byte transferred.
During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written
register before the write operation.
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3. SX1276/77/78/79 Analog & RF Frontend Electronics
3.1. Power Supply Strategy
The SX1276/77/78/79 employs an internal voltage regulation scheme which provides stable operating voltage, and hence
device characteristics, over the full industrial temperature and operating voltage range of operation. This includes up to
+17 dBm of RF output power which is maintained from 1.8 V to 3.7 V and +20 dBm from 2.4 V to 3.7 V.
The SX1276/77/78/79 can be powered from any low-noise voltage source via pins VBAT_ANA, VBAT_RF and VBAT_DIG.
Decoupling capacitors should be connected, as suggested in the reference design of the applications section of this
document, on VR_PA, VR_DIG and VR_ANA pins to ensure correct operation of the built-in voltage regulators.
3.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to the supply voltage
dropping below a programmable threshold that is adjustable through the register RegLowBat. The interrupt signal can be
mapped to any of the DIO pins by programming RegDioMapping.
Note: This can be used in FSK or LoRa mode, but can only be configured while in FSK mode.
3.3. Frequency Synthesis
3.3.1. Crystal Oscillator
The crystal oscillator is the main timing reference of the SX1276/77/78/79. It is used as the reference for the PLL’s
frequency synthesis and as the clock signal for all digital processing.
The crystal oscillator startup time, TS_OSC, depends on the electrical characteristics of the crystal reference used, for
more information on the electrical specification of the crystal see section 5.1. The crystal connects to the Pierce oscillator
on pins XTA and XTB. The SX1276/77/78/79 optimizes the startup time and automatically triggers the PLL when the
oscillator signal is stable.
Optionally, an external clock can be used to replace the crystal oscillator. This typically takes the form of a tight tolerance
temperature compensated crystal oscillator (TCXO). When using an external clock source the bit TcxoInputOn of register
RegTcxo should be set to 1 and the external clock has to be provided on XTA (pin 5). XTB (pin 6) should be left open.
The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an
appropriate value of decoupling capacitor, CD.
XTA
XTB
NC
TCXO
32 MHz
OP
Vcc
GND
Vcc
CD
Figure 39. TCXO Connection
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3.3.2. CLKOUT Output
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 13) by modifying bits ClkOut in RegDioMapping2.
Two typical applications of the CLKOUT output include:
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the
initial crystal tolerance.
Note
To minimize the current consumption of the SX1276/77/78/79, please ensure that the CLKOUT signal is disabled
when not required.
3.3.3. PLL
The local oscillator of the SX1276/77/78/79 is derived from two almost identical fractional-N PLLs that are referenced to the
crystal oscillator circuit. Both PLLs feature a programmable bandwidth setting where one of four discrete preset bandwidths
may be accessed.
The SX1276/77/78/79 PLL uses a 19-bit sigma-delta modulator whose frequency resolution, constant over the whole
frequency range, is given by:
F XOSC
F STEP = --------------19
2
The carrier frequency is programmed through RegFrf, split across addresses 0x06 to 0x08:
F RF = F STEP Frf (23,0)
Note
The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the
least significant byte FrfLsb in RegFrfLsb is written. This allows the potential for user generation of m-ary FSK at
very low bit rates. This is possible where frequency modulation is achieved by direct programming of the
programmed RF centre frequency. To enable this functionality set the FastHopOn bit of register RegPllHop.
Three frequency bands are supported, defined as follows:
Table 32 Frequency Bands
Name
Frequency Limits
Products
Band 1 (HF)
862 (*779)-1020 (*960) MHz
SX1276/77/79
Band 2 (LF)
410-525 (*480) MHz
SX1276/77/78/79
Band 3 (LF)
137-175 (*160)MHz
SX1276/77/78/79
* For SX1279
3.3.4. RC Oscillator
All timing operations in the low-power Sleep state of the Top Level Sequencer rely on the accuracy of the internal lowpower RC oscillator. This oscillator is automatically calibrated at the device power-up not requiring any user input.
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3.4. Transmitter Description
The transmitter of SX1276/77/78/79 comprises the frequency synthesizer, modulator (both LoRa and FSK/OOK) and
power amplifier blocks, together with the DC biasing and ramping functionality that is provided through the VR_PA block.
3.4.1. Architecture Description
The architecture of the RF front end is shown in the following diagram:
Figure 40. RF Front-end Architecture Shows the Internal PA Configuration.
3.4.2. RF Power Amplifiers
PA_HF and PA_LF are high efficiency amplifiers capable of yielding RF power programmable in 1 dB steps from -4 to
+14dBm directly into a 50 ohm load with low current consumption. PA_LF covers the lower bands (up to 525 MHz), whilst
PA_HF will cover the upper bands (from 779 MHz). The output power is sensitive to the power supply voltage, and typically
their performance is expressed at 3.3V.
PA_HP (High Power), connected to the PA_BOOST pin, covers all frequency bands that the chip addresses. It permits
continuous operation at up to +17 dBm and duty cycled operation at up to +20dBm. For full details of operation at +20dBm
please consult section 3.4.3
Table 33 Power Amplifier Mode Selection Truth Table
Mode
PaSelect
Power Range
Pout Formula
0
PA_HF or PA_LF on RFO_HF or RFO_LF
-4 to +15dBm
Pout=Pmax-(15-OutputPower)
Pmax=10.8+0.6*MaxPower [dBm]
1
PA_HP on PA_BOOST, any frequency
+2 to +17dBm
Pout=17-(15-OutputPower) [dBm]
Notes - For +20 dBm restrictions on operation please consult the following .
- To ensure correct operation at the highest power levels ensure that the current limiter OcpTrim is adjusted to
permit delivery of the requisite supply current.
- If the PA_BOOST pin is not used it may be left floating.
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3.4.3. High Power +20 dBm Operation
The SX1276/77/78/79 have a high power +20 dBm capability on PA_BOOST pin, with the following settings:
Table 34 High Power Settings
Register
Address
Value for
High Power
Default value
PA_HF/LF or
+17dBm
Description
RegPaDac
0x4d
0x87
0x84
Set Pmax to +20dBm for PA_HP
Notes - High Power settings must be turned off when using PA_LF or PA_HF
- The Over Current Protection limit should be adapted to the actual power level, in RegOcp
Specific Absolute Maximum Ratings and Operating Range restrictions apply to the +20 dBm operation. They are listed in
Table 35 and Table 36.
Table 35 Operating Range, +20dBm Operation
Symbol
Description
Min
Max
Unit
DC_20dBm
Duty Cycle of transmission at +20 dBm output
-
1
%
VSWR_20dBm
Maximum VSWR at antenna port, +20 dBm output
-
3:1
-
Min
Max
Unit
2.4
3.7
V
Table 36 Operating Range, +20dBm Operation
Symbol
VDDop_20dBm
Description
Supply voltage, +20 dBm output
The duty cycle of transmission at +20 dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the
standard operating range [-40;+85°C]. For any other operating condition, contact your Semtech representative.
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DATASHEET
3.4.4. Over Current Protection
The power amplifiers of SX1276/77/78/79 are protected against current over supply in adverse RF load conditions by the
over current protection block. This has the added benefit of protecting battery chemistries with limited peak current
capability and minimising worst case PA consumption in battery life calculation. The current limiter value is controlled by
the OcpTrim bits in RegOcp, and is calculated according to the following formulae:
Table 37 Trimming of the OCP Current
OcpTrim
IMAX
Imax Formula
0 to 15
45 to 120 mA
45 + 5*OcpTrim [mA]
16 to 27
130 to 240 mA
-30 + 10*OcpTrim [mA]
27+
240 mA
240 mA
Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the SX1276/
77/78/79 is equal to Imax + IDDFS.
3.5. Receiver Description
3.5.1. Overview
The SX1276/77/78/79 features a digital receiver with the analog to digital conversion process being performed directly
following the LNA-Mixers block. In addition to the LoRa modulation scheme the low-IF receiver is able to demodulate ASK,
OOK, (G)FSK and (G)MSK modulation. All filtering, demodulation, gain control, synchronization and packet handling is
performed digitally allowing a high degree of programmable flexibility. The receiver also has automatic gain calibration, this
improves the precision of RSSI measurement and enhances image rejection.
3.5.2. Receiver Enabled and Receiver Active States
In the receiver operating mode two states of functionality are defined. Upon initial transition to receiver operating mode the
receiver is in the ‘receiver-enabled’ state. In this state the receiver awaits for either the user defined valid preamble or RSSI
detection criterion to be fulfilled. Once met the receiver enters ‘receiver-active’ state. In this second state the received
signal is processed by the packet engine and top level sequencer. For a complete description of the digital functions of the
SX1276/77/78/79 receiver please see section 4 of the datasheet.
3.5.3. Automatic Gain Control In FSK/OOK Mode
The AGC feature allows receiver to handle a wide Rx input dynamic range from the sensitivity level up to maximum input
level of 0dBm or more, whilst optimizing the system linearity.
The following table shows typical NF and IIP3 performances for the SX1276/77/78/79 LNA gains available.
Rev. 7 - May 2020
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Table 38 LNA Gain Control and Performances
Gain
Setting
LnaGain
Relative LNA
Gain [dB]
NF
Band 3/2/1
[dB]
IIP3
Band 3/2/1
[dBm]
Pin = 5.
RegSyncValue6
(0x2d)
7-0
SyncValue(23:16)
rw
0x01
*
6th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 6.
RegSyncValue7
(0x2e)
7-0
SyncValue(15:8)
rw
0x01
*
7th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) >= 7.
RegSyncValue8
(0x2f)
7-0
SyncValue(7:0)
rw
0x01
*
8th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) = 8.
RegSyncConfig
(0x27)
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Name
(Address)
RegPacketConfig1
(0x30)
DATASHEET
Bits
Variable Name
Mode
Default
value
7
PacketFormat
rw
0x01
Defines the packet format used:
0 Fixed length
1 Variable length
FSK/OOK Description
6-5
DcFree
rw
0x00
Defines DC-free encoding/decoding performed:
00 None (Off)
01 Manchester
10 Whitening
11 reserved
4
CrcOn
rw
0x01
Enables CRC calculation/check (Tx/Rx):
0 Off
1 On
0x00
Defines the behavior of the packet handler when CRC check fails:
0 Clear FIFO and restart new packet reception. No
PayloadReady interrupt issued.
1 Do not clear FIFO. PayloadReady interrupt issued.
3
CrcAutoClearOff
rw
2-1
AddressFiltering
rw
0x00
Defines address based filtering in Rx:
00 None (Off)
01 Address field must match NodeAddress
10 Address field must match NodeAddress or
BroadcastAddress
11 reserved
0
CrcWhiteningType
rw
0x00
Selects the CRC and whitening algorithms:
0 CCITT CRC implementation with standard whitening
1 IBM CRC implementation with alternate whitening
7
unused
r
-
6
DataMode
rw
0x01
Data processing mode:
0 Continuous mode
1 Packet mode
unused
5
IoHomeOn
rw
0x00
Enables the io-homecontrol® compatibility mode
0 Disabled
1 Enabled
4
IoHomePowerFrame
rw
0x00
reserved - Linked to io-homecontrol® compatibility mode
3
BeaconOn
rw
0x00
Enables the Beacon mode in Fixed packet format
2-0
PayloadLength(10:8)
rw
0x00
Packet Length Most significant bits
RegPayloadLength
(0x32)
7-0
PayloadLength(7:0)
rw
0x40
If PacketFormat = 0 (fixed), payload length.
If PacketFormat = 1 (variable), max length in Rx, not used in Tx.
RegNodeAdrs
(0x33)
7-0
NodeAddress
rw
0x00
RegBroadcastAdrs
(0x34)
7-0
BroadcastAddress
rw
0x00
RegPacketConfig2
(0x31)
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Node address used in address filtering.
Broadcast address used in address filtering.
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WIRELESS & SENSING PRODUCTS
Name
(Address)
RegFifoThresh
(0x35)
Variable Name
Bits
DATASHEET
Mode
Default
value
7
TxStartCondition
rw
0x01
*
6
unused
r
-
5-0
FifoThreshold
rw
0x0f
FSK/OOK Description
Defines the condition to start packet transmission:
0 FifoLevel (i.e. the number of bytes in the FIFO exceeds
FifoThreshold)
1 FifoEmpty goes low(i.e. at least one byte in the FIFO)
unused
Used to trigger FifoLevel interrupt, when:
number of bytes in FIFO >= FifoThreshold + 1
Sequencer registers
7
SequencerStart
wt
0x00
Controls the top level Sequencer
When set to ‘1’, executes the “Start” transition.
The sequencer can only be enabled when the chip is in Sleep or
Standby mode.
6
SequencerStop
wt
0x00
Forces the Sequencer Off.
Always reads ‘0’
5
IdleMode
rw
0x00
Selects chip mode during the state:
0: Standby mode
1: Sleep mode
0x00
Controls the Sequencer transition when SequencerStart is set to 1
in Sleep or Standby mode:
00: to LowPowerSelection
01: to Receive state
10: to Transmit state
11: to Transmit state on a FifoLevel interrupt
4-3
FromStart
rw
RegSeqConfig1
(0x36)
2
LowPowerSelection
rw
0x00
Selects the Sequencer LowPower state after a to
LowPowerSelection transition:
0: SequencerOff state with chip on Initial mode
1: Idle state with chip on Standby or Sleep mode depending on
IdleMode
Note:
Initial mode is the chip LowPower mode at
Sequencer Start.
1
FromIdle
rw
0x00
Controls the Sequencer transition from the Idle state on a T1
interrupt:
0: to Transmit state
1: to Receive state
0
FromTransmit
rw
0x00
Controls the Sequencer transition from the Transmit state:
0: to LowPowerSelection on a PacketSent interrupt
1: to Receive state on a PacketSent interrupt
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Name
(Address)
Variable Name
Bits
7-5
FromReceive
DATASHEET
Mode
rw
Default
value
0x00
FSK/OOK Description
Controls the Sequencer transition from the Receive state
000 and 111: unused
001: to PacketReceived state on a PayloadReady interrupt
010: to LowPowerSelection on a PayloadReady interrupt
011: to PacketReceived state on a CrcOk interrupt (1)
100: to SequencerOff state on a Rssi interrupt
101: to SequencerOff state on a SyncAddress interrupt
110: to SequencerOff state on a PreambleDetect interrupt
Irrespective of this setting, transition to LowPowerSelection on a
T2 interrupt
(1) If the CRC is wrong (corrupted packet, with CRC on but
CrcAutoClearOn=0), the PayloadReady interrupt will drive the
sequencer to RxTimeout state.
RegSeqConfig2
(0x37)
4-3
FromRxTimeout
rw
0x00
Controls the state-machine transition from the Receive state on a
RxTimeout interrupt (and on PayloadReady if FromReceive =
011):
00: to Receive State, via ReceiveRestart
01: to Transmit state
10: to LowPowerSelection
11: to SequencerOff state
Note: RxTimeout interrupt is a TimeoutRxRssi,
TimeoutRxPreamble or TimeoutSignalSync interrupt
RegTimerResol
(0x38)
2-0
FromPacketReceived
rw
0x00
Controls the state-machine transition from the PacketReceived
state:
000: to SequencerOff state
001: to Transmit state on a FifoEmpty interrupt
010: to LowPowerSelection
011: to Receive via FS mode, if frequency was changed
100: to Receive state (no frequency change)
7-4
unused
r
-
unused
0x00
Resolution of Timer 1
00: Timer1 disabled
01: 64 us
10: 4.1 ms
11: 262 ms
3-2
Timer1Resolution
rw
1-0
Timer2Resolution
rw
0x00
Resolution of Timer 2
00: Timer2 disabled
01: 64 us
10: 4.1 ms
11: 262 ms
RegTimer1Coef
(0x39)
7-0
Timer1Coefficient
rw
0xf5
Multiplying coefficient for Timer 1
RegTimer2Coef
(0x3a)
7-0
Timer2Coefficient
rw
0x20
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Multiplying coefficient for Timer 2
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Name
(Address)
Bits
Variable Name
DATASHEET
Mode
Default
value
FSK/OOK Description
Service registers
RegImageCal
(0x3b)
7
AutoImageCalOn
rw
0x00
*
Controls the Image calibration mechanism
0 Calibration of the receiver depending on the temperature is
disabled
1 Calibration of the receiver depending on the temperature
enabled.
6
ImageCalStart
wt
-
Triggers the IQ and RSSI calibration when set in Standby mode.
5
ImageCalRunning
r
0x00
4
unused
r
-
3
2-1
RegTemp
(0x3c)
TempChange
TempThreshold
r
rw
Set to 1 while the Image and RSSI calibration are running.
Toggles back to 0 when the process is completed
unused
0x00
IRQ flag witnessing a temperature change exceeding
TempThreshold since the last Image and RSSI calibration:
0 Temperature change lower than TempThreshold
1 Temperature change greater than TempThreshold
0x01
Temperature change threshold to trigger a new I/Q calibration
00 5 °C
01 10 °C
10 15 °C
11 20 °C
Controls the temperature monitor operation:
0 Temperature monitoring done in all modes except Sleep and
Standby
1 Temperature monitoring stopped.
0
TempMonitorOff
rw
0x00
7-0
TempValue
r
-
Measured temperature
-1°C per Lsb
Needs calibration for absolute accuracy
7-4
unused
r
-
unused
3
LowBatOn
rw
0x00
Low Battery detector enable signal
0 LowBat detector disabled
1 LowBat detector enabled
0x02
Trimming of the LowBat threshold:
000 1.695 V
001 1.764 V
010 1.835 V (d)
011 1.905 V
100 1.976 V
101 2.045 V
110 2.116 V
111 2.185 V
RegLowBat
(0x3d)
2-0
LowBatTrim
rw
Status registers
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Name
(Address)
RegIrqFlags1
(0x3e)
RegIrqFlags2
(0x3f)
Bits
Variable Name
DATASHEET
Mode
Default
value
FSK/OOK Description
7
ModeReady
r
-
Set when the operation mode requested in Mode, is ready
- Sleep: Entering Sleep mode
- Standby: XO is running
- FS: PLL is locked
- Rx: RSSI sampling starts
- Tx: PA ramp-up completed
Cleared when changing the operating mode.
6
RxReady
r
-
Set in Rx mode, after RSSI, AGC and AFC.
Cleared when leaving Rx.
5
TxReady
r
-
Set in Tx mode, after PA ramp-up.
Cleared when leaving Tx.
4
PllLock
r
-
Set (in FS, Rx or Tx) when the PLL is locked.
Cleared when it is not.
3
Rssi
rwc
-
Set in Rx when the RssiValue exceeds RssiThreshold.
Cleared when leaving Rx or setting this bit to 1.
2
Timeout
r
-
Set when a timeout occurs
Cleared when leaving Rx or FIFO is emptied.
1
PreambleDetect
rwc
-
Set when the Preamble Detector has found valid Preamble.
bit clear when set to 1
0
SyncAddressMatch
rwc
-
Set when Sync and Address (if enabled) are detected.
Cleared when leaving Rx or FIFO is emptied.
This bit is read only in Packet mode, rwc in Continuous mode
7
FifoFull
r
-
Set when FIFO is full (i.e. contains 66 bytes), else cleared.
6
FifoEmpty
r
-
Set when FIFO is empty, and cleared when there is at least 1 byte
in the FIFO.
5
FifoLevel
r
-
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold, else cleared.
4
FifoOverrun
rwc
-
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The FIFO then
becomes immediately available for the next transmission /
reception.
3
PacketSent
r
-
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx
2
PayloadReady
r
-
Set in Rx when the payload is ready (i.e. last byte received and
CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared
when FIFO is empty.
1
CrcOk
r
-
Set in Rx when the CRC of the payload is Ok. Cleared when FIFO
is empty.
0
LowBat
rwc
-
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set to 1 by the user.
IO control registers
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Name
(Address)
RegDioMapping1
(0x40)
RegDioMapping2
(0x41)
DATASHEET
Bits
Variable Name
Mode
Default
value
7-6
Dio0Mapping
rw
0x00
5-4
Dio1Mapping
rw
0x00
3-2
Dio2Mapping
rw
0x00
1-0
Dio3Mapping
rw
0x00
See Table 18 for mapping in LoRa mode
7-6
Dio4Mapping
rw
0x00
5-4
Dio5Mapping
rw
0x00
See Table 29 for mapping in Continuous mode
SeeTable 30 for mapping in Packet mode
3-1
reserved
rw
0x00
reserved. Retain default value
0x00
Allows the mapping of either Rssi Or PreambleDetect to the DIO
pins, as summarized on Table 29 and Table 30
0 Rssi interrupt
1 PreambleDetect interrupt
0
MapPreambleDetect
rw
FSK/OOK Description
Mapping of pins DIO0 to DIO5
Version register
RegVersion
(0x42)
7-0
Version
r
Version code of the chip. Bits 7-4 give the full revision number;
0x121 bits 3-0 give the metal mask revision number.
Additional registers
RegPllHop
(0x44)
RegTcxo
(0x4b)
RegPaDac
(0x4d)
RegFormerTemp
(0x5b)
RegBitrateFrac
(0x5d)
7
FastHopOn
rw
0x00
Bypasses the main state machine for a quick frequency hop.
Writing RegFrfLsb will trigger the frequency change.
0 Frf is validated when FSTx or FSRx is requested
1 Frf is validated triggered when RegFrfLsb is written
6-0
reserved
rw
0x2d
reserved
7-5
reserved
rw
0x00
reserved. Retain default value
4
TcxoInputOn
rw
0x00
Controls the crystal oscillator
0 Crystal Oscillator with external Crystal
1 External clipped sine TCXO AC-connected to XTA pin
3-0
reserved
rw
0x09
Reserved. Retain default value.
7-3
reserved
rw
0x10
reserved. Retain default value
2-0
PaDac
rw
0x04
Enables the +20dBm option on PA_BOOST pin
0x04 Default value
0x07 +20dBm on PA_BOOST when OutputPower=1111
7-0
FormerTemp
rw
-
Temperature saved during the latest IQ (RSSI and Image)
calibration. Same format as TempValue in RegTemp.
7-4
unused
r
0x00
unused
Fractional part of the bit rate divider (Only valid for FSK)
If BitRateFrac> 0 then:
3-0
Rev. 7 - May 2020
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BitRateFrac
rw
0x00
Page 105
FXOSC
BitRate = -----------------------------------------------------------------------BitRate (15,0) + BitrateFrac
------------------------------16
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Name
(Address)
RegAgcRef
(0x61)
DATASHEET
Bits
Variable Name
Mode
Default
value
7-6
unused
r
-
FSK/OOK Description
unused
Sets the floor reference for all AGC thresholds:
AGC Reference[dBm]=
-174dBm+10*log(2*RxBw)+SNR+AgcReferenceLevel
SNR = 8dB, fixed value
5-0
AgcReferenceLevel
rw
0x19
RegAgcThresh1
(0x62)
7-5
unused
r
-
4-0
AgcStep1
rw
0x0c
Defines the 1st AGC Threshold
RegAgcThresh2
(0x63)
7-4
AgcStep2
rw
0x04
Defines the 2nd AGC Threshold:
3-0
AgcStep3
rw
0x0b
Defines the 3rd AGC Threshold:
RegAgcThresh3
(0x64)
7-4
AgcStep4
rw
0x0c
Defines the 4th AGC Threshold:
3-0
AgcStep5
rw
0x0c
Defines the 5th AGC Threshold:
unused
1. For Wafer deliveries, refer to the corresponding “Wafer Delivery Specification”
4.3. Band Specific Additional Registers
The registers in the address space from 0x61 to 0x73 are specific for operation in the lower frequency bands (below 525
MHz), or in the upper frequency bands (above 779 MHz). Their programmed value may differ, and are retained when
switching from lower to high frequency and vice-versa. The access to the band specific registers is granted by enabling or
disabling the bit 3 LowFrequencyModeOn of the RegOpMode register. By default, the bit LowFrequencyModeOn is at ‘1’
indicating that the registers are configured for the low frequency band.
Table 43 Low Frequency Additional Registers
Name
(Address)
RegAgcRefLf
(0x61)
Bits
Variable Name
Mode
Default
value
7-6
unused
r
-
Low Frequency Additional Registers
unused
Sets the floor reference for all AGC thresholds:
AGC Reference[dBm]=
-174dBm+10*log(2*RxBw)+SNR+AgcReferenceLevel
SNR = 8dB, fixed value
5-0
AgcReferenceLevel
rw
0x19
RegAgcThresh1Lf
(0x62)
7-5
unused
r
-
4-0
AgcStep1
rw
0x0c
Defines the 1st AGC Threshold
RegAgcThresh2Lf
(0x63)
7-4
AgcStep2
rw
0x04
Defines the 2nd AGC Threshold:
3-0
AgcStep3
rw
0x0b
Defines the 3rd AGC Threshold:
RegAgcThresh3Lf
(0x64)
7-4
AgcStep4
rw
0x0c
Defines the 4th AGC Threshold:
3-0
AgcStep5
rw
0x0c
Defines the 5th AGC Threshold:
RegPllLf
(0x70)
7-6
PllBandwidth
rw
0x03
Controls the PLL bandwidth:
00 75 kHz
10 225 kHz
01 150 kHz
11 300 kHz
5-0
reserved
rw
0x10
reserved. Retain default value
Rev. 7 - May 2020
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unused
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Table 44 High Frequency Additional Registers
Name
(Address)
RegAgcRefHf
(0x61)
Bits
Variable Name
Mode
Default
value
7-6
unused
r
-
Low Frequency Additional Registers
unused
Sets the floor reference for all AGC thresholds:
AGC Reference[dBm]=
-174dBm+10*log(2*RxBw)+SNR+AgcReferenceLevel
SNR = 8dB, fixed value
5-0
AgcReferenceLevel
rw
0x1c
RegAgcThresh1Hf
(0x62)
7-5
unused
r
-
4-0
AgcStep1
rw
0x0e
Defines the 1st AGC Threshold
RegAgcThresh2Hf
(0x63)
7-4
AgcStep2
rw
0x05
Defines the 2nd AGC Threshold:
3-0
AgcStep3
rw
0x0b
Defines the 3rd AGC Threshold:
RegAgcThresh3Hf
(0x64)
7-4
AgcStep4
rw
0x0c
Defines the 4th AGC Threshold:
3-0
AgcStep5
rw
0x0c
Defines the 5th AGC Threshold:
RegPllHf
(0x70)
7-6
PllBandwidth
rw
0x03
Controls the PLL bandwidth:
00 75 kHz
10 225 kHz
01 150 kHz
11 300 kHz
5-0
reserved
rw
0x10
reserved. Retain default value
Rev. 7 - May 2020
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unused
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4.4. LoRa Mode Register Map
This section details the SX1276/77/78/79 register mapping and the precise contents of each register in LoRa mode.
It is essential to understand that the LoRa modem is controlled independently of the FSK modem. Therefore, care should
be taken when accessing the registers, especially as some register may have the same name in LoRa or FSK mode.
The LoRa registers are only accessible when the device is set in Lora mode (and, in the same way, the FSK register are
only accessible in FSK mode). However, in some cases, it may be necessary to access some of the FSK register while in
LoRa mode. To this aim, the AccesSharedReg bit was created in the RegOpMode register. This bit, when set to ‘1’, will
grant access to the FSK register 0x0D up to the register 0x3F. Once the setup has been done, it is strongly recommended
to clear this bit so that LoRa register can be accessed normally.
Convention: r: read, w: write, c: set to clear and t: trigger.
Name
(Address)
RegFifo
(0x00)
Bits
7-0
Variable Name
Fifo
Mode Reset
rw
0x00
LoRa Description
LoRa base-band FIFO data input/output. FIFO is cleared an not
accessible when device is in SLEEP mode
Common Register Settings
7
RegOpMode
(0x01)
LongRangeMode
rw
0x0
0 FSK/OOK Mode
1 LoRa Mode
This bit can be modified only in Sleep mode. A write operation on
other device modes is ignored.
6
AccessSharedReg
rw
0x0
This bit operates when device is in Lora mode; if set it allows
access to FSK registers page located in address space
(0x0D:0x3F) while in LoRa mode
0 Access LoRa registers page 0x0D: 0x3F
1 Access FSK registers page (in mode LoRa) 0x0D: 0x3F
5-4
reserved
r
0x00
reserved
3
LowFrequencyModeOn
rw
0x01
Access Low Frequency Mode registers
0 High Frequency Mode (access to HF test registers)
1 Low Frequency Mode (access to LF test registers)
2-0
Mode
rwt
0x01
Device modes
000 SLEEP
001 STDBY
010 Frequency synthesis TX (FSTX)
011 Transmit (TX)
100 Frequency synthesis RX (FSRX)
101 Receive continuous (RXCONTINUOUS)
110 receive single (RXSINGLE)
111 Channel activity detection (CAD)
(0x02)
7-0
reserved
r
0x00
-
(0x03)
7-0
reserved
r
0x00
-
(0x04)
7-0
reserved
rw
0x00
-
(0x05)
7-0
reserved
r
0x00
-
RegFrMsb
(0x06)
7-0
Frf(23:16)
rw
0x6c
MSB of RF carrier frequency
RegFrMid
(0x07)
7-0
Frf(15:8)
rw
0x80
MSB of RF carrier frequency
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Name
(Address)
Bits
Variable Name
DATASHEET
Mode Reset
LoRa Description
LSB of RF carrier frequency
RegFrLsb
(0x08)
7-0
Frf(7:0)
rwt
F(XOSC) Frf
f RF = -----------------------------------19
2
0x00
Resolution is 61.035 Hz if F(XOSC) = 32 MHz. Default value is
0x6c8000 = 434 MHz. Register values must be modified only when
device is in SLEEP or STAND-BY mode.
Registers for RF blocks
RegPaConfig
(0x09)
RegPaRamp
(0x0A)
7
PaSelect
rw
0x00
Selects PA output pin
0 RFO pin. Output power is limited to +14 dBm.
1 PA_BOOST pin. Output power is limited to +20 dBm
6-4
MaxPower
rw
0x04
Select max output power: Pmax=10.8+0.6*MaxPower [dBm]
3-0
OutputPower
rw
0x0f
Pout=Pmax-(15-OutputPower) if PaSelect = 0 (RFO pin)
Pout=17-(15-OutputPower)
if PaSelect = 1 (PA_BOOST pin)
7-5
unused
r
-
unused
4
reserved
rw
0x00
reserved
3-0
PaRamp(3:0)
rw
0x09
Rise/Fall time of ramp up/down in FSK
0000 3.4 ms
0001 2 ms
0010 1 ms
0011 500 us
0100 250 us
0101 125 us
0110 100 us
0111 62 us
1000 50 us
1001 40 us
1010 31 us
1011 25 us
1100 20 us
1101 15 us
1110 12 us
1111 10 us
7-6
unused
r
0x00
unused
5
OcpOn
rw
0x01
Enables overload current protection (OCP) for PA:
0 OCP disabled
1 OCP enabled
0x0b
Trimming of OCP current:
Imax = 45+5*OcpTrim [mA] if OcpTrim = 0)
(see section 3.5.5 for details)
Current RSSI value (dBm)
RegRssiValu
e
(0x1B)
7-0
Rssi
r
RSSI[dBm] = -157 + Rssi (using HF output port)
or
RSSI[dBm] = -164 + Rssi (using LF output port)
n/a
(see section 3.5.5 for details)
7
RegHopChan
nel
(0x1C)
PllTimeout
r
n/a
PLL failed to lock while attempting a TX/RX/CAD operation
1 PLL did not lock
0 PLL did lock
6
CrcOnPayload
r
n/a
CRC Information extracted from the received packet header
(Explicit header mode only)
0 Header indicates CRC off
1 Header indicates CRC on
5-0
FhssPresentChannel
r
n/a
Current value of frequency hopping channel in use.
Rev. 7 - May 2020
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Name
(Address)
Bits
7-4
Variable Name
Bw
DATASHEET
Mode Reset
rw
0x07
Signal bandwidth:
0000 7.8 kHz
0001 10.4 kHz
0010 15.6 kHz
0011 20.8kHz
0100 31.25 kHz
0101 41.7 kHz
0110 62.5 kHz
0111 125 kHz
1000 250 kHz
1001 500 kHz
other values reserved
In the lower band (169MHz), signal bandwidths 8&9 are not
supported)
RegModemC
onfig1
(0x1D)
RegModemC
onfig2
(0x1E)
RegSymbTim
eoutLsb
(0x1F)
LoRa Description
3-1
CodingRate
rw
‘001’
Error coding rate
001 4/5
010 4/6
011 4/7
100 4/8
All other values reserved
In implicit header mode should be set on receiver to determine
expected coding rate. See 4.1.1.3
0
ImplicitHeaderModeOn
rw
0x0
0 Explicit Header mode
1 Implicit Header mode
7-4
SpreadingFactor
rw
0x07
SF rate (expressed as a base-2 logarithm)
6 64 chips / symbol
7 128 chips / symbol
8 256 chips / symbol
9 512 chips / symbol
10 1024 chips / symbol
11 2048 chips / symbol
12 4096 chips / symbol
other values reserved.
3
TxContinuousMode
rw
0
0 normal mode, a single packet is sent
1 continuous mode, send multiple packets across the FIFO
(used for spectral analysis)
2
RxPayloadCrcOn
rw
0x00
Enable CRC generation and check on payload:
0 CRC disable
1 CRC enable
If CRC is needed, RxPayloadCrcOn should be set:
- in Implicit header mode: on Tx and Rx side
- in Explicit header mode: on the Tx side alone (recovered from the
header in Rx side)
1-0
SymbTimeout(9:8)
rw
0x00
RX Time-Out MSB
7-0
SymbTimeout(7:0)
Rev. 7 - May 2020
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rw
0x64
RX Time-Out LSB
RX operation time-out value expressed as number of symbols:
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Name
(Address)
Bits
Variable Name
DATASHEET
Mode Reset
LoRa Description
RegPreamble
Msb
7-0
(0x20)
PreambleLength(15:8)
rw
0x0
Preamble length MSB, = PreambleLength + 4.25 Symbols
See 4.1.1 for more details.
RegPreamble
Lsb
7-0
(0x21)
PreambleLength(7:0)
rw
0x8
Preamble Length LSB
rw
0x1
Payload length in bytes. The register needs to be set in implicit
header mode for the expected packet length. A 0 value is not
permitted
rw
0xff
Maximum payload length; if header payload length exceeds value a
header CRC error is generated. Allows filtering of packet with a bad
size.
rw
0x0
Symbol periods between frequency hops. (0 = disabled). 1st hop
always happen after the 1st header symbol
FifoRxByteAddrPtr
r
n/a
Current value of RX databuffer pointer (address of last byte written
by Lora receiver)
Unused
r
0x00
LowDataRateOptimize
rw
0x00
0 Disabled
1 Enabled; mandated for when the symbol length exceeds 16ms
AgcAutoOn
rw
0x00
0 LNA gain set by register LnaGain
1 LNA gain set by the internal AGC loop
1-0
Reserved
rw
0x00
Reserved
7-0
PpmCorrection
rw
0x00
Data rate offset value, used in conjunction with AFC
7-4
Reserved
r
n/a
Reserved
RegPayloadL
ength
(0x22)
7-0
RegMaxPayl
oadLength
(0x23)
7-0
RegHopPerio
d
(0x24)
7-0
RegFifoRxByt
eAddr
7-0
(0x25)
RegModemC
onfig3
(0x26)
7-4
3
2
(0x27)
PayloadLength(7:0)
PayloadMaxLength(7:0)
FreqHoppingPeriod(7:0)
Estimated frequency error from modem
MSB of RF Frequency Error
RegFeiMsb
(0x28)
3-0
FreqError(19:16)
r
0x0
RegFeiMid
(0x29)
7-0
FreqError(15:8)
r
0x0
RegFeiLsb
(0x2A)
7-0
FreqError(7:0)
r
0x0
(0x2B)
-
Reserved
r
n/a
Reserved
RegRssiWide
band
(0x2C)
7-0
RssiWideband(7:0)
r
n/a
Wideband RSSI measurement used to locally generate a random
number
(0x2D) (0x2E)
-
Reserved
r
n/a
Reserved
0x2F
7-0
IfFreq2
rw
0x20
See errata note
Rev. 7 - May 2020
©2020 Semtech Corporation
24
FreqError 2
BW kHz
F Error = ------------------------------------------ -----------------------F xtal
500
Middle byte of RF Frequency Error
LSB of RF Frequency Error
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Name
(Address)
0x30
Bits
Variable Name
DATASHEET
Mode Reset
LoRa Description
7-0
IfFreq1
rw
0x00
See errata note
7
AutomaticIFOn
rw
0x1
Should be set to 0x0 after each reset (POR on manual)
See errata note for more information
6-3
Reserved
r
0xC0
Reserved
2-0
DetectionOptimize
rw
0x03
LoRa Detection Optimize
0x03 SF7 to SF12
0x05 SF6
-
Reserved
r
n/a
Reserved
7
Reserved
rw
0x0
6
InvertIQ RX
rw
0x0
Invert the LoRa I and Q signals in RX path
0 normal mode
1 I and Q signals are inverted
5-1
Reserved
rw
0x13
Reserved
0
InvertIQ TX
rw
0x0
Invert the LoRa I and Q signals in TX path
0 normal mode
1 I and Q signals are inverted
(0x34) (0x35)
7-0
Reserved
r
n/a
Reserved
RegHighBW
Optimize1
(0x36)
7-0
HighBWOptimize1
rw
0x20
Optimization for 500 kHz bandwidth. See errata note.
RegDetection
Threshold
(0x37)
7-0
DetectionThreshold
rw
0x0A
LoRa detection threshold
0x0A SF7 to SF12
0x0C SF6
(0x38)
-
Reserved
r
n/a
Reserved
RegSyncWor
d
(0x39)
7-0
SyncWord
rw
0x12
LoRa Sync Word
Value 0x34 is reserved for LoRaWAN networks
RegHighBW
Optimize1
(0x3A)
7-0
HighBWOptimize2
rw
0x20
Optimization for 500 kHz bandwidth. See errata note.
RegInvertIQ2
(0x3B)
7-0
InvertIQ2
rw
0x1D
Set to 0x19 for inverted IQ
(0x3C) (0x3F)
-
Reserved
r
n/a
Reserved
RegDetectOp
timize
(0x31)
(0x32)
RegInvertIQ
(0x33)
Rev. 7 - May 2020
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Reserved
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5. Application Information
5.1. Crystal Resonator Specification
Table 45 shows the crystal resonator specification for the crystal reference oscillator circuit of the SX1276/77/78/79. This
specification covers the full range of operation of the SX1276/77/78/79 and is employed in the reference design.
Table 45 Crystal Specification
Symbol
Description
FXOSC
Conditions
Min
Typ
Max
XTAL Frequency
-
32
-
MHz
RS
XTAL Serial Resistance
-
15
100
ohms
C0
XTAL Shunt Capacitance
-
1
3
pF
CFOOT
External Foot Capacitance
10
15
22
pF
CLOAD
Crystal Load Capacitance
6
-
12
pF
On each pin XTA and XTB
Unit
Notes - the initial frequency tolerance, temperature stability and aging performance should be chosen in accordance with
the target operating temperature range and the receiver bandwidth selected.
- the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL.
5.2. Reset of the Chip
A power-on reset of the SX1276/77/78/79 is triggered at power up. Additionally, a manual reset can be issued by
controlling pin 7.
5.2.1. POR
If the application requires the disconnection of VDD from the SX1276/77/78/79, despite of the extremely low Sleep Mode
current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI
bus. Pin 7 (NRESET) should be left floating during the POR sequence.
Figure 42. POR Timing Diagram
Please note that any CLKOUT activity can also be used to detect that the chip is ready.
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5.2.2. Manual Reset
A manual reset of the SX1276/77/78/79 is possible even for applications in which VDD cannot be physically disconnected.
Pin 7 should be pulled low for a hundred microseconds, and then released. The user should then wait for 5 ms before using
the chip.
Figure 43. Manual Reset Timing Diagram
Note
whilst pin 7 is driven low, an over current consumption of up to one milliampere can be seen on VDD.
5.3. Top Sequencer: Listen Mode Examples
In this scenario, the circuit spends most of the time in Idle mode, during which only the RC oscillator is on. Periodically the
receiver wakes up and looks for incoming signal. If a wanted signal is detected, the receiver is kept on and data are
analyzed. Otherwise, if there was no wanted signal for a defined period of time, the receiver is switched off until the next
receive period.
During Listen mode, the Radio stays most of the time in a Low Power mode, resulting in very low average power
consumption. The general timing diagram of this scenario is given in Figure 44.
Listen mode : principle
Receive
Idle ( Sleep + RC )
Receive
Idle
Figure 44. Listen Mode: Principle
An interrupt request is generated on a packet reception. The user can then take appropriate action.
Depending on the application and environment, there are several ways to implement Listen mode:
Wake on a PreambleDetect interrupt
Wake on a SyncAddress interrupt
Wake on a PayloadReady interrupt
5.3.1. Wake on Preamble Interrupt
In one possible scenario, the sequencer polls for a Preamble detection. If a preamble signal is detected, the sequencer is
switched off and the circuit stays in Receive mode until the user switches modes. Otherwise, the receiver is switched off
until the next Rx period.
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5.3.1.1. Timing Diagram
When no signal is received, the circuit wakes every Timer1 + Timer2 and switches to Receive mode for a time defined by
Timer2, as shown on the following diagram. If no Preamble is detected, it then switches back to Idle mode, i.e. Sleep mode
with RC oscillator on.
No received signal
Receive
Idle ( Sleep + RC )
Receive
Timer2
Idle
Timer2
Timer1
Timer1
Timer1
Figure 45. Listen Mode with No Preamble Received
If a Preamble signal is detected, the Sequencer is switched off. The PreambleDetect signal can be mapped to DIO4, in
order to request the user's attention. The user can then take appropriate action.
Received signal
Preamble ( As long as T1 + 2 * T2 )
Idle ( Sleep + RC )
Timer1
Sync
Word
Timer2
Payload
Crc
Receive
Timer2
Preamble
Detect
Figure 46. Listen Mode with Preamble Received
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5.3.1.2. Sequencer Configuration
The following graph shows Listen mode - Wake on PreambleDetect state machine:
State Machine
Sequencer Off
&
Initial mode = Sleep or Standby
IdleMode = 1 : Sleep
Start bit set
Start
FromStart = 00
LowPower
Selection
LowPowerSelection = 1
Idle
On T1
FromIdle = 1
On T2
Receive
On PreambleDetect
FromReceive = 110
Sequencer Off
Figure 47. Wake On PreambleDetect State Machine
This example configuration is achieved as follows:
Table 46 Listen Mode with PreambleDetect Condition Settings
Variable
IdleMode
FromStart
LowPowerSelection
FromIdle
FromReceive
Effect
1: Sleep mode
00: To LowPowerSelection
1: To Idle state
1: To Receive state on T1 interrupt
110: To Sequencer Off on PreambleDetect interrupt
TTimer2 defines the maximum duration the chip stays in Receive mode as long as no Preamble is detected. In order to
optimize power consumption, Timer2 must be set just long enough for Preamble detection.
TTimer1 + TTimer2 defines the cycling period, i.e. time between two Preamble polling starts. In order to optimize average
power consumption, Timer1 should be relatively long. However, increasing Timer1 also extends packet reception duration.
In order to insure packet detection and optimize the receiver's power consumption, the received packet Preamble should
be as long as TTimer1 + 2 x TTimer2.
An example of DIO configuration for this mode is described in the following table:
Table 47 Listen Mode with PreambleDetect Condition Recommended DIO Mapping
DIO
0
1
3
4
Value
01
00
00
11
Rev. 7 - May 2020
©2020 Semtech Corporation
Description
CrcOk
FifoLevel
FifoEmpty
PreambleDetect – Note: MapPreambleDetect bit should be set.
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5.3.2. Wake on SyncAddress Interrupt
In another possible scenario, the sequencer polls for a Preamble detection and then for a valid SyncAddress interrupt. If
events occur, the sequencer is switched off and the circuit stays in Receive mode until the user switches modes.
Otherwise, the receiver is switched off until the next Rx period.
5.3.2.1. Timing Diagram
Most of the sequencer running time is spent while no wanted signal is received. As shown by the timing diagram in
Figure 48, the circuit wakes periodically for a short time, defined by RxTimeout. The circuit is in a Low Power mode for the
rest of Timer1 + Timer2 (i.e. Timer1 + Timer2 - TrxTimeout)
No wanted signal
Idle
Receive
Idle ( Sleep + RC )
Receive
Timer2
Idle
Timer2
Timer1
Timer1
RxTimeout
Timer1
RxTimeout
Figure 48. Listen Mode with no SyncAddress Detected
If a preamble is detected before RxTimeout timer ends, the circuit stays in Receive mode and waits for a valid
SyncAddress detection. If none is detected by the end of Timer2, Receive mode is deactivated and the polling cycle
resumes, without any user intervention.
Unwanted Signal
Preamble ( Preamble + Sync = T2 )
Idle
Wrong
Word
Receive
Payload
Idle
Receive
Timer2
Timer1
Crc
Idle
Timer2
RxTimeout
Timer1
Timer1
RxTimeout
Preamble
Detect
Figure 49. Listen Mode with Preamble Received and no SyncAddress
But if a valid Sync Word is detected, a SyncAddress interrupt is fired, the Sequencer is switched off and the circuit stays in
Receive mode as long as the user doesn't switch modes.
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Wanted Signal
Preamble ( Preamble + Sync = T2 )
Idle
Sync
Word
Payload
Crc
Receive
Timer2
Timer1
RxTimeout
Preamble
Detect
Sync
Address
Fifo
Level
Figure 50. Listen Mode with Preamble Received & Valid SyncAddress
5.3.2.2. Sequencer Configuration
The following graph shows Listen mode - Wake on SyncAddress state machine:
State Machine
Sequencer Off
&
Initial mode = Sleep or Standby
IdleMode = 1 : Sleep
Start bit set
Start
FromStart = 00
LowPower
Selection
LowPowerSelection = 1
Idle
On T1
FromIdle = 1
FromRxTimeout = 10
RxTimeout
On T2
Receive
On SyncAdress
FromReceive = 101
Sequencer Off
On RxTimeout
Figure 51. Wake On SyncAddress State Machine
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This example configuration is achieved as follows:
Table 48 Listen Mode with SyncAddress Condition Settings
Variable
IdleMode
FromStart
LowPowerSelection
FromIdle
FromReceive
FromRxTimeout
Effect
1: Sleep mode
00: To LowPowerSelection
1: To Idle state
1: To Receive state on T1 interrupt
101: To Sequencer off on SyncAddress interrupt
10: To LowPowerSelection
TTimeoutRxPreamble should be set to just long enough to catch a preamble (depends on PreambleDetectSize and BitRate).
TTimer1 should be set to 64 µs (shortest possible duration).
TTimer2 is set so that TTimer1 + TTimer2 defines the time between two start of reception.
In order to insure packet detection and optimize the receiver power consumption, the received packet Preamble should be
defined so that TPreamble = TTimer2 - TSyncAddress with TSyncAddress = (SyncSize + 1)*8/BitRate.
An example of DIO configuration for this mode is described in the following table:
Table 49 Listen Mode with PreambleDetect Condition Recommended DIO Mapping
DIO
0
1
2
3
4
Value
01
00
11
00
11
Rev. 7 - May 2020
©2020 Semtech Corporation
Description
CrcOk
FifoLevel
SyncAddress
FifoEmpty
PreambleDetect – Note: MapPreambleDetect bit should be set.
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5.4. Top Sequencer: Beacon Mode
In this mode, a repetitive message is transmitted periodically. If the Payload being sent is always identical, and
PayloadLength is smaller than the FIFO size, the use of the BeaconOn bit in RegPacketConfig2 together with the
Sequencer permit to achieve periodic beacon without any user intervention.
5.4.1. Timing diagram
In this mode, the Radio is switched to Transmit mode every TTimer1 + TTimer2 and back to Idle mode after PacketSent, as
shown in the diagram below. The Sequencer insures minimal time is spent in Transmit mode, and therefore power
consumption is optimized.
Beacon mode
Idle
Transmit
Idle ( Sleep + RC )
Transmit
Timer2
Idle
Timer2
Timer1
Timer1
Timer1
Packet
Sent
Packet
Sent
Figure 52. Beacon Mode Timing Diagram
5.4.2. Sequencer Configuration
The Beacon mode state machine is presented in the following graph. It is noticeable that the sequencer enters an infinite
loop and can only be stopped by setting SequencerStop bit in RegSeqConfig1.
State Machine
Sequencer Off
&
Initial mode = Sleep or Standby
IdleMode = 1 : Sleep
Start bit set
Start
FromStart = 00
LowPower
Selection
LowPowerSelection = 1
Idle
On T1
FromIdle = 0
On PacketSent
FromTransmit = 0
Transmit
Figure 53. Beacon Mode State Machine
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This example is achieved by programming the Sequencer as follows:
Table 50 Beacon Mode Settings
Variable
IdleMode
FromStart
LowPowerSelection
FromIdle
FromTransmit
Effect
1: Sleep mode
00: To LowPowerSelection
1: To Idle state
0: To Transmit state on T1 interrupt
0: To LowPowerSelection on PacketSent interrupt
TTimer1 + TTimer2 define the time between the start of two transmissions.
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5.5. Example CRC Calculation
The following routine(s) may be implemented to mimic the CRC calculation of the SX1276/77/78/79:
Figure 54. Example CRC Code
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5.6. Example Temperature Reading
The following routine(s) may be implemented to read the temperature and calibrate the sensor:
Figure 55. Example Temperature Reading
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Figure 56. Example Temperature Reading (continued)
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6. Packaging Information
6.1. Package Outline Drawing
The SX1276/77/78/79 is available in a 28-lead QFN package as shown in Figure 57.
Figure 57. Package Outline Drawing
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6.2. Recommended Land Pattern
Figure 58. Recommended Land Pattern
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6.3. Tape & Reel Information
Figure 59. Tape and Reel Information
6.4. Wafer Delivery
Please get in touch with a Semtech representative for wafer delivery option.
Semtech will deliver probed wafers with a die picking map.
The specifications given in Section 2.5. "Chip Specification" on page 14 are determined from the reference design with
QFN 28 package (see the reference design available on the Semtech website). In order to fulfill these specifications, the
die assembly must be done with similar wire constraints as in the QFN 28 package, see Addendum2 in the SX1276WS
devivery specification.
A complete wafer delivery specification is available on request.
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7. Revision History
Table 51 Revision History
Revision
1
2
Date
Sept 2013
Nov 2014
3
Nov 2014
4
March 2015
5
August 2016
6
January 2019
7
May 2020
Rev. 7 - May 2020
©2020 Semtech Corporation
Comment
First FINAL release
Miscellaneous typographical corrections
Correction of RxPayloadCrcOn description
Improve description in the RSSI and IQ calibration mechanism
Correction of ToA formulae
Inclusion of FEI and automatic frequency correction for LoRa
Corrected Rssi Formula in Lora mode
Addition of part SX1279
Clarified operation modes for Rx Single and Rx Continuous mode in LoRa
Added use cases for Rx Single and Rx Continuous mode in LoRa mode
Clarified used of LoRa RxPayloadCrcOn in Register Table
Added description of register RegSyncWord in LoRa register table
Changed Stand-By typo into Standby
Addition of part SX1276WS
Amendment of chapter on Frequency Error Indication
Addition of chapter on LoRa AFC Correction of LoRa registered trademark
Clarified RegLowPower
Added LoRa RegIfFreq1 & RegIfFreq2
Added LoRa RegHighBwOptimize1 & RegHighBwOptimize2
Added RegInvertIQ2 and clarified RegInvertIQ in LoRa mode
Added FifoFillCondition
Make reference to the “Wafer Delivery Specification”, governing document for the SX1276WS
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WIRELESS & SENSING PRODUCTS
DATASHEET
Important Notice
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© Semtech 2020
Contact information
Semtech Corporation
Wireless & Sensing Product Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
E-mail: sales@semtech.com
Internet: http://www.semtech.com
Rev. 7 - May 2020
©2020 Semtech Corporation
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