SX1302C915GW1

SX1302 LoRa Gateway Baseband Transceiver ^W/ ,ŽƐƚ ZĂĚŝŽĐŽƌĞ Z&ŵĂƚĐŚŝŶŐ͕&ŝůƚĞƌŝŶŐ͕ĂůƵŶ ĂŶĚ͕ŽƵƚƉƵƚƉŽǁĞƌ͕ ŵŽĚĞ ^yϭϮϱϱ ^yϭϮϱϳ ^yϭϮϱϬ ^W/ ĚĞĐŝŵ ϯϮD,nj ^yϭϮϱϱ ^yϭϮϱϳ ^yϭϮϱϬ ϴ >ŽZĂĞƚĞĐƚ ϴŚĂŶŶĞůdžϴ^& >ŽZĂ,ŝŐŚ^ƉĞĞĚ ϱϬϬͬϮϱϬͬϭϮϱŬ,nj ĚĞĐŝŵ ;'Ϳ&^< Ϯ ĂŶĚ͕ŽƵƚƉƵƚƉŽǁĞƌ͕ ŵŽĚĞ 'W^ ϭϮϱŬ,nj >ŽZĂdžϭϲ WĂĐŬĞƚ ŚĂŶĚůĞƌ ;'Ϳ&^ŽZĂddž ^W/ Figure A: Block Diagram General Description Key Features The SX1302 is a new generation of baseband LoRa® chip for gateways. It excels in reducing current consumption, simplifies the thermal design of gateways, and reduces the Bill Of Materials costs, yet it is capable of handling a higher amount of traffic than preceding devices. • LoRaWAN, Class A/B/C, all regions • 125 kHz LoRa reception with: • • 8 x 8 channels LoRa® packet detectors • 8 x SF5-SF12 LoRa® demodulators • 8 x SF5-SF10 LoRa® demodulators 125 /250 / 500 kHz LoRa® demodulator • (G)FSK demodulator • Direct interface to Semtech transceivers • SX1255, SX1257 and SX1250 • Single 32 MHz clock The high-speed baseband digital engines are clocked from a single 32 MHz clock source, and the chip embeds the capability to support SF5 and SF6 unlike previous generations. To absorb the additional traffic that the radio will be able to detect, more modems are now collaborating. 8 of them have been added to specifically handle the high-speed SF5 and SF6 packets, whilst the 8 others are still taking care of the SF7-SF12 traffic. The architecture has been reworked to reduce power consumption very significantly; it makes it easier to embed the SX1302 in highly-integrated environments where power dissipation might be a challenge. The SX1302 is also serialized in production, with a globally unique 64-bit number. Ordering Information Part Number Delivery Order Quantity SX1302IMLTRT Tape and Reel 3000 QFN68 Package, operating range from -40 to +85°C Pb-free, Halogen free, RoHS/WEEE compliant product SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 1 of 31 Revision History Version ECO Date Rev 1.0 ECO-047283 June 2019 Rev 1.1 ECO-050134 January 2020 SX1302 Datasheet DS.SX1302.W.APP Modifications First Release Add specification for the sequencing of VCC_CORE and VCC_IO in Section 5. www.semtech.com Rev 1.1 Jan 2020 2 of 31 Table of Contents General Description.............................................................................................................................................1 Key Features...........................................................................................................................................................1 Ordering Information .........................................................................................................................................1 Revision History ....................................................................................................................................................2 List of Figures ........................................................................................................................................................5 List of Tables .........................................................................................................................................................6 1. Introduction.......................................................................................................................................................7 1.1 RF Front End Interface ......................................................................................................................7 1.2 Power Distribution .............................................................................................................................7 1.3 Clocking .................................................................................................................................................7 1.4 Detection Engine and Modems ....................................................................................................7 1.5 Digital Interface and Control ..........................................................................................................7 1.6 Application Programming Interface ............................................................................................7 1.7 Application Information ...................................................................................................................7 2. Pin Connections ...............................................................................................................................................8 2.1 Pinout .....................................................................................................................................................8 2.2 Package View .................................................................................................................................... 11 3. Specifications ................................................................................................................................................. 12 3.1 ESD Notice .......................................................................................................................................... 12 3.2 Absolute Minimum and Maximum Ratings ........................................................................... 13 3.3 Operating Range .............................................................................................................................. 13 3.4 Electrical Specifications ................................................................................................................. 13 3.5 Digital I/O Specifications ............................................................................................................... 14 3.6 Example Reference Design Performance ............................................................................... 14 4. RF Front End Interface................................................................................................................................. 16 5. Power Distribution ....................................................................................................................................... 18 6. Clocking ........................................................................................................................................................... 19 7. Detection Engine - Modems..................................................................................................................... 20 8. Digital Interface and Control .................................................................................................................... 21 8.1 Host SPI Interface ............................................................................................................................. 21 8.1.1 HOST SPI Timings ................................................................................................................ 21 8.1.2 SPI Timings............................................................................................................................. 22 9. Application Programming Interface...................................................................................................... 23 9.1 Globally Unique EUI ........................................................................................................................ 23 10. Application Information .......................................................................................................................... 24 10.1 Geographical Designs ................................................................................................................. 24 10.2 Reference Block Diagram ........................................................................................................... 24 10.3 Reference Design Layout ........................................................................................................... 25 11. Packaging Information............................................................................................................................. 26 11.1 Package Outline Drawing .......................................................................................................... 26 11.2 Package Marking ........................................................................................................................... 27 11.3 Land Pattern ................................................................................................................................... 27 11.4 Reflow Profiles ................................................................................................................................ 28 SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 3 of 31 11.5 Tape and Reel Specification ...................................................................................................... 28 11.6 Thermal Impedance ..................................................................................................................... 28 Glossary ................................................................................................................................................................ 29 SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 4 of 31 List of Figures Figure 2-1: Pin Locations, Top View........................................................................................................... Figure 4-1: Receive Interconnection ......................................................................................................... Figure 4-2: Transmit Interconnection ....................................................................................................... Figure 5-1: VCC_CORE and VCC_IO Sequencing .................................................................................. Figure 8-1: SPI Timing Diagram................................................................................................................... Figure 10-1: Application Design Block Diagram ................................................................................... Figure 10-2: Reference Design PCB Layout............................................................................................. Figure 11-1: QFN 7x7 Package Outline Drawing................................................................................... Figure 11-2: SX1302 Package Marking ..................................................................................................... Figure 11-3: QFN 7x7mm Land Pattern.................................................................................................... Figure 11-4: Tape and Reel Specification ................................................................................................ SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 11 16 16 18 21 24 25 26 27 27 28 5 of 31 List of Tables Table 2-1: Pinout.................................................................................................................................................. 8 Table 3-1: ESD and Latch-Up Notice.......................................................................................................... 12 Table 3-2: Minimum and Maximum Ratings .......................................................................................... 13 Table 3-3: Operating Range.......................................................................................................................... 13 Table 3-4: Performances ................................................................................................................................ 13 Table 3-5: Digital I/O Specifications........................................................................................................... 14 Table 3-6: Reference Design Performance.............................................................................................. 14 Table 4-1: Semtech RF Front-end Summary........................................................................................... 17 Table 5-1: Current Consumption ................................................................................................................ 18 Table 8-1: SPI Timing Requirements.......................................................................................................... 22 Table 11-1: Tape and Reel Specification .................................................................................................. 28 SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 6 of 31 1. Introduction The SX1302 is a digital baseband engine, capable of detecting and demodulating large amounts of LoRa® packets expected in the IOT networks. 1.1 RF Front End Interface The SX1302 is intended to be used with various RF Front End chips (RF to IQ), such as Semtech’s SX1255/57. Details on the interface and compatibility is available on Section 4. "RF Front End Interface" on page 16 . 1.2 Power Distribution The SX1302 is supplied on two different domains, 1.2 V for the core of the baseband processing, and 3 to 3.6V for the host and RF interface. For details, see Section 5. "Power Distribution" on page 18 . 1.3 Clocking SX1302 clocking is achieved from a single clock source. Details are found in Section 6. "Clocking" on page 19 . 1.4 Detection Engine and Modems The SX1302 can detect at any time, any packet in a combination of 8 different spreading factors (SF5 to SF12) and 10 channels, and demodulate up to 16 packets at any time. Details on the modems and their assignment are found in Section 7. "Detection Engine - Modems" on page 20 . 1.5 Digital Interface and Control The SPI interface of the SX1302 to its host controller is detailed in Section 8. "Digital Interface and Control" on page 21 . 1.6 Application Programming Interface An example API is made available as source code with the HAL library and the Packet Forwarder example software. Details are available in Section 9. "Application Programming Interface" on page 23 . 1.7 Application Information Semtech has designed, validated, and released multiple reference design with the SX1302. The performance tabulated in this document is obtained on the said reference design. Details of the Core Cell reference design are posted in Section 10. "Application Information" on page 24 . SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 7 of 31 2. Pin Connections 2.1 Pinout Table 2-1: Pinout Pin Number Pin Name Direction Description (0) GND Power Ground 1 HOST_CSN Input External HOST SPI CSN pin 2 HOST_MISO Output External HOST SPI MISO pin 3 HOST_MOSI Input External HOST SPI MOSI pin 4 HOST_SCK Input External HOST SPI SCK pin 5 VCC_CORE Power Core supply 6 GND Power Ground 7 RESET Input Asynchronous Reset Input 8 PPS Input PPS input from GPS 9 GND Power Ground 10 RADIO_CTRL[0] Output Radio A Enable LDO 11 RADIO_CTRL[1] Output Radio A Enable LNA and control switch 12 RADIO_CTRL[2] Output Radio A Enable PA and control switch 13 RADIO_CTRL[3] Output Radio A Reset 14 VCC_IO Power IO supply 15 GND Power Ground 16 RADIO_CTRL[4] Output Radio A PA gain_0 17 RADIO_CTRL[5] Output Radio A PA gain_1 18 RADIO_B_CSN Output 19 RADIO_B_MOSI 20 SX1250 SX1255/57 NRESET RESET Radio B SPI CSN pin NSS NSS Output Radio B SPI MOSI pin MOSI MOSI SP_VALID Input Stream synchronization for FPGA 21 RADIO_B_SCK Output Radio B SPI SCK pin SCK SCK 22 RADIO_CTRL[6] Output Radio B Enable LDO 23 VCC_CORE Power Core supply SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 8 of 31 Table 2-1: Pinout Pin Number Pin Name Direction Description 24 GND Power Ground 25 GND Power Ground 26 RADIO_CTRL[7] Output Radio B Enable LNA and control switch 27 RADIO_CTRL[8] Output Radio B Enable PA and control switch 28 RADIO_CTRL[9] Output Radio B Reset 29 RADIO_CTRL[10] Output Radio B PA gain_0 30 VCC_IO Power IO supply 31 RADIO_CTRL[11] Output Radio B PA gain_1 32 RADIO_B_IQ[3] 33 SX1250 SX1255/57 NRESET RESET I/O - NS DIO4 I_OUT RADIO_B_MISO Input MISO MISO 34 RADIO_B_CLK_I Input BUSY CLK_OUT 35 RADIO_B_IQ[0] I/O - NS DIO1 Q_OUT 36 RADIO_B_IQ[1] I/O - NS DIO2 I_IN 37 RADIO_B_IQ[4] I/O - NS DIO5 Q_IN 38 RADIO_B_IQ[2] I/O - NS DIO3 CLK_IN 39 GND Power Ground 40 VCC_CORE Power Core supply 41 RADIO_A_IQ[3] I/O - NS DIO4 I_OUT 42 RADIO_A_MISO Input MISO MISO 43 RADIO_A_CLK_I Input BUSY CLK_OUT 44 RADIO_A_IQ[0] I/O - NS DIO1 Q_OUT 45 RADIO_A_IQ[1] I/O - NS DIO2 I_IN 46 GND Power Ground 47 VCC_IO Power IO supply 48 RADIO_A_IQ[4] I/O - NS DIO5 Q_IN 49 RADIO_A_IQ[2] I/O - NS DIO3 CLK_IN 50 GPIO[11] In/out General purpose IO 51 GPIO[10] In/out General purpose IO SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 9 of 31 Table 2-1: Pinout Pin Number Pin Name Direction Description 52 GPIO[9] In/out General purpose IO 53 GPIO[8] In/out General purpose IO 54 GPIO[7] In/out General purpose IO 55 GND Power Ground 56 VCC_CORE Power Core supply 57 GPIO[6] In/out General purpose IO 58 GPIO[5] In/out General purpose IO 59 GPIO[4] In/out General purpose IO 60 GPIO[3] In/out General purpose IO 61 VCC_IO Power IO supply 62 GND Power Ground 63 GPIO[2] In/out General purpose IO 64 GPIO[1] In/out General purpose IO 65 RADIO_A_SCK Output Radio A SPI SCK pin 66 GPIO[0] Input General purpose IO 67 RADIO_A_MOSI Output 68 RADIO_A_CSN (0) GND SX1302 Datasheet DS.SX1302.W.APP SX1255/57 SCK SCK Radio A SPI MOSI pin MOSI MOSI Output Radio A SPI CSN pin NSS NSS Power Ground www.semtech.com Rev 1.1 Jan 2020 SX1250 10 of 31 2.2 Package View ϯϱ ϭ ϱϮ ϭϴ Figure 2-1: Pin Locations, Top View SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 11 of 31 3. Specifications All measured performances and conditions are listed in this chapter. Quantitative indications left in other chapters are for the ease of reading and are indicative only. The following specifications are given for the typical operating conditions of VCC_IO = VBAT = 3.3 V, temperature = 25 °C (85°C for maximum values), reference oscillator frequency = 32 MHz, RF centre frequency = 868 MHz. All RF impedances are matched using the reference design, see Section 10.2 "Reference Block Diagram" on page 24. Blocking, ACR and co-channel rejection are given for a single tone interferer and referenced to sensitivity level +6 dB. 3.1 ESD Notice The SX1302 has built-in ESD and latch-up protection. It should however be handled with all the necessary ESD precautions to avoid any permanent damage. Table 3-1: ESD and Latch-Up Notice Symbol Description Min Typ Max Unit ESD_HBM Class 2 of ANSI/ESDA/JEDEC Standard JS-001-2014 (Human Body Model) - - 2 kV ESD_CDM ESD Charged Device Model, JEDEC standard JESD22-C101, class C4 - - 500 V LU Latch-up, JEDEC standard JESD78 B, class I level A - - 100 mA SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 12 of 31 3.2 Absolute Minimum and Maximum Ratings Table 3-2: Minimum and Maximum Ratings Symbol Description Min Max Unit VCCIO,ABSMAX IO power supply to VSS -0.5 4.0 V VCCcore,ABSMAX Core power supply to VSS -0.5 1.5 V TSTORE Storage temperature -40 +125 °C TREFLOW Peak reflow temperature 260 °C MSL Humidity rating MSL1 3.3 Operating Range Table 3-3: Operating Range Symbol Description Minimum Typical Maximum Unit VCCIO,OP IO supply operating conditions 3.0 3.3 3.6 V VCCCORE,OP Core supply operating conditions 1.1 1.2 1.3 V TA,OP Operating temperature -40 25 +85 °C 3.4 Electrical Specifications Table 3-4, “Performances,” on page 13 summarizes the electrical performance of the SX1302, over operating conditions. The reference design described in Section 10. "Application Information" on page 24 is used to measure this performance. Table 3-4: Performances Symbol Description Min Typ Max IDD_8CH_CO RE Average consumption when all correlators are active - 15 - mA - 1 - mA - 17 77 mA IDD_8CH_PE Peak1 consumption when all correlators are active, and 16 modems are active, AK_CORE on VCC_CORE - 28 85 mA IDD_8CH_AV G_IO - 1 - mA IDD_8CH_IO IDD_8CH_AV G_CORE SX1302 Datasheet DS.SX1302.W.APP (no packet detected, no modem activated), on VCC_CORE Average consumption when all correlators are active (no packet detected, no modem activated), on VCC_IO Average consumption when all correlators are active, and 16 modems are active, on VCC_CORE Average consumption when all correlators are active, and 16 modems are active, on VCC_IO www.semtech.com Rev 1.1 Jan 2020 Unit 13 of 31 Table 3-4: Performances Symbol Description Min Typ Max IDD_TX_COR E Sending data on SX1250 using SF6, average, on VCC_CORE - 7.2 - mA IDD_TX_IO Sending data on SX1250 using SF6, average, on VCC_IO - 1.4 - mA IDD_OFF_CO RE OFF current, clock is disabled, on VCC_CORE - 3.2 - mA IDD_OFF_IO On VCC_IO - 10 - uA FERR Frequency Offset Tolerance, less than 3dB degradation2 - - Unit +/-0.25* Hz BW 1. Average and Peak current concepts are explained in Section 5. on page 18 2. Capability to receive a LoRa® signal with frequency offset on the carrier, assuming a precision of up to +/-0.5ppm on the reference frequency of the SX1302-based design. For instance, for LoRa® Bandwidth of 125 kHz, incoming packets can be offset by up to +/-31 kHz. 3.5 Digital I/O Specifications Table 3-5: Digital I/O Specifications Symbol Description Conditions Min Typ Max Unit VIH Input High Voltage - 0.7*VCC_IO - VCC_IO + 0.3 V VIL Input Low Voltage -0.3 - 0.3*VCC_IO V VOH Output High Voltage Imax = -8 mA VCC_IO - 0.6 - VCC_IO V VOL Output Low Voltage Imax = 8mA 0 - 0.4 V All inputs are floating and should be driven to a proper potential to avoid current leakage in low-power modes. GPIO[i] pins have a selectable internal 100 kOhms pull-down resistor, when configured as inputs, and they are disabled at Reset. 3.6 Example Reference Design Performance Disclaimer: the performance specifications listed below are only indicative, and obtained on the reference design described in Section 10.2 "Reference Block Diagram" on page 24. Sensitivity is specified with a PER=10%, receiving 12 Byte packets, all under nominal temperature and voltage conditions. It is measured with a SX1250 front-end, an LNA with 18dB of gain and 1.5 dB of Noise Figure. Table 3-6: Reference Design Performance Symbol Description Min Typ Max Unit S_SF5_125 SF5 Sensitivity, LoRa 125 kHz bandwidth - -121 - dBm S_SF6_125 SF6 Sensitivity, LoRa 125 kHz bandwidth - -123.5 - dBm S_SF7_125 SF7 Sensitivity, LoRa 125 kHz bandwidth - -127 - dBm S_SF8_125 SF8 Sensitivity, LoRa 125 kHz bandwidth - -129 - dBm SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 14 of 31 Table 3-6: Reference Design Performance Symbol Description Min Typ Max Unit S_SF9_125 SF9 Sensitivity, LoRa 125 kHz bandwidth - -132.5 - dBm S_SF10_125 SF10 Sensitivity, LoRa 125 kHz bandwidth - -135.5 - dBm S_SF11_125 SF11 Sensitivity, LoRa 125 kHz bandwidth - -138 - dBm S_SF12_125 SF12 Sensitivity, LoRa 125 kHz bandwidth - -141 - dBm S_FSK_50 50 kbps, GFSK modulation - -111 - dBm S_SF9_250 SF9 Sensitivity, LoRa 250 kHz bandwidth - -126.5 - dBm A complete performance report of the reference design published in Section 10.2 "Reference Block Diagram" on page 24 is posted on www.semtech.com. SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 15 of 31 4. RF Front End Interface The SX1302 can accommodate any of the following RF front-end devices: SX1250, SX1255 and SX1257, all of which are Semtech products. For any other device, hardware logic could be used on the interface for translation purposes. The roles of these devices is to down-convert the RF signal to baseband (direct conversion or low-IF), and digitize it to feed the IQ samples to the SX1302 baseband chip. The interconnection to the front-end device is organized as follows. Here, the SX1250 is taken as an example: 5HFHLYH,QWHUFRQQHFWLRQ ^yϭϮϱϬ;ĞdžĂŵƉůĞͿ %86< ',2 ',2 ',2 ',2 ',2 0,62 026, 6&. 166 ^yϭϯϬϮ System clock 32 MHz I(t) 2 Q(t) 2 Gain Control Interface 4 Chip Select 5$',2B[B&./B, 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B0,62 5$',2B[B026, 5$',2B[B6&. 5$',2B[B&61 Figure 4-1: Receive Interconnection 7UDQVPLW,QWHUFRQQHFWLRQ ^yϭϮϱϬ;ĞdžĂŵƉůĞͿ %86< ',2 ',2 ',2 ',2 ',2 0,62 026, 6&. 166 ^yϭϯϬϮ System clock 32 MHz Modulator input 5 Sigma-delta clock sync Chip Select 5$',2B[B&./B, 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B,4>@ 5$',2B[B0,62 5$',2B[B026, 5$',2B[B6&. 5$',2B[B&61 Figure 4-2: Transmit Interconnection SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 16 of 31 The table hereafter summarizes the characteristics of the three front-end devices currently supported with the SX1302: Table 4-1: Semtech RF Front-end Summary Part # Frequency Band Receive BW Output Power Rx NF Comment SX1255 400 - 510 MHz 1 MHz About 0 dBm 5 dB 5x5 mm package, 20 mA Rx SX1257 862 - 1020 MHz 1 MHz About 0 dBm 5 dB 5x5 mm package, 20 mA Rx SX1250 150 - 960 MHz 1 MHz +22 dBm 10 dB 4x4 mm package, 5 mA Rx SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 17 of 31 5. Power Distribution The SX1302 needs two powers rails: VCC_IO and VCC_CORE. VCC_IO sets the voltage level for all of the digital interfaces of the chip (SPI, GPIO and IQ interface), whilst VCC_CORE supplies current to the baseband engine. VCC_CORE can be derived from a higher voltage source with a high-efficiency DC-DC buck converter, as it is only 1.2 V. An optimized power management strategy is proposed in Semtech’s reference designs, and one example of displayed in Section 10.2 "Reference Block Diagram" on page 24 . The following currents can be measured, and should be used to design the power supply in the system: Table 5-1: Current Consumption Conditions VCC_CORE Temperature @ 1.2 V Average current 25°C 17 mA Peak current 25°C 28 mA Average current 60°C 48 mA Peak current 60°C 55 mA Average current 85°C 77 mA Peak current 85°C 85 mA During a reception phase, the current observed won’t be always the same, but will spike up during certain phases of the reception. Therefore, the average current should be used to compute the total energy consumption of the SX1302 based gateway, however the peak current will be the relevant metric to size the power supply components. To ensure proper control of all digital IOs during the power-up and power-down sequences of the SX1302, VCC_CORE shall be enabled before VCC_IO at start-up, and disabled after VCC_IO at shut-down. Start-up Shut-down VCC_CORE VCC_CORE VCC_IO VCC_IO Δt1 Δt2 Figure 5-1: VCC_CORE and VCC_IO Sequencing Δt1 and Δt2 must be equal to or greater than 0. SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 18 of 31 6. Clocking The SX1302 uses the 32 MHz clock source from its companion RF Front-end (for example, Semtech’s SX1250) to clock the entire system. This clock is injected on pin 43 (RADIO_A_CLK_I). It is advised to use a GPS-precision TCXO (0.5 ppm), in order to have a maximum “capture range” for the receiver, allowing lower precision reference clock, which are cheaper, on the end-devices. SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 19 of 31 7. Detection Engine - Modems The SX1302 embeds 16 different modems, of two sorts: • 8 multi-SF LoRa® modems, capable of demodulating any LoRa® packet from SF5 to SF12 • 8 multi-SF LoRa® modems, specifically demodulating SF5 to SF10 traffic • 1 high-speed multi-BW LoRa® modem (125, 250 or 500 kHz), handling a single declared SF A holistic detection engine can capture any LoRa® traffic in the pre-defined frequency plan, and assign the detected packets to the pool of available modems for demodulation. SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 20 of 31 8. Digital Interface and Control The transceiver is controlled via a serial interface (SPI) and a set of general purpose input/output (DIOs). 8.1 Host SPI Interface The SPI interface gives access to the configuration register via a synchronous full-duplex frame corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. An address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The CSN pin goes low at the beginning of the frame and goes high after the data byte. MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer is always started by the CSN pin going low. MISO is high impedance when CSN is high. The host terminates an SPI transaction by raising the CSN signal, it does not explicitly send the command length as a parameter. The host must not raise CSN within the bytes of a transaction. 8.1.1 HOST SPI Timings tCSH CSN tDELAY tSCK tSCKH tSCKL tQUIET SCK tSETUP tHOLD MOSI tDOEN tDOV tDODIS MISO Figure 8-1: SPI Timing Diagram SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 21 of 31 8.1.2 SPI Timings All timings are given in next table for Max load cap of 10 pF. Table 8-1: SPI Timing Requirements Symbol Description Minimum Typical Maximum Unit Timing constraints in SPI inputs tSPI,SCK SCK period 100 ns tSPI,SCKH SCK high duration 40 ns tSPI,SCKL SCK low duration 40 ns tSPI,SCKR SCK rise time (10% VCC_IO ->90% VCC_IO) 0 2.5 ns tSPI,SCKF SCK fall time (90% VCC_IO ->10% VCC_IO) 0 2.5 ns tSPI,DELAY SCK lead time 40 ns tSPI,QUIET SCK trail time 40 ns tSPI,CSH Time between two successive CSN chip select 250 ns tSPI,CSR CSN rise time (10% VCC_IO ->90% VCC_IO) 0 2.5 ns tSPI,CSF CSN fall time (90% VCC_IO ->10% VCC_IO) 0 2.5 ns tSPI,SETUP Data in setup time 5 ns tSPI,HOLD Data in hold time 5 ns SPI output timing specification tSPI,DOEN SPI output enable time 0 10 ns tSPI,DODIS SPI output disable time 0 10 ns tSPI,DOV SCK out falling edge to MISO delay 15 ns SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 22 of 31 9. Application Programming Interface Through SPI interface, the SX1302 is fully controlled by its host, whether it is a MCU (smal-size cell) or a Linux MPU for higher-end gateways. Semtech fully abstracts the complexity of the SX1302 and its companions chips by delivering two libraries as open-source code: • SX1302 HAL (Hardware Abstraction layer), incorporating all of the required code to initialize, calibrate, run and exchange radio packets with the gateway board • SX1302 Packet Forwarder, which is a simple example application of how a gateway can be connected to a host. The host, in a LoRaWAN network, is typically cloud-based, but can also be co-located with the gateway in case of small-scale networks All of these open-sourced libraries are available from Github on https://github.com/Lora-net/lora_gateway. 9.1 Globally Unique EUI The SX1302 chip is serialized in production, with a globally unique 64-bit number. It may be used by the application for identification and security purposes. This 64-bit EUI can be retrieved with the function lgw_get_eui() available in the HAL library. SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 23 of 31 10. Application Information The Core cell reference design represents a compact reference implementation of the SX1302, along with its power management, clocks, Front End Module, RF matching and filtering. 10.1 Geographical Designs The suitability of the SX1302-based reference designs to national radio frequency regulations depends on the RF front-end device being used. With the SX1250/55/57 front-ends provided by Semtech, the expectation is: • Up to +27 dBm supported in the USA, Canada or other FCC-type countries • Up the +27 dBm in Europe and other ITU 1 regions • Up to +21 dBm in Japan where the phase noise requirement is more stringent 10.2 Reference Block Diagram The application block diagram is shown below: Reset SPI SX1250 Clk_32_MHz I/Q PA / LNA Enable, LNA active, PA active, PA gain TCXO Reset SX1302 HOST SPI Enable, LNA active, PA active, PA gain PPS PA / LNA Reset SPI SX1250 Clk_32_MHz I/Q Optional GPS Figure 10-1: Application Design Block Diagram SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 24 of 31 10.3 Reference Design Layout Figure 10-2: Reference Design PCB Layout SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 25 of 31 11. Packaging Information 11.1 Package Outline Drawing The transceiver is delivered in a 7x7mm QFN package with 0.35mm pitch: Figure 11-1: QFN 7x7 Package Outline Drawing SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 26 of 31 11.2 Package Marking Figure 11-2: SX1302 Package Marking 11.3 Land Pattern The recommended land pattern is as follows: Figure 11-3: QFN 7x7mm Land Pattern SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 27 of 31 11.4 Reflow Profiles Reflow process instructions are available from the Semtech website, at the following address: http://www.semtech.com/quality/ir_reflow_profiles.html The transceiver uses a QFN68 7x7mm package, also named MLP package. 11.5 Tape and Reel Specification Pin #1  Figure 11-4: Tape and Reel Specification Table 11-1: Tape and Reel Specification Carrier Tape (mm) Package Size Tape Width1 (W) Pocket2 Pitch (P) AO3 16 12 7.3 7x7 Reel BO KO4 Reel Size [in] Reel Width [mm] Min. Trailer Length [mm] Min. Leader Length [mm] QTY per Reel 7.3 1.1 13 16.4 400 400 3000 1. Tolerance for tape width is +/- 0.3 mm 2. Single Sprocket holes, pocket pitch range +/-0.1 mm 3. Range from nominal values for Ao and Bo is +/-0.2 mm 4. Range is +/-0.1 mm 11.6 Thermal Impedance The thermal impedance of this package is: • 28.3 °C/W when used in still air (natural convection) • 21.6 °C/W when used with an air speed of 1 m/s • 19.5 °C/W when used with an air speed of 2.5 m/s This measurement is made with a 1.6 mm 4-layer PCB of 87 cm2, metallized over 55 cm2, with 16 vias of 0.3 mm diameter. SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 28 of 31 Glossary List of Acronyms and their Meaning Acronym Meaning ACR Adjacent Channel Rejection ADC Analog-to-Digital Converter AFC Automatic Frequency Correction AGC Automatic Gain Control API Application Programming Interface β Modulation Index BR Bit Rate BT Bandwidth-Time bit period product BW BandWidth CAD Channel Activity Detection CMD Command Transaction CPOL Clock Polarity CPHA Clock Phase CR Coding Rate CRC Cyclical Redundancy Check CSN Chip Select active low CW Continuous Wave DC-DC Direct Current to Direct Current converter DIO Digital Input / Output DSB Double Side Band FEC Forward Error Correction FLRC Fast Long Range Communication FSK Frequency Shift Keying GFSK Gaussian Frequency Shift Keying GMSK Gaussian Minimum Shift Keying IF Intermediate Frequencies IRQ Interrupt Request LDO Low-Dropout LNA Low-Noise Amplifier SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 29 of 31 List of Acronyms and their Meaning Acronym Meaning LO Local Oscillator Long Range Communication LoRa® the LoRa® Mark is a registered trademark of the Semtech Corporation LSB Least Significant Bit MD More Data MIC Message Integrity Check MISO Master Input Slave Output MOSI Master Output Slave Input MSB Most Significant Bit MSK Minimum-Shift Keying NESN Next Expected Sequence Number NOP No Operation NRZ Non-Return-to-Zero OOK On-Off Keying PA Power Amplifier PDU Protocol Data Unit PER Packet Error Rate PID Product Identification PLL Phase-Locked Loop PRNG Pseudo-Random Number Generation RFU Reserved for Future Use RTC Real-Time Clock RTSN Request to Send SCK Serial Clock SF Spreading Factor SN Sequence Number SNR Signal to Noise Ratio SPI Serial Peripheral Interface STDBY Standby TCXO Temperature Compensated Crystal Oscillator UART Universal Asynchronous Receiver/Transmitter XOSC Crystal Oscillator SX1302 Datasheet DS.SX1302.W.APP www.semtech.com Rev 1.1 Jan 2020 30 of 31 Important Notice Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. 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All rights reserved. © Semtech 2020 Contact Information Semtech Corporation Wireless & Sensing Products 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com SX1302 Datasheet DS.SX1302.W.APP 31 of 31 Rev 1.1 Jan 2020 31