XE8807AMI026TLF

XE8806A/XE8807A XE8806A Radio Machine XE8806A and XE8807A Ultra Low-Power Low-Voltage Radio Machines General Description The XE8806A and XE8807A are ultra low-power lowvoltage microcontroller based Radio Machines. They include the revolutionary BitJockey™, UART type of peripheral specialized for radio communication. The XE8806A and XE8807A are available with on chip ROM or Multiple-Time-Programmable (MTP) program memory. Key product Features • • • • • • Ultra low-power MCU, up to 7 MIPS 300 uA at 1 MIPS operation 6 uA at 32 kHz operation 1 uA time keeping Low-voltage operation (1.2 - 5.5 V supply voltage) 22 kB (8 kW) ROM/MTP (XE8806A) 11 kB (4kW) MTP (XE8807A) • • • • • • Applications • RF companion chip • RF system supervisor • Portable, battery operated instruments • Metering • Remote control • HVAC control Ordering Information Product XE8806AMI000 XE8806AMI026LF XE8806ARI000 XE8806ARI026LF XE8807AMI000 XE8807AMI026LF Temperature range -40°C to 85 °C -40°C to 85 °C -40°C to 125°C -40°C to 125°C -40°C to 85 °C -40°C to 85 °C Memory type MTP MTP ROM ROM MTP MTP Package die TQFP32 die TQFP32 die TQFP32 520 B RAM 4 counters PWM, UART, BitJockey™ Analog matrix switching 4 low-power analog comparators independant RC and crystal oscillators • 5 reset, 15 interrupt, 8 event sources • 100 years MTP Flash retention at 55°C Rev 1 January 2006 www.semtech.com XE8806A/XE8807A TABLE OF CONTENTS Chapter Title 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. General overview XE8806A and XE8807A performance CPU Memory mapping Low power modes Reset generator Clock generation Interrupt handler Event handler Low power RAM Port A Port B Port D Radio Asynchronous Receiver/Transmitter (BitJockey™) Universal Asynchronous Receiver/Transmitter (UART) Universal Synchronous Receiver/Transmitter (USRT) Counters/PWM The Voltage Level Detector Low power comparators Dimensions © Semtech 2006 www.semtech.com XE8806A/XE8807A 1. General overview 1.1 Top schematic 1-2 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 Pin map TQFP-32 SO-28 SO-24 Bare die XE8806A Bare die XE8807A 1-4 1-4 1-4 1-5 1-6 1-7 1.3 Pin assignment 1-7 © Semtech 2006 www.semtech.com 1-1 XE8806A/XE8807A 1.1 Top schematic The top level block schematic of the circuit is shown in Figure 1-1. The heart of the circuit consists of the Coolrisc816 CPU (central processing unit) core. This core includes an 8x8 multiplier and 16 internal registers. The bus controller generates all control signals for access to all data registers other than the CPU internal registers. The reset block generates the adequate reset signals for the rest of the circuit as a function of the set-up contained in its control registers. Possible reset sources are the power-on-reset (POR), the external pin NRESET, the watchdog (WD), a bus error detected by the bus controller or a programmable pattern on Port A. The clock generation and power management block sets up the clock signals and generates internal supplies for different blocks. The clock can be generated from the RC oscillator (this is the start-up condition), the crystal oscillator (XTAL) or an external clock source (given on the XIN pin). The test controller generates all set-up signals for different test modes. In normal operation, it is used as a set of 8 low power RAM. If power consumption is important for the application, the variables that need to be accessed frequently should be stored in these registers rather than in the RAM. The IRQ handler routes the interrupt signals of the different peripherals to the IRQ inputs of the CPU core. It allows masking of the interrupt sources and it flags which interrupt source is active. Events are generally used to restart the processor after a HALT period without jumping to a specified address, i.e. the program execution resumes with the instruction following the HALT instruction. The EVN handler routes the event signals of the different peripherals to the EVN inputs of the CPU core. It allows masking of the event sources and it flags which event source is active. The Port B is an 8 bit parallel IO port with analog capabilities. The USRT, UART, PWM and CMPD blocks also make use of this port. The instruction memory is a 22-bit wide flash or ROM memory depending on the circuit version. In case of the ROM version, the VPP pin is not used. The maximal number of instructions in the XE8806A is 8192. The maximal number of instructions in the XE8807A is 4096. The data memory on this product is a 512 byte SRAM. The port A is an 8 bit parallel input port. It can also generate interrupts, events or a reset. It can be used to input external clocks for the timer/counter/PWM block. The Port D is a general purpose 8 bit parallel IO port. The USRT (universal synchronous receiver/transmitter) contains some simple hardware functions in order to simplify the software implementation of a synchronous serial link. The UART (universal asynchronous receiver/transmitter) contains a full hardware implementation of the asynchronous serial link. The RFIF interface is a serial interface dedicated to communication with RF circuits. From the CPU side, it very much looks like an ordinary UART but it also implements low level coding/decoding and frame synchronisation. The input/output pins are multiplexed on port D. The counters/timers/PWM can take its clocks from internal or external sources (on Port A) and can generate interrupts or events. The PWM is output on Port B. The VLD (voltage level detector) detects the battery end of life with respect to a programmable threshold. The CMPD contains a 4 channel comparator. It is intended to monitor analog or digital signals whilst having a very low power consumption. © Semtech 2006 www.semtech.com 1-2 XE8806A/XE8807A DATA MEMORY INSTRUCTION MEMORY VPP CPU COOLRISC816 VBAT VSS 8 X8 MULTIPLIER B U S C O N T R O L L E R address control PORT A PA(7:0) datain dataout PORT D PD(7:0) 16 CPU REGISTERS RESET BLOCK POR CLOCK GENERATION/ POW ER MANAGEMENT RC XTAL VREG USRT clocks UART test control TEST CONTROLLER TEST 8 DATA REGISTERS IRQ HANDLING EVN HANDLING COUNTERS TIMERS PW M irq evn PB(1:0) PA(3:0) XIN XOUT VREG reset control PB(7:6) WD PB(5:4) NRESET VLD PB(7:0) CMPD PB(7:4) PORT B PD(3:0) RFIF BitJockey Figure 1-1. Block schematic of the XE8806A and XE8807A circuits. © Semtech 2006 www.semtech.com 1-3 XE8806A/XE8807A 1.2 Pin map The XE8806A and XE8807A can be delivered in different packages. The pin maps for the different packages are given below. VPP NRESET 9 PD(1) PA(1) PA(2) PD(2) PB(0) PB(1) 1.2.1 TQFP-32 PB(2) PD(0) 17 PB(3) PA(0) PD(3) VBAT PA(3) XOUT PA(4) XIN PD(4) VSS PB(4) PA(7) PD(7) VREG TEST PD(6) PA(6) PA(5) PD(5) 25 1 PB(7) PB(6) PB(5) Figure 1-2. TQFP-32 pin map 1.2.2 SO-28 PD(2)/PA(2) 15 14 PA(1)/PD(1) PB(0) NRESET PB(1) VPP PB(2) PD(0) PB(3) PA(0) PD(3) VBAT PA(3) XOUT PA(4) XIN PD(4) VSS PB(4) PA(7) PB(5) PD(7) PB(6) VREG PB(7) PD(5)/PA(5) TEST 28 1 PA(6)/PD(6) Figure 1-3. SO28 pin map In the SO-28 package, 4 pins of Port A and Port D are connected together. It is up to the user to choose between the functionality of Port A or Port D for these pins. Note: if one of the pins PD(1), PD(2), PD(5), PD(6) is used as output, the pull up of the corresponding pin of Port A should be disabled in order to have low power consumption. © Semtech 2006 www.semtech.com 1-4 XE8806A/XE8807A 1.2.3 SO-24 PD(2)/PA(2) 13 12 PA(1)/PD(1) PB(0) NRESET PB(1) VPP PB(2) PA(0)/PD(0) PB(3) VBAT PD(3)/PA(3) XOUT PD(4)/PA(4) XIN PB(4) VSS PB(5) PA(7)/PD(7) PB(6) VREG TEST PB(7) PD(5)/PA(5) 24 1 PA(6)/PD(6) Figure 1-4. SO24 pin map In the SO-24 package, all pins of Port A and Port D are connected together. It is up to the user to choose between the functionality of Port A or Port D. Note: if one of the pins of Port D is used as output, the pull up of the corresponding pin of Port A should be disabled in order to have low power consumption. © Semtech 2006 www.semtech.com 1-5 XE8806A/XE8807A 1.2.4 Bare die XE8806A The circuit is also available in bare die for chip on board assembly. All VBAT pins and all VSS pins should be connected together. The substrate of the circuit is connected to VSS. ( 792,3580) (1065,3580) (1369,3580) (1584,3580) (2478,3580) (2780,3580) (3287,3580) (3584,3580) PB(4) VSS PD(4) PA(4) PA(3) PD(3) PB(3) PB(2) (123, 2658) PB(5) PB(6) VBAT ( 477,3580) (123, 3236) (123,2970) PB(1) (3787,3078) PB(7) PB(0) (3787,2714) (123,2345) PD(5) PD(2) (3787,2354) (123,2113) PA(5) PA(2) (3787,2082) PA(1) (3787,1530) PD(1) (3787,1178) XEMICS 4050µm PA(6) (123,1072) PD(6) (123, 835) TEST (123, 545) VSS VSS (3787, 588) VREG VPP (3787, 340) (123, 310) 3850µm (123,1386) NRESET (3787, 913) PA(0) PD(0) VSS (2572,118) (2808,118) (3022,118) (3324,118) (3589,118) (1906,118) (2141,118) VBAT XIN XOUT VSS ( 992,118) ( 707,118) (1212,118) ( 472,118) VBAT PA(7) VBAT PD(7) Figure 1-5. Die dimension and pin location of the XE8806A © Semtech 2006 www.semtech.com 1-6 XE8806A/XE8807A 1.2.5 Bare die XE8807A The circuit is also available in bare die for chip on board assembly. All VBAT pins and all VSS pins should be connected together. The substrate of the circuit is connected to VSS. ( 792,3580) (1065,3580) (1369,3580) (1584,3580) (2478,3580) (2780,3580) (3287,3580) (3584,3580) PB(4) VSS PD(4) PA(4) PA(3) PD(3) PB(3) PB(2) (123, 2658) PB(5) PB(6) VBAT ( 477,3580) (123, 3236) (123,2970) PB(1) (3787,3078) PB(7) PB(0) (3787,2714) (123,2345) PD(5) PD(2) (3787,2354) (123,2113) PA(5) PA(2) (3787,2082) PA(1) (3787,1530) PD(1) (3787,1178) XEMICS 4050µm PA(6) (123,1072) PD(6) (123, 835) TEST (123, 545) VSS VSS (3787, 588) VREG VPP (3787, 340) (123, 310) 3850µm (123,1386) NRESET (3787, 913) PA(0) PD(0) VSS (2572,118) (2808,118) (3022,118) (3324,118) (3589,118) (1906,118) (2141,118) VBAT XIN XOUT VSS ( 992,118) ( 707,118) (1212,118) ( 472,118) VSS PA(7) VBAT PD(7) Figure 1-6. Die dimension and pin location of the XE8807A 1.3 Pin assignment The table below gives a short description of the different pin assignments. Pin Assignment VBAT Positive power supply VSS Negative power supply VREG Connection for the mandatory external capacitor of the voltage regulator VPP High voltage supply for flash memory programming (NC in ROM versions) NRESET Resets the circuit when the voltage is low TEST Sets the pin to flash programming mode XIN/XOUT Quartz crystal connections, also used for flash memory programming PA(7:0) Parallel input port A pins PB(7:0) Parallel I/O port B pins PD(7:0) Parallel I/O port D pins Table 1-1. Pin assignment © Semtech 2006 www.semtech.com 1-7 XE8806A/XE8807A Table 1-2 gives a more detailed pin map for the different pins in the different packages. It also indicates the possible I/O configuration of these pins. The indications in blue bold are the configuration at start-up. Please note that in the SO-28 and SO-24 package several functions are routed to the same package pins. These pins are indicated in red italic. The pins RFIF(3:0) are the I/O pins of the RF interface, the CNTx pins are possible counter inputs, PWMx are possible PWM outputs, the CMPD pins are comparator inputs. POWER SNAP PD X PU DO X X OD DI PD(7) PA(7) VSS XIN XOUT VBAT PA(0) PD(0) VPP NRESET PD(1) PA(1) PA(2) PD(2) PB(0) PB(1) PB(2) PB(3) PD(3) PA(3) PA(4) PD(4) PB(4) PB(5) PB(6) PB(7) PD(5) PA(5) PA(6) PD(6) TEST VREG AO 4 4 5 6 7 8 9 9 10 11 12 12 13 13 14 15 16 17 18 18 19 19 20 21 22 23 24 24 1 1 2 3 AI first 4 5 6 7 8 9 10 11 12 13 14 14 15 15 16 17 18 19 20 21 22 23 24 25 26 27 28 28 1 1 2 3 third SO-24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O configuration second SO-28 function tqfp-32 pin number X X X X X X X X CNTA RFIF(0) X X X X X X X X RFIF(1) CNTB CNTC RFIF(2) PWM0 PWM1 X X X X X X X X RFIF(3) CNTD USRT_S0 USRT_S1 UART_Tx UART_Rx CMPD(0) CMPD(1) CMPD(2) CMPD(3) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Table 1-2. Pin description table Pin map table legend: red italic: pin shared with another peripheral in a specific package blue bold: configuration at start up AI: analog input AO: analog output DI: digital input DO: digital output OD: nMOS open drain output PU: pull-up resistor PD: pull-down resistor SNAP: snap-to-rail function (see peripheral description for detailed description) POWER: power supply © Semtech 2006 www.semtech.com 1-8 XE8806A/XE8807A 2 XE8806A and XE8807A Performance 2.1 Absolute maximum ratings 2-2 2.2 Operating range 2-2 2.3 Current consumption 2-3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 Operating speed Flash circuit version XE8806AM Flash circuit version XE8807AM ROM circuit version, regulator on ROM circuit version, regulator by-passed 2-4 2-4 2-5 2-5 2-6 © Semtech 2006 www.semtech.com 2-1 XE8806A/XE8807A 2.1 Absolute maximum ratings Voltage applied to VBAT with respect to VSS Voltage applied to VPP with respect to VSS Voltage applied to all pins except VPP and VBAT Storage temperature (ROM device or unprogrammed flash device) Storage temperature (programmed flash device) Min. Max. -0.3 VBAT-0.3 VSS-0.3 -55 6.0 12 VBAT+0.3 150 V V V °C Note -40 85 °C Table 2-1. Absolute maximal ratings Stresses beyond the absolute maximal ratings may cause permanent damage to the device. Functional operation at the absolute maximal ratings is not implied. Exposure to conditions beyond the absolute maximal ratings may affect the reliability of the device. 2.2 Operating range Voltage applied to VBAT with respect to VSS Voltage applied to VBAT with respect to VSS during the flash programming Voltage applied to VPP with respect to VSS Voltage applied to all pins except VPP and VBAT Operating temperature range Capacitor on VREG Min. Max. Note 2.4 4.5 5.5 5.5 V V VBAT VSS -40 0.8 11.5 VBAT 85 1.2 V V °C µF 1 Table 2-2. Operating range for the flash device Note 1. During the programming of the device, the supply voltage should at least be equal to the supply voltage used during normal operation, and temperature between 10°C and 40°C. Min. Voltage applied to VBAT VREG by-passed with respect to VSS VREG on Voltage applied to all pins except VPP and VBAT Operating temperature range Capacitor on VREG 1.2 1.5 VSS -40 0.1 Max. Note 5.5 3.6 VBAT 125 1.2 V V V °C µF 1 Table 2-3. Operating range for the ROM device Note 1. The capacitor may be omitted when VREG is connected to VBAT. All specifications in this document are valid for the complete operating range unless otherwise specified. Min. Retention time at 85°C Retention time at 55°C Number of programming cycles 10 100 10 Max. Note years years 1 1 2 Table 2-4. Operating range of the Flash memory Note 1. Valid only if programmed using a programming tool that is qualified Note 2. Circuits can be programmed more than 10 times but in that case, the retention time is no longer guaranteed. © Semtech 2006 www.semtech.com 2-2 XE8806A/XE8807A 2.3 Current consumption The tables below give the current consumption for the circuit in different configurations. The figures are indicative only and may change as a function of the actual software implemented in the circuit. Table 2-5 gives the current consumption for the flash version of the circuit. The peripherals (USRT, UART, CNT, VLD, CMPD) are disabled. The parallel ports are configured in input with pull up. Their pins are not connected externally. Operation mode CPU RC Xtal Consumption comments Note 32 kHz 200 µA 320 µA 410 µA 310 µA 21 µA 33 µA 42 µA 7.5 µA 11.0 µA 14.5 µA 1.9 µA 2.4V 5.5V, 27°C Ready 32kHz 2.3 µA 2.4V 5.5V, 27°C 1 MHz Off 35 µA 2.4V 5.5V, 27°C 15 µA 2 µA 2.4V 5.5V, 27°C 2.4V 5.5V, 27°C High speed CPU 1 MIPS 1 MHz Off Low speed CPU .1 MIPS 100 kHz Off Low power CPU 32 kIPS Off 32 kHz HALT Off HALT HALT Low power time keeping Fast wake-up time keeping Immediate wakeup time keeping VLD static current CMPD static current 2.4V5.5V, 27°C 2.4V 5.5V, 27°C 2.4V 5.5V, 27°C 1 2 3 4 1 2 3 1 2 3 Table 2-5. Typical current consumption of the XE8806AM version (8k instructions flash memory) and XE8807AM version (4k instructions flash memory) 1. 2. 3. 4. Software without data access 100% low power RAM access 100% RAM access typical software Table 2-6 shows the typical current consumption for the ROM version with 8k instructions. Two possible modes are possible: a 2.4V-5.5V operating range using the internal regulator and a 1.2V-3.3V operating range short circuiting the voltage regulator (i.e. connect VREG to VBAT). Operation mode CPU RC Xtal Consumption comments Note High speed CPU Max. Speed CPU Low speed CPU Low power CPU Low voltage CPU Low power time keeping 1 MIPS 4 MIPS .1 MIPS 32 kIPS 32 kIPS HALT 1 MHz 4 MHz 100 kHz Off Off Off Off Off Off 32 kHz 32 kHz 32 kHz 200 800 21 7 1 1.3 2.4V5.5V, 27°C 2.4V5.5V, 27°C 2.4V 5.5V, 27°C 2.4V 5.5V, 27°C 1.2V, 27°C 2.4V 5.5V, 27°C 1,2 1,2 1,2 1,2 1,3 2 Table 2-6. Current consumption of the XE8806AR version (8k instructions ROM memory) 1. Software using MOVE instruction using internal CPU registers and peripheral registers. 2. Using the internal voltage regulator (see Figure 2-5). 3. With the internal regulator short circuited (i.e. by connecting VREG to VBAT, see Figure 2-7). In this case, the current consumption will increase with VBAT. © Semtech 2006 www.semtech.com 2-3 XE8806A/XE8807A Hints for low power operation: 1. Use the low power RAM instead of the RAM for all parameters that are accessed frequently. The average current consumption for the low power RAM is about 40 times lower than for the RAM. 2. Rather than using the circuit at low speed, it is better to use the circuit at higher speed and switch off the blocks when not needed. 3. The power consumption of the program memory is an important part of the overall power consumption. In case you intend to use a ROM version and power consumption is too high, please ask us to provide you with a circuit version with smaller ROM size. 2.4 2.4.1 Operating speed Flash circuit version XE8806AM The speed of the flash devices is not highly dependent upon the supply voltage. However, by limiting the temperature range, the speed can be increased. The minimal guaranteed speed as a function of the supply voltage and maximal temperature operating temperature is given in Figure 2-2. VBAT 2.4 - 5.5 V VREG 1uF VSS speed (MIPS) Figure 2-1. Supply configuration for flash circuit operation. 3.5 3 2.5 2 1.5 1 0.5 0 85°C 2 2.5 3 3.5 4 4.5 45°C 5 5.5 supply voltage VBAT (V) Figure 2-2. Guaranteed speed as a function of the supply voltage and maximal temperature. Note that the speed of the flash circuit version is limited by the flash memory. All other peripherals of the device can run at the same speed as the ROM version (see Figure 2-6). The maximal speed of the peripherals can be exploited by reducing the CPU frequency by a factor of 2 with respect to the clock source by executing the instruction “FREQ div2”. Take care to execute this instruction before increasing the clock speed above the figures given in Figure 2-2. © Semtech 2006 www.semtech.com 2-4 XE8806A/XE8807A 2.4.2 Flash circuit version XE8807AM The speed of the flash devices is not highly dependent upon the supply voltage. However, by limiting the temperature range, the speed can be increased. The minimal guaranteed speed as a function of the supply voltage and maximal temperature operating temperature is given in Figure 2-4. VBAT 2.4 - 5.5 V VREG 1uF VSS speed (MIPS) Figure 2-3. Supply configuration for flash circuit operation. 7 6 5 4 3 2 1 0 85°C 2 2.5 3 3.5 4 45°C 4.5 5 5.5 supply voltage VBAT (V) Figure 2-4. Guaranteed speed as a function of the supply voltage and maximal temperature. 2.4.3 ROM circuit version, regulator on For the ROM version, two possible operating modes exist: with and without voltage regulator. Using the voltage regulator, a low power consumption will be obtained even with supply voltages above 2.4V. Without the voltage regulator (i.e. VREG short-circuited to VBAT) , a higher speed can be obtained. VBAT 2.4 - 5.5 V VREG 100nF VSS Figure 2-5. Supply configuration for ROM circuit operation using the internal regulator. © Semtech 2006 www.semtech.com 2-5 XE8806A/XE8807A 85°C 45°C 125°C speed (MIPS) 8 6 4 2 0 2 2.5 3 3.5 4 4.5 5 5.5 supply voltage VBAT (V) Figure 2-6. Guaranteed speed as a function of supply voltage and for different maximal temperatures using the voltage regulator. 2.4.4 ROM circuit version, regulator by-passed VBAT VREG 1.2 – 3.3 V VSS Figure 2-7. Supply configuration for ROM circuit operation by-passing the internal regulator. 85°C 45°C 1.5 2 125°C speed (MIPS) 8 6 4 2 0 1 2.5 3 3.5 supply voltage VBAT (V) Figure 2-8. Guaranteed speed as a function of supply voltage and for two temperature ranges when VREG=VBAT. © Semtech 2006 www.semtech.com 2-6 XE8806A/XE88L7A 3. CPU CONTENTS 3.1 CPU description 3-2 3.2 CPU internal registers 3-2 3.3 CPU instruction short reference 3-4 © Semtech 2006 www.semtech.com 3-1 XE8806A/XE8807A 3.1 CPU description The CPU of the XE8000 series is a low power RISC core. It has 16 internal registers for efficient implementation of the C compiler. Its instruction set is made up of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. The circuit therefore runs on 1 MIPS on a 1MHz clock. The CPU hardware and software description is given in the document “Coolrisc816 Hardware and Software Reference Manual”. A short summary is given in the following paragraphs. The good code efficiency of the CPU core makes it possible to compute a polynomial like Z = ( A0 + A1 ⋅ Y ) ⋅ X + B0 + B1 ⋅ Y in less than 300 clock cycles (software code generated by the XEMICS Ccompiler, all numbers are signed integers on 16 bits). 3.2 CPU internal registers As shown in Figure 3-1, the CPU has 16 internal 8-bit registers. Some of these registers can be concatenated to a 16-bit word for use in some instructions. The function of these registers is defined in Table 3-1. The status register stat (Table 3-2) is used to manage the different interrupt and event levels. An interrupt or an event can both be used to wake up after a HALT instruction. The difference is that an interrupt jumps to a special interrupt function whereas an event continues the software execution with the instruction following the HALT instruction. The program counter (PC) is a 16 bit register that indicates the address of the instruction that has to be executed. The stack (STn) is used to memorise the return address when executing subroutines or interrupt routines. ST4 ST3 ST1 ST2 r0 r1 Data memory r2 data bus 22bit CPU CPU internal registers Instruction memory instruction bus PC program counter stack r3 i0h i0l i1h i1l i2h i2l i3h i3l iph ipl stat a Figure 3-1. CPU internal registers © Semtech 2006 www.semtech.com 3-2 XE8806A/XE8807A Register name r0 r1 r2 r3 i0h i0l i1h i1l i2h i2l i3h i3l iph ipl stat a Register function general purpose general purpose general purpose data memory offset MSB of the data memory index i0 LBS of the data memory index i0 MSB of the data memory index i1 LBS of the data memory index i1 MSB of the data memory index i2 LBS of the data memory index i2 MSB of the data memory index i3 LBS of the data memory index i3 MSB of the program memory index ip LBS of the program memory index ip status register accumulator Table 3-1. CPU internal register definition bit 7 6 5 4 name IE2 IE1 GIE IN2 3 IN1 2 IN0 1 EV1 0 EV0 function enables (when 1) the interrupt request of level 2 enables (when 1) the interrupt request of level 1 enables (when 1) all interrupt request levels interrupt request of level 2. The interrupts labelled “low” in the interrupt handler are routed to this interrupt level. This bit has to be cleared when the interrupt is served. interrupt request of level 1. The interrupts labelled “mid” in the interrupt handler are routed to this interrupt level. This bit has to be cleared when the interrupt is served. interrupt request of level 0. The interrupts labelled “hig” in the interrupt handler are routed to this interrupt level. This bit has to be cleared when the interrupt is served. event request of level 1. The events labelled “low” in the event handler are routed to this event level. This bit has to be cleared when the event is served. event request of level 1. The events labelled “hig” in the event handler are routed to this event level. This bit has to be cleared when the event is served. Table 3-2. Status register description The CPU also has a number of flags that can be used for conditional jumps. These flags are defined in Table 3-3. symbol Z C V name zero carry overflow function Z=1 when the accumulator a content is zero This flag is used in shift or arithmetic operations. For a shift operation, it has the value of the bit that was shifted out (LSB for shift right, MSB for shift left). For an arithmetic operation with unsigned numbers: it is 1 at occurrence of an overflow during an addition (or equivalent). it is 0 at occurrence of an underflow during a subtraction (or equivalent). This flag is used in shift or arithmetic operations. For arithmetic or shift operations with signed numbers, it is 1 if an overflow or underflow occurs. Table 3-3. Flag description © Semtech 2006 www.semtech.com 3-3 XE8806A/XE8807A 3.3 CPU instruction short reference Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation cc in the conditional jump instruction refers to the condition description as given in Table 3-6. The notation reg, reg1, reg2, reg3 refers to one of the CPU internal registers of Table 3-1. The notation eaddr and DM(eaddr) refer to one of the extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with address xxx. Instruction Modification Operation Jump addr[15:0] Jump ip Jcc addr[15:0] Jcc ip Call addr[15:0] Call ip Calls addr[15:0] Calls ip -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, - PC := addr[15:0] PC := ip if cc is true then PC := addr[15:0] if cc is true then PC := ip STn+1 := STn (n>1); ST1 := PC+1; PC := addr[15:0] STn+1 := STn (n>1); ST1 := PC+1; PC := ip ip := PC+1; PC := addr[15:0] ip := PC+1; PC := ip Ret Rets Reti Push Pop -,-,-, -,-,-, -,-,-, -,-,-, -,-,-, - PC := ST1; STn := STn+1 (n>1) PC := ip PC := ST1; STn := STn+1 (n>1); GIE :=1 PC := PC+1; STn+1 := STn (n>1); ST1 := ip PC := PC+1; ip := ST1; STn := STn+1 (n>1) Move reg,#data[7:0] Move reg1, reg2 Move reg, eaddr Move eaddr, reg Move addr[7:0],#data[7:0] -,-, Z, a -,-, Z, a -,-, Z, a -,-,-, -,-,-, - a := data[7:0]; reg := data[7:0] a := reg2; reg1 := reg2 a := DM(eaddr); reg := DM(eaddr) DM(eaddr) := reg DM(addr[7:0]) := data[7:0] Cmvd reg1, reg2 Cmvd reg, eaddr Cmvs reg1, reg2 Cmvs reg, eaddr -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a a := reg2; if C=0 then reg1 := a; a := DM(eaddr); if C=0 then reg := a a := reg2; if C=1 then reg1 := a; a := DM(eaddr); if C=1 then reg := a Shl reg1, reg2 Shl reg Shl reg, eaddr Shlc reg1, reg2 Shlc reg Shlc reg, eaddr Shr reg1, reg2 Shr reg Shr reg, eaddr Shrc reg1, reg2 Shrc reg Shrc reg, eaddr Shra reg1, reg2 Shra reg Shra reg, eaddr C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a a := reg21; a[7] := C; C := DM(eaddr)[0]; reg := a a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a Cpl1 reg1, reg2 Cpl1 reg Cpl1 reg, eaddr Cpl2 reg1, reg2 Cpl2 reg Cpl2 reg, eaddr Cpl2c reg1, reg2 Cpl2c reg Cpl2c reg, eaddr -,-, Z, a -,-, Z, a -,-, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a a := NOT(reg2); reg1 := a a := NOT(reg); reg := a a := NOT(DM(eaddr)); reg := a a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a Inc reg1, reg2 Inc reg Inc reg, eaddr Incc reg1, reg2 Incc reg Incc reg, eaddr Dec reg1, reg2 C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a a := reg+1; if a=0 then C := 1 else C := 0; reg := a a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a © Semtech 2006 www.semtech.com 3-4 XE8806A/XE8807A Dec reg Dec reg, eaddr Decc reg1, reg2 Decc reg Decc reg, eaddr C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a a := reg-1; if a=hFF then C := 0 else C := 1; reg := a a := DM(eaddr)-1; if a=hFF then C := 0 else C := 1; reg := a a := reg2-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg1 := a a := reg-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a a := DM(eaddr)-(1-C); if a=hFF and C=0 then C := 0 else C := 1; reg := a And reg,#data[7:0] And reg1, reg2, reg3 And reg1, reg2 And reg, eaddr Or reg,#data[7:0] Or reg1, reg2, reg3 Or reg1, reg2 Or reg, eaddr Xor reg,#data[7:0] Xor reg1, reg2, reg3 Xor reg1, reg2 Xor reg, eaddr -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a -,-, Z, a a := reg and data[7:0]; reg := a a := reg2 and reg3; reg1 := a a := reg1 and reg2; reg1 := a a := reg and DM(eaddr); reg := a a := reg or data[7:0]; reg := a a := reg2 or reg3; reg1 := a a := reg1 or reg2; reg1 := a a := reg or DM(eaddr); reg := a a := reg xor data[7:0]; reg := a a := reg2 xor reg3; reg1 := a a := reg1 xor reg2; reg1 := a a := reg or DM(eaddr); reg := a Add reg,#data[7:0] Add reg1, reg2, reg3 Add reg1, reg2 Add reg, eaddr Addc reg,#data[7:0] Addc reg1, reg2, reg3 Addc reg1, reg2 Addc reg, eaddr Subd reg,#data[7:0] Subd reg1, reg2, reg3 Subd reg1, reg2 Subd reg, eaddr Subdc reg,#data[7:0] Subdc reg1, reg2, reg3 Subdc reg1, reg2 Subdc reg, eaddr Subs reg,#data[7:0] Subs reg1, reg2, reg3 Subs reg1, reg2 Subs reg, eaddr Subsc reg,#data[7:0] Subsc reg1, reg2, reg3 Subsc reg1, reg2 Subsc reg, eaddr C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a a := reg+data[7:0]; if overflow then C:=1 else C := 0; reg := a a := reg2+reg3; if overflow then C:=1 else C := 0; reg1 := a a := reg1+reg2; if overflow then C:=1 else C := 0; reg1 := a a := reg+DM(eaddr); if overflow then C:=1 else C := 0; reg := a a := reg+data[7:0]+C; if overflow then C:=1 else C := 0; reg := a a := reg2+reg3+C; if overflow then C:=1 else C := 0; reg1 := a a := reg1+reg2+C; if overflow then C:=1 else C := 0; reg1 := a a := reg+DM(eaddr)+C; if overflow then C:=1 else C := 0; reg := a a := data[7:0]-reg; if underflow then C := 0 else C := 1; reg := a a := reg2-reg3; if underflow then C := 0 else C := 1; reg1 := a a := reg2-reg1; if underflow then C := 0 else C := 1; reg1 := a a := DM(eaddr)-reg; if underflow then C := 0 else C := 1; reg := a a := data[7:0]-reg-(1-C); if underflow then C := 0 else C := 1; reg := a a := reg2-reg3-(1-C); if underflow then C := 0 else C := 1; reg1 := a a := reg2-reg1-(1-C); if underflow then C := 0 else C := 1; reg1 := a a := DM(eaddr)-reg-(1-C); if underflow then C := 0 else C := 1; reg := a a := reg-data[7:0]; if underflow then C := 0 else C := 1; reg := a a := reg3-reg2; if underflow then C := 0 else C := 1; reg1 := a a := reg1-reg2; if underflow then C := 0 else C := 1; reg1 := a a := reg-DM(eaddr); if underflow then C := 0 else C := 1; reg := a a := reg-data[7:0]-(1-C); if underflow then C := 0 else C := 1; reg := a a := reg3-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a a := reg1-reg2-(1-C); if underflow then C := 0 else C := 1; reg1 := a a := reg-DM(eaddr)-(1-C); if underflow then C := 0 else C := 1; reg := a Mul reg,#data[7:0] Mul reg1, reg2, reg3 Mul reg1, reg2 Mul reg, eaddr Mula reg,#data[7:0] Mula reg1, reg2, reg3 Mula reg1, reg2 Mula reg, eaddr u, u, u, a u, u, u, a u, u, u, a u, u, u, a u, u, u, a u, u, u, a u, u, u, a u, u, u, a a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8] a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8] a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8] a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8] a := (data[7:0]*reg)[7:0]; reg := (data[7:0]*reg)[15:8] a := (reg2*reg3)[7:0]; reg1 := (reg2*reg3)[15:8] a := (reg2*reg1)[7:0]; reg1 := (reg2*reg1)[15:8] a := (DM(eaddr)*reg)[7:0]; reg := (DM(eaddr)*reg)[15:8] Mshl reg,#shift[2:0] Mshr reg,#shift[2:0] Mshra reg,#shift[2:0] u, u, u, a u, u, u, a u, u, u, a* a := (reg*2 )[7:0]; reg := (reg*2 )[15:8] (8-shift (8-shift a := (reg*2 )[7:0]; reg := (reg*2 )[15:8] (8-shift (8-shift a := (reg*2 )[7:0]; reg := (reg*2 )[15:8] Cmp reg,#data[7:0] Cmp reg1, reg2 Cmp reg, eaddr Cmpa reg,#data[7:0] Cmpa reg1, reg2 Cmpa reg, eaddr C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a C, V, Z, a a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z) a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z) a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z) a := data[7:0]-reg; if underflow then C :=0 else C:=1; V := C and (not Z) a := reg2-reg1; if underflow then C :=0 else C:=1; V := C and (not Z) a := DM(eaddr)-reg; if underflow then C :=0 else C:=1; V := C and (not Z) Tstb reg,#bit[2:0] Setb reg,#bit[2:0] Clrb reg,#bit[2:0] Invb reg,#bit[2:0] -, -, Z, a -, -, Z, a -, -, Z, a -, -, Z, a a[bit] := reg[bit]; other bits in a are 0 reg[bit] := 1; other bits unchanged; a := reg reg[bit] := 0; other bits unchanged; a := reg reg[bit] := not reg[bit]; other bits unchanged; a := reg shift shift © Semtech 2006 www.semtech.com 3-5 XE8806A/XE8807A Sflag -,-,-, a a[7] := C; a[6] := C xor V; a[5] := ST full; a[4] := ST empty Rflag reg Rflag eaddr C, V, Z, a C, V, Z, a a := reg