GS71024U-12

GS71024T/U TQFP, FP-BGA Commercial Temp Industrial Temp Features • Fast access time: 8, 9, 10, 12, 15 ns • CMOS low power operation: 190/170/160/130/110 mA at minimum cycle time. • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40 to 85°C • Package T: 100-pin TQFP package U: 6 mm x 8 mm Fine Pitch Ball Grid Array GT: Pb-Free 100-pin TQFP available 64K x 24 1.5Mb Asynchronous SRAM 1 A B C D E F G H 2 3 4 8, 9, 10, 12, 15 ns 3.3 V VDD Center VDD and VSS Fine Pitch BGA Bump Configuration 5 6 DQ DQ DQ VSS VDD DQ DQ DQ A3 DQ DQ DQ DQ DQ DQ A15 A2 CE2 CE1 A5 A7 A9 A11 A14 A1 WE OE A4 A6 A8 A10 A13 A0 DQ DQ DQ DQ DQ DQ A12 DQ DQ DQ VDD VSS DQ DQ DQ Description The GS71024 is a high speed CMOS static RAM organized as 65,536 words by 24 bits. Static design eliminates the need for external clocks or timing strobes. The GS71024 operates on a single 3.3 V power supply, and all inputs and outputs are TTLcompatible. The GS71024 is available in a 6 mm x 8 mm Fine Pitch BGA package, as well as in a 100-pin TQFP package. 6 mm x 8 mm, 0.75 mm Bump Pitch Top View Pin Descriptions Symbol A0 to A15 X/Y WE CE1, CE2 VDD Description Address input Vector Input Write enable input Chip enable input +3.3 V power supply Symbol DQ1 to DQ24 V/S OE — VSS Description Data input/output Address Multiplexer Control Output enable input — Ground Block Diagram A0 Row Decoder Address Input A14 A15 X/Y V/S CE1 CE2 WE OE Memory Array 1024 x 1536 0 1 Q Column Decoder Control I/O Buffer DQ1 DQ24 Rev: 1.05 11/2004 1/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U 100-Pin TQFP Pinout A A CE1 CE2 NC NC NC X/Y V/S NC NC NC NC NC DQ DQ DQ DQ VSS VDD DQ DQ NC VDD NC VSS DQ DQ VDD VSS DQ DQ DQ DQ NC NC NC NC NC VDD VSS NC WE NC OE NC NC NC A0 A1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 Top View 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC NC NC DQ DQ DQ DQ VSS VDD DQ DQ VSS NC VDD NC DQ DQ VDD VSS DQ DQ DQ DQ NC NC NC NC NC NC A A A A A A NC NC VSS VDD Rev: 1.05 11/2004 2/13 NC NC A A A A A A NC © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Truth Table CE1 H X L L L L L X: “H” or “L” CE2 X L H H H H H OE X X L L X X H WE X X H H L L H V/S X X H L H L X Mode Not selected Not selected Read using X/Y Read using A15 Write using X/Y Write using A15 Output disable DQ0 to DQ23 High Z High Z Data Out Data Out Data In Data In High Z IDD VDD Current ISB1, ISB2 Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Allowable TQFP power dissipation Allowable FPBGA power dissipation Storage temperature Symbol VDD VIN VOUT PD PD TSTG Rating –0.5 to +4.6 –0.5 to VDD + 0.5 (≤ 4.6 V max.) –0.5 to VDD + 0.5 (≤ 4.6 V max.) 1 1 –55 to 150 Unit V V V W W o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Rev: 1.05 11/2004 3/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Recommended Operating Conditions Parameter Supply Voltage for -10/12/15 Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range Symbol VDD VDD VIH VIL TAc TAi Minimum 3.0 3.135 2.0 –0.3 0 –40 Typical 3.3 3.3 — — — — Maximum 3.6 3.6 VDD + 0.3 0.8 70 85 Unit V V V V o C oC Notes: 1. Input overshoot voltage should be less than VDD + 2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Capacitance Parameter Input Capacitance I/O Capacitance Symbol CIN COUT Test Condition VIN = 0 V VOUT = 0 V Maximum 5 7 Unit pF pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested DC I/O Pin Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol IIL IOL VOH VOL Test Conditions VIN = 0 to VDD Output High Z, VOUT = 0 to VDD IOH = –4mA IOL = +4mA Minimum –1uA –1uA 2.4 — Maximum 1uA 1uA — 0.4 V Rev: 1.05 11/2004 4/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U AC Test Conditions Parameter Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load Conditions VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2 Output Load 1 DQ 50Ω VT = 1.4 V 30pF1 Output Load 2 3.3 V DQ 5pF1 589Ω 434Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. Power Supply Currents Parameter Symbol Test Conditions CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time CE ≥ VDD – 0.2 V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V 0 to 70°C 8 ns 9 ns 10 ns 12 ns 15 ns 10 ns -40 to 85°C 12 ns 15 ns Operating Supply Current IDD 190 mA 170 mA 160 mA 130 mA 110 mA 165 mA 135 mA 115 mA Standby Current ISB1 45 mA 45 mA 40 mA 35 mA 30 mA 45 mA 40 mA 35 mA Standby Current ISB2 10 mA 15 mA Rev: 1.05 11/2004 5/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U AC Characteristics Read Cycle Parameter Read cycle time Address access time Chip enable access time (CE1, CE2) MUX control to output valid (V/S) Output enable to output valid (OE) Output hold from address change Output hold from MUX controls change Chip enable to output in low Z (CE1, CE2) Output enable to output in low Z (OE) Chip disable to output in High Z (CE1, CE2) Output disable to output in High Z (OE) Symbol tRC tAA tAC tAV tOE tOH tOH1 tLZ* tOLZ* tHZ* tOHZ* -8 Min 8 — — — — 3 3 3 0 — — Max — 8 8 8 4 — — — — 4 4 Min 9 — — — — 3 3 3 0 — — -9 Max — 9 9 9 4.5 — — — — 4.5 4.5 Min 10 — — — — 3 3 3 0 — — -10 Max — 10 10 10 5 — — — — 5 5 Min 12 — — — — 3 3 3 0 — — -12 Max — 12 12 12 6 — — — — 6 6 Min 15 — — — — 3 3 3 0 — — -15 Max — 15 15 15 7 — — — — 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns * These parameters are sampled and are not 100% tested Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA V/S tOH Data Out Previous Data tOH1 tAV Data valid Rev: 1.05 11/2004 6/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Read Cycle 2: WE = VIH tRC Address tAA CE1(*1) tAC tLZ V/S OE tOLZ High impedance tOE Data valid tHZ tAV tOHZ Data Out *1 CE1 represents both CE1 low and CE2 high. Rev: 1.05 11/2004 7/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Write Cycle Parameter Write cycle time Address valid to end of write Chip enable to end of write (CE1, CE2) MUX control to end of write (V/S) Data set up time Data hold time Write pulse width Address set up time MUX control set up time Write recovery time (WE) Write recovery time (V/S, CE1, CE2 ) Output Low Z from end of write Write to output in High Z Symbol tWC tAW tCW tVW tDW tDH tWP tAS tVS tWR tWR1 tWLZ* tWHZ* -8 Min 8 5.5 5.5 5.5 4 0 5.5 0 0 0 0 2 — Max — — — — — — — — — — — — 4 Min 9 6.25 6.25 6.25 4.5 0 6.25 0 0 0 0 2.5 — -9 Max — — — — — — — — — — — — 4.5 Min 10 7 7 7 5 0 7 0 0 0 0 3 — -10 Max — — — — — — — — — — — — 5 Min 12 8 8 8 6 0 8 0 0 0 0 3 — -12 Max — — — — — — — — — — — — 6 Min 15 10 10 10 7 0 10 0 0 0 0 3 — -15 Max — — — — — — — — — — — — 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns * These parameters are sampled and are not 100% tested Rev: 1.05 11/2004 8/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Write Cycle 1: WE control tWC Address tAW OE tCW CE1 V/S tAS WE Data In tWHZ Data Out High impedance (*1) tWR tVS tVW tWP (*2) tDW Data valid tDH tWLZ (*3) (*3) *1 CE1 represents both CE1 low and CE2 high. *2 Write is executed when both CE1 and WE are at low simultaneously. *3 Do not apply the data input voltage to the output while DQ pin is in output condition. Write Cycle 2: CE control tWC Address tAW OE tAS CE1 V/S WE Data In Data Out tWP tDW Data valid (*1) tWR1 tCW tVW tDH High impedance *1 CE1 represents both CE1 low and CE2 high. Rev: 1.05 11/2004 9/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U 6 mm x 8 mm Fine Pitch BGA 8.00 ± 0.10 6.00 ± 0.10 0.22 ± 0.05 0.10 2 1 6 0.75(typ). 10/13 Top View 1.20(max) pin A1 index Bottom View pin A1 index 5 4 Rev: 1.05 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Ball Dia. 0.35 Pitch 0.75 © 1999, GSI Technology 3.75 3 0.36(typ) G D C H A B E F D units: mm 5.25 GS71024T/U TQFP Package Drawing θ L c Min. Nom. Max L1 0.05 0.10 0.15 1.35 0.20 0.09 21.9 19.9 15.9 13.9 0.45 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.10 0° 7° 0.75 1.40 0.30 1.45 0.40 0.20 22.1 20.1 16.1 14.1 Symbol A1 A2 b c D D1 E E1 e L L1 Y θ Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Pin 1 e b D D1 Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion A1 Y A2 E1 E BPR 1999.05.18 Rev: 1.05 11/2004 11/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Ordering Information Part Number GS71024T-8 GS71024T-9 GS71024T-10 GS71024T-12 GS71024T-15 GS71024T-8I GS71024T-9I GS71024T-10I GS71024T-12I GS71024T-15I GS71024GT-8 GS71024GT-9 GS71024GT-10 GS71024GT-12 GS71024GT-15 GS71024GT-8I GS71024GT-9I GS71024GT-10I GS71024GT-12I GS71024GT-15I GS71024U-8 GS71024U-9 GS71024U-10 GS71024U-12 GS71024U-15 GS71024U-8I GS71024U-9I GS71024U-10I Package 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP Pb-free 100-Pin TQFP 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA Access Time 8 ns 9 ns 10 ns 12 ns 15 ns 8 ns 9 ns 10 ns 12 ns 15 ns 8 ns 9 ns 10 ns 12 ns 15 ns 8 ns 9 ns 10 ns 12 ns 15 ns 8 ns 9 ns 10 ns 12 ns 15 ns 8 ns 9 ns 10 ns Temp. Range Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Status Rev: 1.05 11/2004 12/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71024T/U Ordering Information Part Number GS71024U-12I GS71024U-15I Package 6 mm x 8 mm Fine Pitch BGA 6 mm x 8 mm Fine Pitch BGA Access Time 12 ns 15 ns Temp. Range Industrial Industrial Status * Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS71024T/U-12T. Revision History Rev. Code: Old; New Types of Changes Format or Content Format/Typos GS71024Rev 2:17pm, 4/8/ 1999; 1.00a5/1999 Page/Revisions/Reason • Document Changed subscripts to small caps. • 1/Features: Changed TP to T. • Document/Replaced “micro” with “fine pitch”. • Ordering Information/Added Tape and Reel Note/ Enhancement • Pin Description/Changed A0 - A14 to A0 - A15/Correction • Page 1/Took out “Byte Control” from Features/Correction • 3/Changed pin 97 from NC to CE2/Correction • 1. 2. 3. 4. Pin out/Changed Pin 89 from CK to NC/Correction Pin out/Changed Pin 92 from NC to V/S/Correction Pin out/Changed Pin 93 from V/S to X/Y/Correction Pin out/Changed Pin 94 from X/Y to NC/Correction Content GS710241.00a5/1999; 1.01 8/1999B GS710241.01 8/1999C; 1.02 9/1999C GS71024Rev1.01 8/ 1999C;Rev1.02 2/2000D Content Content Format • Package Diagram/Changed Dimension “D Max” from 20.1 to 22.1/Correction • GSI Logo Rev1.02 2/2000D; 71024_r1_03 • Updated format to comply with Technical Publications standards Format and Content • Changed all VSSQ to VSS and all VDDQ to VDD in pinout on page 2 • Updated Revision History (revision notes for 8/1999 incorrect) Content Content/Format • Added 9 ns references to entire document • Updated format • Added Pb-free information for TQFP package 71024_r1_03; 71024_r1_04 71024_r1_04; 71024_r1_05 Rev: 1.05 11/2004 13/13 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.