GS71208TP

GS71208TP TSOP Commercial Temp Industrial Temp Features • Fast access time: 8 ns • CMOS low power operation: 150 mA at minimum cycle time • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up TP: 400 mil, 32-pin TSOP Type II package 128K x 8 1Mb Asynchronous SRAM A3 A2 A1 A0 CE DQ1 DQ2 VDD VSS DQ3 DQ4 WE A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8 ns 3.3 V VDD Center VDD and VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A4 A5 A6 A7 OE DQ8 DQ7 VSS VDD DQ6 DQ5 A8 A9 A10 A11 A12 TSOP-II 128K x 8-Pin Configuration 32-pin 400 mil TSOP II Description The GS71208 is a high speed CMOS Static RAM organized as 131,072 words by 8 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTL-compatible. The GS71208 is available in a 400 mil TSOP Type-II package. Pin Descriptions Symbol A0–A16 DQ1–DQ8 CE WE OE VDD VSS NC Description Address input Data input/output Chip enable input Write enable input Output enable input +3.3 V power supply Ground No connect Rev: 1.03 10/2001 1/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Block Diagram A0 Address Input Buffer Row Decoder Memory Array A16 CE WE OE Column Decoder Control I/O Buffer DQ1 DQ8 Truth Table CE H L L L Note: X: “H” or “L” OE X L X H WE X H L H DQ1 to DQ8 Not Selected Read Write High Z VDD Current ISB1, ISB2 IDD Rev: 1.03 10/2001 2/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature Symbol VDD VIN VOUT PD TSTG Rating –0.5 to +4.6 –0.5 to VDD +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) 0.7 –55 to 150 Unit V V V W o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range Symbol VDD VIH VIL TAc T AI Min 3.135 2.0 –0.3 0 –40 Typ 3.3 — — — — Max 3.6 VDD +0.3 0.8 70 85 Unit V V V oC o C Note: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Capacitance Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = 0 V VOUT = 0 V Max 5 7 Unit pF pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. Rev: 1.03 10/2001 3/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP DC I/O Pin Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol IIL ILO VOH VOL Test Conditions VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = –4mA ILO = +4mA Min –1 uA –1 uA 2.4 — Max 1 uA 1 uA — 0.4 V Power Supply Currents 0 to 70°C Parameter Symbol Test Conditions 8 ns CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time CE ≥ VDD – 0.2 V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V 8 ns –40 to 85°C Operating Supply Current IDD (max) 150 mA 160 mA Standby Current ISB1 (max) 55 mA 65 mA Standby Current ISB2 (max) 15 mA 25 mA Rev: 1.03 10/2001 4/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP AC Test Conditions Parameter Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load Conditions VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2 Output Load 1 DQ 50Ω VT = 1.4 V 30pF1 Output Load 2 3.3 V DQ 5pF1 589Ω 434Ω Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ AC Characteristics Read Cycle Parameter Read cycle time Address access time Chip enable access time (CE) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) * These parameters are sampled and are not 100% tested Symbol tRC tAA tAC tOE tOH tLZ* tOLZ* tHZ* tOHZ* -8 Min 8 — — — 3 3 0 — — Max — 8 8 3.5 — — — 4 3.5 Unit ns ns ns ns ns ns ns ns ns Rev: 1.03 10/2001 5/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA tOH Data Out Previous Data Data valid Read Cycle 2: WE = VIH tRC Address tAA CE tAC tLZ OE tOE Data Out tOLZ High impedance DATA VALID tHZ tOHZ Rev: 1.03 10/2001 6/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Write Cycle Parameter Write cycle time Address valid to end of write Chip enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z * These parameters are sampled and are not 100% tested Symbol tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ* -8 Min 8 5.5 5.5 4 0 5.5 0 0 0 3 — Max — — — — — — — — — — 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns Rev: 1.03 10/2001 7/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Write Cycle 1: WE control tWC Address tAW OE tCW CE tAS WE tDW Data In tWHZ Data Out HIGH IMPEDANCE DATA VALID tWR tWP tDH tWLZ Write Cycle 2: CE control tWC Address tAW OE tAS CE tWP WE tDW Data In Data Out DATA VALID tWR1 tCW tDH HIGH IMPEDANCE Rev: 1.03 10/2001 8/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP 32-Pin TSOP-II, 400mil D Dimension in inch Symbol A A1 E1 E A 32 c Dimension in mm min — 0.01 0.90 0.30 0.12 20.82 — 11.56 10.03 — 0.40 0.60 0.00 0o nom — — 1.02 0.40 0.13 20.95 0.95 11.76 10.16 1.27 0.50 0.80 — — max 1.27 0.15 1.14 0.45 0.16 21.08 — 11.96 10.29 — 0.60 1.00 0.76 5o min 0.039 0.002 0.037 0.012 0.0047 0.820 — 0.455 0.395 — 0.017 0.024 0.00 0o nom — — 0.040 0.016 0.0051 0.825 0.037 0.463 0.400 0.05 0.020 0.031 — — max 0.05 0.006 0.045 0.018 0.0062 0.830 — 0.471 0.405 — 0.023 0.039 0.003 5o A2 b c 1 ZD A2 A e b D ZD E E1 A1 y L1 L e L L1 y Q Detail A Q Note: 1.Dimension D includes mold flash, protrusions or gate burrs. 2. Dimension E does not include interlead flash. 3. Controlling dimension: mm Rev: 1.03 10/2001 9/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Ordering Information Part Number* GS71208TP-8 * Package 400 mil TSOP-II Access Time 8 ns Temp. Range Commercial Status Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS71208TP-8T Rev: 1.03 10/2001 10/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS71208TP Revision History Rev. Code: Old; New 1.00 12/1999/1.01 12/1999 GS71208Rev1.01 12/1999KRev 1.01 2/2000L 71208_r1_01; 71208_r1_02 71208_r1_02; 71208_r1_03 Types of Changes Format or Content Content Format/Content Format/Content Content 1. Page #/Revisions/Reason Added TP package to 71208 • GSI LogoAdded Dimension D to 32 pin 400 ml TSOP II Package. • Updated format to comply with Technical Publications standard • Specifically noted that numbers in Power Supply Currents table are worst case scenario • Removed all references to other parts except 71208TP-8 Rev: 1.03 10/2001 11/11 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.