GS74104TP-8I

GS74104TP/J SOJ, TSOP Commercial Temp Industrial Temp Features • Fast access time: 8, 10, 12, 15 ns • CMOS low power operation: 150/125/110/90 mA at minimum cycle time. • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • Package line up J: 400 mil, 32-pin SOJ package TP: 400 mil, 44-pin TSOP Type II package 1M x 4 4Mb Asynchronous SRAM SOJ 1M x 4-Pin Configuraton A4 A3 A2 A1 A0 CE DQ1 VDD VSS DQ2 WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8, 10, 12, 15 ns 3.3 V VDD Center VDD and VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin 400 mil SOJ Description The GS74104 is a high speed CMOS Static RAM organized as 1,048,576 words by 4 bits. Static design eliminates the need for external clocks or timing strobes. The GS operates on a single 3.3 V power supply and all inputs and outputs are TTL-compatible. The GS74104 is available in 400 mil SOJ and 400 mil TSOP Type-II packages. A5 A6 A7 A8 A9 OE DQ4 VSS VDD DQ3 A10 A11 A12 A13 A14 NC TSOP-II 1M x 4-Pin Configuration NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 NC NC NC A5 A6 A7 A8 A9 OE DQ4 VSS VDD DQ3 A10 A11 A12 A13 A14 NC NC NC NC NC NC A4 A3 A2 A1 A0 CE DQ1 VDD VSS DQ2 WE A19 A18 A17 A16 A15 NC NC NC Pin Descriptions Symbol A0–A19 DQ1–DQ4 CE WE OE VDD VSS NC Description Address input Data input/output Chip enable input Write enable input Output enable input +3.3 V power supply Ground No connect 44-pin 400 mil TSOP II 34 33 32 31 30 29 28 27 26 25 24 23 Rev: 1.07 1/2001 1/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Block Diagram A0 Address Input Buffer Row Decoder Memory Array A19 CE WE OE Column Decoder Control I/O Buffer DQ1 DQ4 Truth Table CE H L L L Note: X: “H” or “L” OE X L X H WE X H L H DQ1 to DQ8 Not Selected Read Write High Z VDD Current ISB1, ISB2 IDD Rev: 1.07 1/2001 2/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature Symbol VDD VIN VOUT PD TSTG Rating –0.5 to +4.6 –0.5 to VDD +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) 0.7 –55 to 150 Unit V V V W o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Supply Voltage for -10/12/15 Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range Symbol VDD VDD VIH VIL TAc T AI Min 3.0 3.135 2.0 –0.3 0 –40 Typ 3.3 3.3 — — — — Max 3.6 3.6 VDD +0.3 0.8 70 85 Unit V V V V oC o C Note: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Rev: 1.07 1/2001 3/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Capacitance Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = 0 V VOUT = 0 V Max 5 7 Unit pF pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. DC I/O Pin Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol IIL ILO VOH VOL Test Conditions VIN = 0 to VDD Output High Z VOUT = 0 to VDD IOH = –4mA ILO = +4mA Min – 1 uA –1 uA 2.4 — Max 1 uA 1 uA — 0.4 V Rev: 1.07 1/2001 4/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Power Supply Currents Parameter Symbol Test Conditions CE ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA CE ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time CE ≥ VDD - 0.2V All other inputs ≥ VDD - 0.2V or ≤ 0.2V 0 to 70°C 8 ns 10 ns 12 ns 15 ns 10 ns –40 to 85°C 12 ns 15 ns Operating Supply Current IDD (max) 150 mA 125 mA 110 mA 90 mA 135 mA 120 mA 100 mA Standby Current ISB1 (max) 70 mA 65 mA 60 mA 55 mA 75 mA 70 mA 65 mA Standby Current ISB2 (max) 30 mA 40 mA AC Test Conditions Parameter Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load Conditions VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2 Output Load 1 DQ 50Ω VT = 1.4 V 30pF1 Output Load 2 3.3 V DQ 5pF1 589Ω 434Ω Note: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ Rev: 1.07 1/2001 5/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J AC Characteristics Read Cycle Parameter Read cycle time Address access time Chip enable access time (CE) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) Symbol tRC tAA tAC tOE tOH tLZ* tOLZ* tHZ* tOHZ* -8 Min 8 — — — 3 3 0 — — -10 Max — 8 8 3.5 — — — 4 3.5 -12 Min 12 — — — 3 3 0 — — -15 Min 15 — — — 3 3 0 — — Min 10 — — — 3 3 0 — — Max — 10 10 4 — — — 5 4 Max — 12 12 5 — — — 6 5 Max — 15 15 6 — — --7 6 Unit ns ns ns ns ns ns ns ns ns * These parameters are sampled and are not 100% tested. Read Cycle 1: CE = OE = VIL, WE = VIH tRC Address tAA tOH Data Out Previous Data Data valid Rev: 1.07 1/2001 6/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Read Cycle 2: WE = VIH tRC Address tAA CE tAC tLZ OE tOE Data Out tOLZ High impedance DATA VALID tHZ tOHZ Write Cycle Parameter Write cycle time Address valid to end of write Chip enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z Symbol tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ* -8 Min 8 5.5 5.5 4 0 5.5 0 0 0 3 — -10 Max — — — — — — — — — — 3.5 -12 Min 12 8 8 6 0 8 0 0 0 3 — -15 Min 15 10 10 7 0 10 0 0 0 3 — Min 10 7 7 5 0 7 0 0 0 3 — Max — — — — — — — — — — 4 Max — — — — — — — — — — 5 Max — — — — — — — — — — 6 Unit ns ns ns ns ns ns ns ns ns ns ns * These parameters are sampled and are not 100% tested. Rev: 1.07 1/2001 7/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Write Cycle 1: WE control tWC Address tAW OE tCW CE tAS WE tDW Data In tWHZ Data Out HIGH IMPEDANCE DATA VALID tWR tWP tDH tWLZ Write Cycle 2: CE control tWC Address tAW OE tAS CE tWP WE tDW Data In Data Out DATA VALID tWR1 tCW tDH HIGH IMPEDANCE Rev: 1.07 1/2001 8/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J 32-Pin SOJ, 400 mil Dimension in inch Symbol D L c E HE GE A A1 A2 B B1 e A Dimension in mm min — 0.66 2.67 0.33 0.61 0.15 20.83 10.04 — 10.93 9.00 2.08 — 0 o min — 0.026 0.105 0.013 0.024 0.006 0.820 0.395 — 0.430 0.354 0.082 — 0 o nom — — 0.110 0.017 0.028 0.008 0.824 0.400 0.05 0.435 0.366 — — — max 0.146 — 0.115 0.021 0.032 0.012 0.829 0.405 — 0.440 0.378 — 0.004 10 o nom — — 2.80 0.43 0.71 0.20 20.93 10.16 1.27 11.05 9.30 — — — max 3.70 — 2.92 0.53 0.81 0.30 21.06 10.28 — 11.17 9.60 — 0.10 10o 1 c D E A A2 A1 y B B1 e HE Detail A Q GE L y Q Note: 1. Dimension D& E do not include interlead flash. 2. Dimension B1 does not include dambar protrusion/intrusion. 3. Controlling dimension: inches Rev: 1.07 1/2001 9/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J 44-Pin, 400 mil TSOP-II Dimension in inch 44 D 23 c Symbol A A1 HE A Dimension in mm min — 0.05 0.95 0.25 — 18.31 10.06 — 11.56 0.40 — — 0o nom — — 1.00 0.35 0.15 18.41 10.16 0.80 11.76 0.50 0.80 — — max 1.20 — 1.05 0.45 — 18.51 10.26 — 11.96 0.60 — 0.10 5o min — 0.002 0.037 0.01 — 0.721 0.396 — 0.455 0.016 — — 0o nom — — 0.039 0.014 0.006 0.725 0.400 0.031 0.463 0.020 0.031 — — max 0.047 — 0.041 0.018 — 0.729 0.404 — 0.471 0.024 — 0.004 5o A2 B c D E e HE L 1 A2 e 22 B A A1 y L1 L E L1 y Q Q Detail A Note: 1. Dimension D& E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm Rev: 1.07 1/2001 10/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Ordering Information Part Number* GS74104TP-8 GS74104TP-10 GS74104TP-12 GS74104TP-15 GS74104TP-8I GS74104TP-10I GS74104TP-12I GS74104TP-15I GS74104J-8 GS74104J-10 GS74104J-12 GS74104J-15 GS74104J-8I GS74104J-10I GS74104J-12I GS74104J-15I * Package 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil TSOP-II 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ 400 mil SOJ Access Time 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns 8 ns 10 ns 12 ns 15 ns Temp. Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Status Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74104TP-8T Rev: 1.07 1/2001 11/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74104TP/J Revision History Rev. Code: Old; New GS74104Rev1.05 1/2000K;Rev 6 2/2000L Types of Changes Format or Content Format/Content • GSI Logo Page #/Revisions/Reason 74104_r1_06; 74104_r1_07 Format • Updated format to comply with Technical Publications standard • Specifically noted that numbers in Power Supply Currents table are worst case scenario • Corrected package reference on page 9 (replaced 300 mil diagram with 400 mil diagram) Rev: 1.07 1/2001 12/12 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.