GS78116B BGA Commercial Temp Industrial Temp Features
• Fast access time: 10, 12, 15 ns • CMOS low power operation: 300/250/220/180 mA at minimum cycle time • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • 14 mm x 22 mm, 119-Bump, 1.27 mm Pitch Ball Grid Array package
512K x 16 8Mb Asynchronous SRAM
Pin Descriptions Symbol
A0 to A18 DQ1 to DQ16 CE WE OE VDD VSS NC
10, 12, 15 ns 3.3 V VDD
Description
Address input Data input/output Chip enable input Write enable input Output enable input +3.3 V power supply Ground No connect
Description
The GS78116 is a high speed CMOS static RAM organized as 524,288-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. The GS78116 operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS78116 is available in 14 mm x 22 mm BGA package.
Block Diagram
A0 Address Input Buffer
Row Decoder
Memory Array
A18 CE WE OE
Column Decoder
Control
I/O Buffer
DQ1
DQ16
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
1/11
© 1999, Giga Semiconductor, Inc.
GS78116B 512K x 16 Async SRAM in 119-Bump, 14 mm x 22 mm
Top View
1 A B C D E F G H J K L M N P R T U NC NC, VSS NC NC DQ1 DQ2 DQ3 DQ4 VDD DQ5 DQ6 DQ7 DQ8 NC NC NC NC 2 A15 A11 NC VDD NC VDD NC VDD VSS VDD NC VDD NC VDD NC A7 A3 3 A14 A10 VDD, NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A6 A2 4 A16 CE A17 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A18 WE OE 5 A13 A9 VSS, NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A5 A1 6 A12 A8 NC VDD NC VDD NC VDD VSS VDD NC VDD NC VDD NC A4 A0 7 NC NC NC NC DQ16 DQ15 DQ14 DQ13 VDD DQ12 DQ11 DQ10 DQ9 NC NC NC, VSS NC
Note: Bumps 1B, 7T, 3C, and 5C are actually NC’s but should be wired 3C = VDD and 1B, 7T and 5C = VSS to assure compatibility with future versions.
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
2/11
© 1999, Giga Semiconductor, Inc.
GS78116B
Truth Table CE
H L L L Note: X: “H” or “L”
OE
X L X H
WE
X H L H
DQ1 to DQ8
Not Selected Read Write High Z
VDD Current
ISB1, ISB2
IDD
Absolute Maximum Ratings
Parameter
Supply Voltage Input Voltage Output Voltage Allowable power dissipation Storage temperature
Symbol
VDD VIN VOUT PD TSTG
Rating
–0.5 to +4.6 –0.5 to VDD +0.5 (≤ 4.6 V max.) –0.5 to VDD+0.5 (≤ 4.6 V max.) 1.5 –55 to 150
Unit
V V V W
o
C
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage for -10/12/15 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
VDD VIH VIL TAc TAi
Min
3.0 2.0 –0.3 0 –40
Typ
3.3 — — — —
Max
3.6 VDD +0.3 0.8 70 85
Unit
V V V
oC oC
Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
3/11
© 1999, Giga Semiconductor, Inc.
GS78116B Capacitance
Parameter
Input Capacitance Output Capacitance
Symbol
CIN COUT
Test Condition
VIN = 0 V VOUT = 0 V
Max
10 7
Unit
pF pF
Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL IOL VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z, VOUT = 0 to VDD IOH = –4 mA IOL = +4 mA
Min
–2 uA –1 uA 2.4
Max
2 uA 1 uA
0.4 V
Power Supply Currents Parameter Symbol Test Conditions
E ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA E ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time E ≥ VDD – 0.2V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V
0 to 70°C 10 ns 12 ns 15 ns 10 ns
–40 to 85°C 12 ns 15 ns
Operating Supply Current
IDD
225 mA
220 mA
180 mA
270 mA
240 mA
200 mA
Standby Current
ISB1
130 mA
120 mA
110 mA
150 mA
140 mA
130 mA
Standby Current
ISB2
60 mA
80 mA
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
4/11
© 1999, Giga Semiconductor, Inc.
GS78116B AC Test Conditions
Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH = 2.4 V VIL = 0.4 V tr = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2
Output Load 1
DQ 50Ω VT = 1.4 V 30pF1
Output Load 2
3.3 V DQ 5pF1 589Ω 434Ω
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ.
AC Characteristics
Read Cycle Parameter
Read cycle time Address access time Chip enable access time (CE) Output enable to output valid (OE) Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in High Z (CE) Output disable to output in High Z (OE)
Symbol
tRC tAA tAC tOE tOH tLZ* tOLZ* tHZ* tOHZ*
-10 Min
10 — — — 3 3 0 — —
-12 Min
12 — — — 3 3 0 — —
-15 Min
15 — — — 3 3 0 — —
Max
— 10 10 4 — — — 5 4
Max
— 12 12 5 — — — 6 5
Max
— 15 15 6 — — — 7 6
Unit
ns ns ns ns ns ns ns ns ns
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
5/11
© 1999, Giga Semiconductor, Inc.
GS78116B
Read Cycle 1:CE = OE = VIL
tRC Address tAA tOH Data Out Previous Data Data valid
Read Cycle 2: WE = VIH
tRC Address tAA CE tAC tLZ OE tOLZ High impedance tOE
Data valid
tHZ
tOHZ
Data Out
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
6/11
© 1999, Giga Semiconductor, Inc.
GS78116B
Write Cycle Parameter
Write cycle time Address valid to end of write Chip enable to end of write Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time (CE) Output Low Z from end of write Write to output in High Z
Symbol
tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ*
-10 Min
10 7 7 5 0 7 0 0 0 3 —
-12 Min
12 8 8 6 0 8 0 0 0 3 —
-15 Min
15 10 10 7 0 10 0 0 0 3 —
Max
— — — — — — — — — — 4
Max
— — — — — — — — — — 5
Max
— — — — — — — — — — 6
Unit
ns ns ns ns ns ns ns ns ns ns ns
* These parameters are sampled and are not 100% tested.
Write Cycle 1: WE Controlled
tWC Address tAW OE tCW CE tAS WE tDW Data In tWHZ Data Out
High impedance Data valid
tWR
tWP tDH tWLZ
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
7/11
© 1999, Giga Semiconductor, Inc.
GS78116B
Write Cycle 2: CE Controlled
tWC Address tAW OE tAS CE WE tWP tDW Data In Data Out
Data valid
tWR1 tCW
tDH
High impedance
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
8/11
© 1999, Giga Semiconductor, Inc.
GS78116B Package Dimensions - 119-Pin PBGA
Pin 1 Corner
A
7654321
G
P
B
S
D
A B C D E F G H J K L M N P R T U
N
Top View
R Bottom View
Package Dimensions - 119 Pin PBGA
Symbol A B C D E F G K N P R S T Unit: mm Description Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Cut-out Package Width Foot Length Width of package between balls Length of package between balls Variance of Ball Height Min. 13.8 21.8 — 0.60 0.50 — — 0.80 — — — — — Nom. 14.0 22.0 — 0.75 0.60 1.46 1.27 0.90 12.00 19.50 7.62 20.32 0.15 Max 14.2 22.2 2.40 0.90 0.70 1.70 — 1.00 — — — — —
T F
Side View
C
E
K
BPR 1999.05.18
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
9/11
© 1999, Giga Semiconductor, Inc.
GS78116B
Ordering Information Part Number*
GS78116B-10 GS78116B-12 GS78116B-15 GS78116B-10I GS78116B-12I GS78116B-15I
Package
BGA BGA BGA BGA BGA BGA
Access Time
10 ns 12 ns 15 ns 10 ns 12 ns 15 ns
Temp. Range
Commercial Commercial Commercial Industrial Industrial Industrial
Status
* Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS78116B-12T
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
10/11
© 1999, Giga Semiconductor, Inc.
GS78116B
Asynchronous SRAM Datasheet Revision History Rev. Code: Old; New
GS78116Rev0.01a 5/1999; 1.00 X/1999 GS78116Rev 1.0010/1999A;Rev 1.01 2/2000FormatB Rev 1.01 2/2000FormatB; 78116_r1_02 Format/Content
Types of Changes Format or Content
Format/Typos Content
Page #/Revisions/Reason
• p.2/Changed E to CE/consistency. • p.2/Changed Pin T1 from BA to BD/Correction • Added GSI Logo • Updated format to comply with Technical Publication standards • Finalized document and removed preliminary references
Rev: 1.02 9/2001
For latest documentation see http://www.gsitechnology.com.
11/11
© 1999, Giga Semiconductor, Inc.
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