GS816018T-250

Preliminary GS816018/32/36T-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2.5 2.7 3.0 3.4 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.7 7.5 ns 280 330 275 320 5.5 5.5 175 200 175 200 255 300 250 295 6.0 6.0 165 190 165 190 230 270 230 265 6.5 6.5 160 180 160 180 200 230 195 225 7.0 7.0 150 170 150 170 185 215 180 210 7.5 7.5 145 165 145 165 165 190 165 185 8.5 8.5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816018/32/36T operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Functional Description Applications The GS816018/32/36T is an 18,874,368-bit (16,777,216-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst Rev: 2.12 3/2002 1/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 GS816018 100-Pin TQFP Pinout NC NC NC VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 NC NC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9 A19 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC Rev: 2.12 3/2002 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. A3 A2 A1 A0 NC NC VSS V DD A18 A17 A10 A11 A12 A13 A14 A15 A16 2/28 © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 GS816032 100-Pin TQFP Pinout NC DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9 NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC Rev: 2.12 3/2002 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. A3 A2 A1 A0 NC NC VSS V DD A18 A17 A10 A11 A12 A13 A14 A15 A16 3/28 © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 GS816036 100-Pin TQFP Pinout DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 BD BC BB BA E3 V DD VSS CK GW BW G A DS C A DS P A DV A8 A9 DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 Rev: 2.12 3/2002 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. A3 A2 A1 A0 NC NC VSS V DD A18 A17 A10 A11 A12 A13 A14 A15 A16 4/28 © 1999, Giga Semiconductor, Inc. Preliminary GS816018/32/36T-250/225/200/166/150/133 TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42 80 63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29 51, 80, 1, 30 51, 80, 1, 30 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57 75, 78, 79, 95, 96, 1, 2, 3, 6, 7, 25, 28, 29, 30 87 93, 94 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 16, 38, 39, 66 Symbol A0, A1 A2–A18 A19 DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 DQA9, DQB9, DQC9, DQD9 NC DQA1–DQA9 DQB1–DQB9 NC BW BA, BB BC, BD CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC Type I I I I/O Description Address field LSBs and Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input and Output pins (x32, x36 Version) I/O Data Input and Output pins (x36 Version) No Connect (x32 Version) I/O Data Input and Output pins (x18 Version) — I I I I I I I I I I I I I I I I — No Connect (x18 Version) Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low (x32, x36 Version) Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect Rev: 2.12 3/2002 5/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 GS816018/32/36 Block Diagram Register A0–An D Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1 LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q Register E1 E2 E3 D Q Register D Q FT G Power Down Control ZZ 1 DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 2.12 3/2002 6/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name LBO FT ZZ State L H L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 01 10 11 00 10 11 00 01 11 00 01 10 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 2.12 3/2002 7/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 2.12 3/2002 8/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X H E2 X F F T T T X X X X X X X X ADSP ADSC X L H L H H H X H X H X H X L X L X L L H H H H H H H H ADV X X X X X X L L L L H H H H W3 X X X X F T F F T T F F T T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 2.12 3/2002 9/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 2.12 3/2002 10/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 2.12 3/2002 11/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to 4.6 –0.5 to 6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V V mA mA W o o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 2.12 3/2002 12/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 VDDQ3 VDDQ2 Min. 3.0 2.3 3.0 2.3 Typ. 3.3 2.5 3.3 2.5 Max. 3.6 2.7 3.6 2.7 Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 2.0 –0.3 2.0 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 0.6*VDD –0.3 0.6*VDD –0.3 Typ. — — — — Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 2.12 3/2002 13/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing VIH Overshoot Measurement and Timing 20% tKC VDD + 2.0 V VSS 50% VSS – 2.0 V 20% tKC 50% VDD VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF Package Thermal Characteristics Rating Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Layer Board single four Symbol RΘJA RΘJA Max 40 24 Unit °C/W °C/W Notes 1,2 1,2 RΘJC Junction to Case (TOP) — 9 °C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 2.12 3/2002 14/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA –1 uA –1 uA –100 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V Rev: 2.12 3/2002 15/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Operating Currents - 250 Mo d e Symbol 0 to 70°C Unit 290 40 180 20 260 20 165 10 290 30 180 20 260 15 165 10 20 20 85 60 90 65 30 20 80 60 30 20 30 30 85 65 175 10 155 10 165 10 150 10 20 20 75 50 270 15 235 15 245 15 215 15 225 15 160 10 30 30 80 55 190 20 170 20 180 20 165 15 175 15 155 15 185 10 140 10 20 20 64 50 300 30 265 30 275 30 240 25 250 25 205 20 215 20 165 15 195 10 150 10 30 30 70 55 175 10 155 10 165 10 150 10 160 10 140 10 150 10 135 10 190 20 150 15 170 10 135 10 20 20 60 50 270 20 235 20 245 20 215 15 225 15 185 15 195 15 170 15 180 15 145 10 200 20 160 15 180 10 145 10 30 30 65 55 190 20 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 155 10 125 10 170 15 140 10 155 10 125 10 20 20 50 45 300 40 265 35 275 35 240 30 250 30 205 25 215 25 190 25 200 25 170 20 180 20 150 10 165 10 135 10 180 15 150 10 165 10 135 10 30 30 55 50 mA mA mA mA mA mA mA mA mA mA mA mA - 225 0 to 70° C –40 to 85° C 0 to 70° C – 40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85° C -200 - 166 - 150 - 133 Rev: 2.12 3/2002 –40 to 85°C (x32/ x36) Flow T hr ough Pipeline (x18) Flow T hr ough IDDQ ID D IDDQ ID D IDDQ ID D IDDQ ID D IDDQ IS B IS B ID D ID D Pipeline Flow T hr ough Pipeline (x18) Flow T hr ough Pipeline — Flow T hr ough Pipeline — Flow T hr ough ID D ID D IDDQ ID D IDDQ Pipeline ID D IDDQ (x32/ x36) Parameter Test Conditions Operating Current 3 .3 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open 16/28 Operating Current 2 .5 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Standby Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Preliminary GS816018/32/36T-250/225/200/166/150/133 © 1999, Giga Semiconductor, Inc. Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Preliminary GS816018/32/36T-250/225/200/166/150/133 AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR 1 -250 Min 4.0 — 1.5 1.5 1.2 0.2 5.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 2.5 — — — — — 5.5 — — — — — — 2.3 2.3 — 2.3 — — — -225 Min 4.4 — 1.5 1.5 1.3 0.3 6.0 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 2.7 — — — — — 6.0 — — — — — — 2.5 2.5 — 2.5 — — — -200 Min 5.0 — 1.5 1.5 1.4 0.4 6.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 3.0 — — — — — 6.5 — — — — — — 3.0 3.2 — 3.0 — — — -166 Min 6.0 — 1.5 1.5 1.5 0.5 7.0 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 3.4 — — — — — 7.0 — — — — — — 3.0 3.5 — 3.0 — — — -150 Min 6.7 — 1.5 1.5 1.5 0.5 7.5 — 3.0 3.0 1.5 0.5 1.5 1.7 1.5 — 0 — 5 1 20 Max — 3.8 — — — — — 7.5 — — — — — — 3.0 3.8 — 3.0 — — — -133 Min 7.5 — 1.5 1.5 1.5 0.5 8.5 — 3.0 3.0 1.5 0.5 1.7 2 1.5 — 0 — 5 1 20 Max — 4.0 — — — — — 8.5 — — — — — — 3.0 4.0 — 3.0 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 2.12 3/2002 17/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Write Cycle Timing Single Write Burst Write Write Deselected CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH ADV must be inactive for ADSP Write WR2 WR3 A0–An GW WR1 tS tH tS tH BW tS tH BA–BD tS tH WR1 WR1 WR2 WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 tS tH E2 and E3 only sampled with ADSP or ADSC E3 G tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D D2A D2B D2C D2D D3A DQA–DQD Hi-Z D1A Rev: 2.12 3/2002 18/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Flow Through Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An GW RD1 tS RD2 RD3 tH tS tH BW BA–BB tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE tOHZ G tOLZ tKQX Q1A tLZ tKQ tHZ Q2A Q2B Q2c Q2D Q3A tKQX DQA–DQD Hi-Z Rev: 2.12 3/2002 19/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Flow Through Read-Write Cycle Timing Single Read Single Write Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An GW RD1 WR1 RD2 tS tH tS tS tH BW BA–BD tS tH tS WR1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 tOHZ E3 tOE G tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A DQA–DQD Hi-Z D1A Burst wrap around to it’s initial state Rev: 2.12 3/2002 20/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Pipelined SCD Read Cycle Timing Single Read Burst Read tKH tKL tKC tS tH ADSC initiated read ADSP is blocked by E inactive CK tS tH ADSP ADSC tS tH Suspend Burst ADV tS tH A0–An GW RD1 tS RD2 RD3 tH tS tH BW BWA–BWD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE G DQA–DQD Hi-Z tOLZ Q1A tLZ tOHZ tKQX Q2A Q2B Q2c Q2D tKQX Q3A tHZ tKQ Rev: 2.12 3/2002 21/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Pipelined SCD Read-Write Cycle Timing Single Read tKL Single Write Burst Read CK tS tH tKH tKC tS tH ADSP is blocked by E inactive ADSP ADSC initiated read ADSC tS tH ADV tS tH A0–An GW RD1 WR1 RD2 tS tH tS tH BW tS tH BWA–BWD tS tH WR1 E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G DQA–DQD Hi-Z tKQ Q1A tS tH D1A Q2A Q2Bb Q2c Q2D Rev: 2.12 3/2002 22/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram ~ ~~~~ ~ ~ ~~~~ ~ CK tS tH tKC tKH tKL ADSP ADSC tZZS ~~ ~~ tZZH ~ ~ tZZR ZZ Snooze Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 2.12 3/2002 23/28 ~~ ~~ © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 TQFP Package Drawing L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c P in 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — 0.45 — 0.10 1.40 0.30 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 0.75 — 0.10 L1 D D1 e b A1 Y A2 0° — 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 2.12 3/2002 24/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs Org 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 512K x 32 Part Number1 GS816018T-250 GS816018T-225 GS816018T-200 GS816018T-166 GS816018T-150 GS816018T-133 GS816032T-250 GS816032T-225 GS816032T-200 GS816032T-166 GS816032T-150 GS816032T-133 GS816036T-250 GS816036T-225 GS816036T-200 GS816036T-166 GS816036T-150 GS816036T-133 GS816018T-250I GS816018T-225I GS816018T-200I GS816018T-166I GS816018T-150I GS816018T-133I GS816032T-250I GS816032T-225I GS816032T-200I GS816032T-166I GS816032T-150I GS816032T-133I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Speed2 (MHz/ns) 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 TA3 C C C C C C C C C C C C C C C C C C I I I I I I I I I I I I Status Not Available Not Available Not Available Not Available Not Available Not Available Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 2.12 3/2002 25/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 Org 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 Part Number1 GS816036T-250I GS816036T-225I GS816036T-200I GS816036T-166I GS816036T-150I GS816036T-133I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP Speed2 (MHz/ns) 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 TA3 I I I I I I Status Not Available Not Available Not Available Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018T-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 2.12 3/2002 26/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New GS816018T-150IT 1.00 9/ 1999A;GS816018T-150IT 2.00 1/1999B GS816018T- 2.00 11/ 1999B;GS816018T 2.01 1/ 2000C GS816018T 2.01 1/ 2000C;GS816018 T 2.02 1/ 2000D Types of Changes Format or Content Content Page;Revisions;Reason • Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B • Added x72 Pinout. • Added GSI Logo. • Changed Flow-Through Read-Write cycle Timing Diagram for accuracy • Changed pin description in TQFP to match order of pins in pinout. • Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Core and Interface voltages - Changed paragraph to include information for 3.3V;Completeness • Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. • Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness • Electrical Characteristics - Added second Output High Voltage line to table; completeness. • Note: There was not a Rev 2.02 for the 8160Z or the 8161Z. Format GS18/362.0 1/2000DGS18/ 362.03 2/2000E GS18/362.03 2/2000E; 816018_r2_04 816018_r2_04; 816018_r2_05 Content Content • Input High Voltage (p. 11) changed to 0.7* VDD • Input Low Voltage (p.11) changed to 0.3* VDD • Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 15 from 20 ns to 100 ns • Added 225 MHz speed bin • Updated Pg. 1 table, AC Characteristics table, and Operating Currents table to match 815xxx • Updated format to comply with Technical Publications standards • Updated Capitance table—removed Input row and changed Output row to I/O • Updated Features list on page 1 • Completely reworked table on page 1 • Updated Mode Pin Functions tableon page 7 • Added 3.3 V references to entire document • Updated Operating Conditions table • Added Pin 56 to Pin Description table • Updated Operating Currents table and added note • Updated Application Tips paragraph • Updated table on page 1; added power numbers 27/28 © 1999, Giga Semiconductor, Inc. 816018_r2_05; 816018_r2_06 Content/Format 816018_r2_06; 816018_r2_07 816018_r2_07; 816018_r2_08 Content Content 816018_r2_08; 816018_r2_09 Content Rev: 2.12 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816018/32/36T-250/225/200/166/150/133 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 816018_r2_09; 816018_r2_10 Types of Changes Format or Content Content Page;Revisions;Reason • Updated Operating Currents table • Updated table on page 1; updated power numbers • Updated Recommended Operating Conditions table (added VDDQ references) • Updated table on page 1 • Created recommended operating conditions tables on pages 12 and 13 • Updated AC Electrical Characteristics table • Added Sleep mode description on page 23 • Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) • Added 250 MHz speed bin • Deleted 180 MHz speed bin • Updated AC Characteristics table • Updated FT power numbers • Updated Mb references from 16Mb to 18Mb • Updated AC Test Conditions table and removed Output Load 2 diagram 816018_r2_10; 816018_r2_11 Content 816018_r2_11; 816018_r2_12 Content Rev: 2.12 3/2002 28/28 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.