GS816118CD-250T

Preliminary GS816118/36CD-333/300/250 165-Bump BGA Commercial Temp Industrial Temp Features • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 165-bump BGA package 1M x 18 and 512K x 36 18Mb Sync Burst SRAMs 333 MHz–250 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS816118/36CD is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816118/36CD operates on a 1.8 V power supply. All input are 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V compatible. Functional Description Applications The GS816118/36CD is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Parameter Synopsis -333 Pipeline 3-1-1-1 tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) 2.5 3.0 375 435 4.5 4.5 280 335 -300 2.5 3.3 335 390 5.0 5.0 230 270 -250 2.5 4.0 280 330 5.5 5.5 210 240 Unit ns ns mA mA ns ns mA mA Flow Through 2-1-1-1 Rev: 1.00 9/2004 1/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 165 Bump BGA—x18 Commom I/O—Top View (Package D) 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQPB NC LBO 2 A A NC DQB DQB DQB DQB MCL NC NC NC NC NC NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A A B C D E F G H J K L M N P R 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.00 9/2004 2/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 165 Bump BGA—x36 Common I/O—Top View (Package D) 1 A B C D E F G H J K L M N P R NC NC DQPC DQC DQC DQC DQC FT DQD DQD DQD DQD DQPD NC LBO 2 A A NC DQC DQC DQC DQC MCL DQD DQD DQD DQD NC NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A A B C D E F G H J K L M N P R 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch Rev: 1.00 9/2004 3/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 GS816118/36CD 165-Bump BGA Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD BA , BB , BC , BD NC CK BW GW E1 E3 E2 G ADV ADSC, ADSP ZZ FT LBO TMS TDI TDO TCK MCL VDD VSS VDDQ Type I I I/O I — I I I I I I I I I I I I I I O I — I I I Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low No Connect Clock Input Signal; active high Byte Write—Writes all enabled bytes; active low Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active l0w Address Strobe (Processor, Cache Controller); active low Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply Rev: 1.00 9/2004 4/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 GS816118/36C Block Diagram Register A0–An D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q 36 D 36 Register D BB Q 4 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q 36 36 E1 Register D Q 36 Register D Q FT G Power Down Control 36 ZZ 1 DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.00 9/2004 5/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name LBO FT ZZ State L H L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 1st address 2nd address 3rd address 4th address Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.00 9/2004 6/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x36 version. Rev: 1.00 9/2004 7/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Synchronous Truth Table Operation Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None External External External Next Next Next Next Current Current Current State Diagram Key5 X R R W CR CR CW CW E1 H L L L X H X H X H X ADSP X L H H H X H X H X H ADSC L X L L H H H H H H H ADV X X X X L L L L H H H W3 X X F T F F T T F F T DQ4 High-Z Q Q D Q Q D D Q Q D Write Cycle, Suspend Burst Current H X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 9/2004 8/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.00 9/2004 9/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.00 9/2004 10/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V mA mA W oC oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 VDDQ3 VDDQ2 Min. 3.0 2.3 3.0 2.3 Typ. 3.3 2.5 3.3 2.5 Max. 3.6 2.7 3.6 2.7 Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00 9/2004 11/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 2.0 –0.3 2.0 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 0.6*VDD –0.3 0.6*VDD –0.3 Typ. — — — — Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.00 9/2004 12/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Undershoot Measurement and Timing VIH VDD + 2.0 V VSS 50% VSS – 2.0 V 50% tKC VIL 50% VDD Overshoot Measurement and Timing 50% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* Rev: 1.00 9/2004 13/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA –1 uA –1 uA –100 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V Rev: 1.00 9/2004 14/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Operating Currents -333 Parameter Test Conditions Mode Symbol 0 to 70°C 385 50 300 35 345 30 260 20 40 40 85 60 -300 –40 to 85°C 395 50 310 35 355 30 270 20 50 50 90 65 -250 –40 to 85°C 355 45 250 30 320 25 225 15 50 50 90 65 0 to °C 345 45 240 30 310 25 215 15 40 40 85 60 0 to 70°C 290 40 220 20 260 20 200 10 40 40 85 60 –40 to 85°C 300 40 230 20 270 20 210 10 50 50 90 65 Unit Pipeline (x36) Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open (x18) Flow Through Standby Current Deselect Current ZZ ≥ VDD – 0.2 V Device Deselected; All other inputs ≥ VIH or ≤ VIL Pipeline Flow Through Pipeline — Flow Through Flow Through Pipeline IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB ISB IDD IDD mA mA mA mA mA mA mA mA — Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Rev: 1.00 9/2004 15/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR -333 Min 3.0 — 1.5 1.5 1.0 0.1 4.5 — 2.0 2.0 1.3 0.3 1.0 1.2 1.5 — 0 — 5 1 20 Max — 2.5 — — — — — 4.5 — — — — — — 2.5 2.5 — 2.5 — — — Min 3.3 — 1.5 1.5 1.0 0.1 5.0 — 2.0 2.0 1.4 0.4 1.0 1.2 1.5 — 0 — 5 1 20 -300 Max — 2.5 — — — — — 5.0 — — — — — — 2.5 2.5 — 2.5 — — — Min 4.0 — 1.5 1.5 1.2 0.2 5.5 — 2.0 2.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 -250 Max — 2.5 — — — — — 5.5 — — — — — — 2.5 2.5 — 2.5 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Pipeline Flow Through Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00 9/2004 16/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Pipeline Mode Timing Begin Read A Cont Cont Deselect Write B Single Write tKL tKH tKC Read C Read C+1 Read C+2 Read C+3 Cont Burst Read Deselect Single Read CK ADSP tS tH ADSC tS ADV tS tH A0–An A B C ADSC initiated read tH tS GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa–DQd tOHZ Q(A) D(B) E2 and E3 only sampled with ADSP and ADSC E1 masks ADSP Deselected with E1 tH tKQ tH tLZ Q(C) Q(C+1) Q(C+2) tKQX tHZ Q(C+3) Rev: 1.00 9/2004 17/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Flow Through Mode Timing Begin Read A Cont tKL tKH Cont tKC Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect CK ADSP tS tH ADSC tS tH ADV tS tH A0–An A B C Fixed High tS tH ADSC initiated read tS tH GW tS tH BW tS tH Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tH tS tOE DQa–DQd Q(A) Deselected with E1 E2 and E3 only sampled with ADSC tOHZ D(B) tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) tHZ tKQX Rev: 1.00 9/2004 18/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.00 9/2004 19/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.00 9/2004 20/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 JTAG TAP Block Diagram · · · 108 · · · · · · · · 1 Boundary Scan Register 0 Bypass Register 210 0 Instruction Register TDI ID Code Register 31 30 29 TDO · ··· 210 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents Die Revision Code Bit # x36 x18 GSI Technology JEDEC Vendor ID Code Presence Register 0 1 1 Not Used I/O Configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 011011001 0 011011001 Rev: 1.00 9/2004 21/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.00 9/2004 22/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.00 9/2004 23/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU Code 000 001 010 011 100 101 110 Description Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 1 1 1 1 1 BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.00 9/2004 24/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 2.0 –0.3 0.6 * VDD2 –0.3 –300 –1 –1 1.7 — VDDQ – 100 mV — Max. VDD3 +0.3 0.8 VDD2 +0.3 0.3 * VDD2 1 100 1 — 0.4 — 100 mV Unit Notes V V V V uA uA uA V V V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9 Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions VDD – 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ JTAG Port AC Test Load 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.00 9/2004 25/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 JTAG Port Timing Diagram tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 — 20 20 10 10 Max — 20 — — — — Unit ns ns ns ns ns ns Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.00 9/2004 26/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Package Dimensions—165-Bump FPBGA (Package D; Variation 3) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.44~0.64 (165x) A1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 10.0 1.0 15±0.05 14.0 A 0.53 REF 0.35 C 1.0 1.0 0.20 C B 0.20(4x) 13±0.05 Rev: 1.00 9/2004 0.36~0.46 1.40 MAX. 0.36 REF C SEATING PLANE 27/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 Ordering Information for GSI Synchronous Burst RAMs Org 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 Part Number1 GS816118CD-333 GS816118CD-300 GS816118CD-250 GS816136CD-333 GS816136CD-300 GS816136CD-250 GS816118CD-333I GS816118CD-300I GS816118CD-250I GS816136CD-333I GS816136CD-300I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) 165 BGA (var. 3) Speed2 (MHz/ns) 333/4.5 300/5 250/5.5 333/4.5 300/5 250/5.5 333/4.5 300/5 250/5.5 333/4.5 300/5 TA3 C C C C C C I I I I I Status 512K x 36 GS816136CD-250I Pipeline/Flow Through 165 BGA (var. 3) 250/5.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816118CD-250IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 9/2004 28/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS816118/36CD-333/300/250 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 8161xxC_r1 Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet Rev: 1.00 9/2004 29/29 © 2004, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.