GS816272C-200I

GS816218(B/D)/GS816236(B/D)/GS816272(C) 119-, 165-, & 209-Bump BGA Commercial Temp Industrial Temp Features 1M x 18, 512K x 36, 256K x 72 18Mb Sync Burst SRAMs 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Functional Description Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. ica ti o n sp ec if x3 6 pa Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the rt s in th is Parameter Synopsis -250 tKQ tCycle Curr (x18) Curr (x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x36) Curr (x72) 2.5 4.0 280 330 n/a 5.5 5.5 175 200 n/a ar eN ot Applications The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. x1 8a nd -225 2.7 4.4 255 300 n/a 6.0 6.0 165 190 n/a Re co m -200 3.0 5.0 230 270 350 6.5 6.5 160 180 225 m -166 3.4 6.0 200 230 300 7.0 7.0 150 170 115 en d ed • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119-, 165-, and 209-bump BGA package SCD and DCD Pipelined Reads The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. -150 3.8 6.7 185 215 270 7.5 7.5 145 165 210 fo rN ew -133 4.0 7.5 165 190 245 8.5 8.5 135 150 185 Pipeline 3-1-1-1 3.3 V Th e Flow Through 2-1-1-1 3.3 V Rev: 2.17 11/2004 1/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n Unit ns ns mA mA mA ns ns mA mA mA Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816272 Pad Out—209 Bump BGA—Top View (Package C) 1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD 2 DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQH DQH DQH DQH DQPH DQD DQD DQD DQD 3 A BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS 5 ADSP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT 7 ADV A NC GW VDD VSS VDD VSS 8 E3 BB BE NC VDDQ VSS 9 A BF BA 10 DQB 11 DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC DQA DQA DQA DQA DQPE DQE DQE DQE DQE fo rN ew VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK VSS ed en d VDDQ VSS Re co m VDD VSS m VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO ar eN ot VDD VSS VDD VSS VDD NC A A A MCL VDD VSS SCD ZZ VDD LBO A1 A1 A0 n VDDQ NC A1 A TDI ica ti o VDD NC A A A sp ec if is rt s in TMS th 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa 2/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n DQB DQB DQB DQP DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE DQE DQE DQE © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816272 BGA Pin Description Symbol A 0, A 1 An DQA DQB DQC DQD DQE DQF DQG DQH BA, BB, BC,BD, BE, BF, BG,BH NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCL BW ZQ TMS TDI TDO TCK VDD VSS I I Type I I Description Address field LSBs and Address Counter Preset Inputs. Address Inputs — I I I I I I I I I I I I No Connect Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high n Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect Low Byte Enable; active low sp ec if in th is pa rt s I I ica ti o Single Cycle Deselect/Dual Cycle Deselect Mode Control FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply x3 6 x1 8a nd O I I I I Rev: 2.17 11/2004 Th e VDDQ 3/41 ar eN ot Burst address counter advance enable; active low Re co m Clock Input Signal; active high Output Enable; active low m en d I Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low ed fo rN © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ew I/O Data Input and Output pins De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) 165-Bump BGA—x18 Commom I/O—Top View (Package D) 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQB NC LBO 2 A A NC DQB DQB DQB DQB MCL NC NC NC NC SCD NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC ZQ DQA DQA DQA DQA NC A A 11 A A De sig n NC DQA DQA DQA DQA DQA ZZ NC NC NC NC NC A A ew fo rN ed m en d Re co m ar eN ot n ica ti o sp ec if is in th TDI TMS pa Rev: 2.17 11/2004 Th e x1 8a nd x3 6 rt s 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch 4/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . B C D E F G H J K L M N P R GS816218(B/D)/GS816236(B/D)/GS816272(C) 165-Bump BGA—x36 Common I/O—Top View (Package D) 1 A B C D E F G H J K L M N P R NC NC DQC DQC DQC DQC DQC FT DQD DQD DQD DQD DQD NC LBO 2 A A NC DQC DQC DQC DQC MCL DQD DQD DQD DQD SCD NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BW GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADSC G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB ZQ DQA DQA DQA DQA NC A A 11 NC A De sig n NC DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA A A ew fo rN ed m en d Re co m ar eN ot n ica ti o sp ec if is in th TDI TMS pa Rev: 2.17 11/2004 Th e x1 8a nd x3 6 rt s 11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch 5/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . B C D E F G H J K L M N P R GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816236 Pad Out—119-Bump BGA—Top View (Package B) 1 A B C D E F G H J K L M N P R T VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD 2 A A A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC TMS 3 A A A VSS VSS VSS BC VSS NC 4 ADSP ADSC VDD ZQ E1 G 5 A A A VSS VSS VSS BB 6 7 VDDQ A DQB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC en d ed Re co m m ADV GW ar eN ot VSS NC VSS BA VSS VSS VSS FT A TDO VDD CK ica ti o n VSS BD VSS VSS VSS sp ec if SCD BW A1 A0 VDD A TCK VDDQ th is DQD DQD NC NC rt s in pa x3 6 LBO A TDI x1 8a nd U VDDQ Rev: 2.17 11/2004 Th e 6/41 fo rN NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA PE ZZ VDDQ ew © 1999, GSI Technology A NC Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816218 Pad Out—119-Bump BGA—Top View (Package B) 1 A B C D E F G H J K L M N VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB 2 A A A NC DQB NC DQB NC VDD DQB NC 3 A A A VSS VSS VSS BB VSS NC 4 ADSP ADSC VDD ZQ E1 G 5 A A A VSS VSS VSS NC 6 7 VDDQ A DQPA NC en d ed m ADV GW Re co m DQA NC DQA VDD NC DQA NC DQA NC A A NC ar eN ot VSS NC VSS BA VSS VSS VSS FT A TDO VDD CK ica ti o n VSS NC VDDQ sp ec if SCD BW A1 A0 VDD NC TCK DQB NC VSS VSS VSS LBO th is DQB NC NC NC R T pa rt s P in DQPB x3 6 x1 8a nd A TMS A TDI U VDDQ BPR1999.05.18 Rev: 2.17 11/2004 Th e 7/41 fo rN NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA PE ZZ VDDQ ew © 1999, GSI Technology A NC Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816218/36 BGA Pin Description Symbol A 0, A 1 An DQA DQB DQC DQD BA , BB , BC , BD NC CK BW GW E1 G ADV ADSP, ADSC ZZ FT LBO ZQ SCD TMS TDI TDO TCK PE VDD VSS VDDQ Type I I I/O I — I I I I I I I I I I I I I I O I I I I I Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins No Connect Clock Input Signal; active high Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep mode control; active high ica ti o FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Single Cycle Deselect/Dual Cyle Deselect Mode Control Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Parity Bit Enable; active low Core power supply I/O and Core Ground Output driver power supply Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th is sp ec if 8/41 n ar eN ot Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Re co m Output Enable; active low m Chip Enable; active low en d Global Write Enable—Writes all bytes; active low ed Byte Write—Writes all enabled bytes; active low fo rN Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ew Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816218/36 (PE = 0) Block Diagram Register A0–An D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A CK ADSC ADSP GW BW BA Register Q D BB Q Re co m Register m en d D Q 36 ed fo rN 4 Memory Array ew D 36 4 Register 4 36 LBO ADV Register BC Register ar eN ot D Q De sig n D 36 32 Parity Encode 4 Parity Compare A1 Register D Q D BD Q Register th is E1 sp ec if D Q ica ti o n 36 Register D Q 36 in Register x3 6 FT G pa rt s D Q 36 x1 8a nd ZZ Power Down Control SCD DQx1–DQx9 NC Q NC Note: Only x36 version shown for simplicity. Rev: 2.17 11/2004 Th e 9/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . Q D Register GS816218(B/D)/GS816236(B/D)/GS816272(C) GS816218/36 (PE = 1) x32 Mode Block Diagram Register A0–An D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A CK ADSC ADSP GW BW BA Register en d D Q 36 ed Q fo rN 4 Q LBO ADV Memory Array ew D 36 4 Parity Encode 32 D BB Q D BC Q ar eN ot Register Re co m Register m Register D Q Register Register ica ti o BD n D Q sp ec if D Q 32 36 Register 36 th E1 is Register D D Q 4 32 Register 32 Parity Encode 4 Parity Compare 32 in rt s Register D Q D Q x1 8a nd x3 6 FT G pa ZZ Power Down Control SCD DQx1–DQx8 De sig n Q Register A1 . D NC NC Note: Only x36 version shown for simplicity. Rev: 2.17 11/2004 Th e 10/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218(B/D)/GS816236(B/D)/GS816272(C) Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control 9th Bit Enable Pin Name LBO FT ZZ SCD ZQ PE State L H L H or NC L or NC H L H or NC L H or NC L H or NC Function Linear Burst Flow Through Pipeline Active Interleaved Burst m Note: There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 ica ti o n Linear Burst Sequence ar eN ot Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 is x3 6 pa rt s Note: The burst counter wraps to initial state on the 5th clock. th sp ec if 01 10 Note: The burst counter wraps to initial state on the 5th clock. in Re co m en d Deactivate DQPx I/Os (x16/x32 mode) ed High Drive (Low Impedance) Low Drive (High Impedance) Activate DQPx I/Os (x18/x36 mode) fo rN Standby, IDD = ISB Dual Cycle Deselect Single Cycle Deselect ew Rev: 2.17 11/2004 Th e x1 8a nd 11/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n BPR 1999.05.18 © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes GW H H H H H H H BW H L L L L L L BA X H L H H H L BB X H H L H H L BC X H H H L H L BD X H H H H L Notes 1 1 fo rN L Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o 12/41 n ar eN ot Re co m Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x36 version. m en d ed ew Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) Synchronous Truth Table Operation Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None External External External Next Next Next Next Current Current Current Current X R R W CR CR CW CW H L L L X H X H X X L H H H X H X L X L L X X X De sig n X X F T F F T T F F T T State Diagram Key5 E1 ADSP ADSC ADV W3 DQ4 High-Z Q Q D Q Q D D Q Q D D H H en d ed H Re co m m H H H H H H X H X ar eN ot H X H Notes: 1. X = Don’t Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o 13/41 n fo rN ew X L L L L H H H H © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . GS816218(B/D)/GS816236(B/D)/GS816272(C) Simplified State Diagram X Deselect W W Simple Synchronous Operation R R First Write CW First Read m en d X R CR ed Simple Burst Synchronous Operation sp ec if X ica ti o W ar eN ot Re co m R n R Burst Write Burst Read CR CR th is CW Rev: 2.17 11/2004 Th e x1 8a nd Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. x3 6 pa rt s in 14/41 fo rN X CR X © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ew De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) Simplified State Diagram with G X Deselect W W X W CW R R First Write First Read ica ti o W X n ar eN ot Re co m CW CR m en d R ed R W CW CR X sp ec if Burst Write R CR Burst Read th is CW Rev: 2.17 11/2004 Th e x1 8a nd Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. x3 6 pa rt s in 15/41 fo rN X CR © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ew De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 Unit De sig n Unit V V V V –0.5 to 4.6 V V V V –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 1.5 +/–20 ew fo rN . mA mA W o o en d –55 to 125 ed C C Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 ar eN ot Min. 3.0 2.3 3.0 2.3 Re co m Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Typ. 3.3 2.5 3.3 2.5 m –55 to 125 Max. 3.6 2.7 3.6 2.7 Notes Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. in th is sp ec if ica ti o VDDQ3 VDDQ2 16/41 n © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218(B/D)/GS816236(B/D)/GS816272(C) VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 2.0 –0.3 2.0 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V Notes De sig n V V . 1 1 1,3 1,3 VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. –0.3 Re co m Typ. — — — — m en d Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. ed Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD fo rN ew Unit V V V V Notes 1 1 1,3 1,3 ica ti o Symbol TA TA n pa Parameter rt s Recommended Operating Temperatures Min. 0 –40 in th is Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. sp ec if ar eN ot 0.6*VDD –0.3 0.6*VDD Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Rev: 2.17 11/2004 Th e Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. x1 8a nd Ambient Temperature (Industrial Range Versions) x3 6 Ambient Temperature (Commercial Range Versions) 17/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218(B/D)/GS816236(B/D)/GS816272(C) Undershoot Measurement and Timing VIH VDD + 2.0 V Overshoot Measurement and Timing 50% tKC 50% VSS – 2.0 V 50% tKC VDD VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Note: These parameters are sample tested. Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 Fig. 1 x3 6 pa rt s Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. in th is x1 8a nd DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance sp ec if VDDQ/2 ica ti o Output Load 1 n ar eN ot AC Test Conditions Rev: 2.17 11/2004 Th e 18/41 Re co m Input/Output Capacitance CI/O VOUT = 0 V m Input Capacitance CIN VIN = 0 V en d Parameter Symbol Test conditions Typ. 4 6 ed fo rN Max. 5 7 ew Unit pF pF 30pF* © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n VSS 50% . GS816218(B/D)/GS816236(B/D)/GS816272(C) DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, SCD, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA Max 1 uA De sig n –1 uA –1 uA . 1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V ew –100 uA –1 uA –1 uA 1.7 V 2.4 V — Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o 19/41 n ar eN ot Re co m m en d ed fo rN © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Operating Currents -250 Mode Symbol 0 to 70°C Unit n/a n/a n/a n/a 290 60 195 30 240 30 165 15 215 15 150 10 290 45 195 30 240 25 205 30 250 25 165 15 175 15 300 45 250 40 185 30 205 20 155 15 160 10 140 10 150 10 260 40 195 30 215 20 165 15 225 15 185 15 195 15 170 15 135 10 225 35 180 30 190 20 150 15 175 15 155 15 165 15 150 15 160 15 180 15 145 10 235 35 190 30 200 20 160 15 250 30 205 25 215 25 190 25 200 25 170 20 140 10 155 10 125 10 205 30 165 20 170 15 140 10 205 30 185 30 195 30 180 30 190 30 165 20 175 20 180 20 150 10 165 10 135 10 215 30 175 20 180 15 150 10 300 60 250 50 260 50 225 45 235 45 205 40 215 40 mA -225 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C -200 -166 -150 -133 Parameter Th e Pipeline (x72) IDD IDDQ IDD IDDQ n/a n/a n/a n/a IDD IDDQ 290 40 180 20 260 20 165 10 n/a n/a n/a 175 10 155 10 165 10 270 20 235 20 245 20 190 20 170 20 180 20 300 40 265 35 275 35 IDD IDDQ Rev: 2.17 11/2004 –40 to 85°C Test Conditions x1 8a nd x3 6 pa Pipeline (x36) Flow Through mA Operating Current 3.3 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open rt s in Pipeline Flow Through mA th is IDD IDDQ mA mA (x18) Flow Through Pipeline n/a (x72) Flow Through IDDQ IDD IDDQ 290 30 180 20 260 15 165 10 20 20 85 IDD 60 175 10 30 30 90 65 270 15 235 15 155 10 20 20 80 60 190 20 170 20 180 20 300 30 265 30 275 30 IDD IDDQ IDD IDDQ IDD IDDQ ISB ISB IDD n/a n/a n/a n/a Pipeline (x36) Flow Through Pipeline (x18) Flow Through Pipeline — Flow Through Pipeline — Flow Through IDD IDD IDDQ IDD IDDQ sp ec if ica ti o n ar eN ot Re co m 245 15 165 10 30 30 85 65 215 15 150 10 20 20 75 50 mA 20/41 mA mA Operating Current mA 2.5 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open m mA Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 225 15 en d 160 10 30 30 80 55 185 10 140 10 ed 20 20 64 50 195 10 150 10 170 10 135 10 30 20 30 70 55 180 10 145 10 30 20 30 60 50 155 10 125 10 20 20 65 50 55 45 165 10 135 10 30 30 55 mA mA mA mA mA fo rN Standby Current ZZ ≥ VDD – 0.2 V ew GS816218(B/D)/GS816236(B/D)/GS816272(C) © 1999, GSI Technology Deselect Current De sig n Device Deselected; All other inputs ≥ VIH or ≤ VIL . 50 mA Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. GS816218(B/D)/GS816236(B/D)/GS816272(C) AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Symbol tKC tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE -250 Min 4.0 — 1.5 1.5 1.2 0.2 5.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 Max — 2.5 — — — — — 5.5 — — — — — — -225 Min 4.4 — 1.5 1.5 1.3 0.3 6.0 — 3.0 3.0 1.5 Max — 2.7 — — — — — 6.0 — — — -200 Min 5.0 — 1.5 1.5 1.4 0.4 6.5 — Max — 3.0 — — — — -166 Min 6.0 — 1.5 1.5 1.5 0.5 Max — 3.4 — — -150 Min 6.7 — 1.5 Max — -133 Min 7.5 — Max — 4.0 — — — — — 8.5 — — — — — — 3.0 4.0 — 3.0 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ew 1.5 1.5 0.5 7.5 — 3.0 3.0 1.5 0.5 1.5 1.7 1.5 — 0 — 5 1 20 fo rN — — — 7.0 — — — — — — 3.0 3.5 — 3.0 — — — ed en d — 7.0 — m Re co m 6.5 — 3.0 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 3.0 — — — — — ar eN ot 1.5 0.5 1.3 1.5 0.5 — 1.3 — n ica ti o 1.5 — 2.7 2.7 — 2.7 — — — 2.5 1.5 — 0 — 5 1 20 1.5 — 0 — 5 1 20 3.0 3.2 — 3.0 — — — sp ec if 2.5 — th tOHZ1 tZZS2 is tOLZ1 — 5 1 20 2.5 — — — in rt s ZZ setup time ZZ hold time Rev: 2.17 11/2004 Th e x1 8a nd Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. x3 6 ZZ recovery pa tZZH2 tZZR 21/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n 3.8 — — — — — 7.5 — — — — — — 3.0 3.8 — 3.0 — — — 1.5 1.5 1.5 0.5 8.5 — 3.0 3.0 1.5 0.5 1.7 2 1.5 — 0 — 5 1 20 © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) Pipeline Mode Timing (SCD) Begin Read A Cont Cont Deselect Write B Single Write tKL tKH tKC Read C Read C+1 Read C+2 Read C+3 Cont Burst Read Deselect Single Read CK ADSP tS tH ADSC tS ADV tS tH A0–An A B C ADSC initiated read tH tS GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G n ar eN ot tH Re co m m en d ed fo rN Deselected with E1 ica ti o E1 masks ADSP E2 and E3 only sampled with ADSP and ADSC rt s in th is sp ec if tS tOHZ Q(A) D(B) tKQ tH tLZ Q(C) Q(C+1) Q(C+2) ew De sig n tKQX tHZ Q(C+3) Rev: 2.17 11/2004 Th e x1 8a nd x3 6 DQa–DQd pa tOE 22/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . GS816218(B/D)/GS816236(B/D)/GS816272(C) Flow Through Mode Timing (SCD) Begin Read A Cont tKL tKH Cont tKC Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect CK ADSP tS tH ADSC tS tH ADV tS tH A0–An A B C Fixed High tS tH GW tS tH BW tS tH Ba–Bd tS tH E1 tS tH E2 tS tH E3 ica ti o n ar eN ot Re co m m en d ed fo rN Deselected with E1 E2 and E3 only sampled with ADSC pa G rt s in th is sp ec if x3 6 tH tS tOHZ Q(A) D(B) tOE tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) ew tS tH ADSC initiated read De sig n tHZ tKQX Rev: 2.17 11/2004 Th e x1 8a nd DQa–DQd 23/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . GS816218(B/D)/GS816236(B/D)/GS816272(C) Pipeline Mode Timing (DCD) tKL tKH CK ADSP tS tH ADSC tS ADV tS tH Ao–An A B C ADSC initiated read tKC tH GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tOE tH ar eN ot Re co m tS m en d ed fo rN Deselected with E1 E2 and E3 only sampled with ADSC th is sp ec if ica ti o in tS tH D(B) n tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) ew tHZ tKQX tOHZ Q(A) Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s DQa–DQd Hi-Z 24/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n © 1999, GSI Technology . Begin Read A Cont Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect Deselect GS816218(B/D)/GS816236(B/D)/GS816272(C) Flow Through Mode Timing (DCD) tKL tKH CK ADSP tS tH ADSC tH tS ADV tS tH Ao–An A B C Fixed High tKC tS ed tS tH GW tS tH BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G ica ti o n ar eN ot Re co m m en d fo rN tH Deselected with E1 E1 masks ADSP tS tH ADSC initiated read E2 and E3 only sampled with ADSP and ADSC th is rt s in pa tOE tKQ sp ec if E1 masks ADSP tH tS tOHZ Q(A) D(B) ew tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) tLZ Q(C) DQa–DQd Rev: 2.17 11/2004 Th e x1 8a nd x3 6 25/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n © 1999, GSI Technology Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect . GS816218(B/D)/GS816236(B/D)/GS816272(C) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKC CK Setup Hold ADSP ADSC tKL ar eN ot Re co m m tZZS ZZ tZZH Application Tips Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. in th is sp ec if ica ti o 26/41 n en d tKH ed tZZR fo rN ew Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description JTAG Port Registers Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the Rev: 2.17 11/2004 27/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Th e Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. x1 8a nd Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. x3 6 pa rt s Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. in th is sp ec if Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. ica ti o n TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. ar eN ot TDI Test Data In In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Re co m The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. m en d Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. ed fo rN ew De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. · · · 108 · · · · · · · 0 210 TDI 31 30 29 ar eN ot Instruction Register ID Code Register Re co m Bypass Register m en d ed Boundary Scan Register · ··· 210 TMS TCK Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. rt s in th is sp ec if Test Access Port (TAP) Controller ica ti o Control Signals 28/41 n fo rN · 1 0 TDO ew © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n . JTAG TAP Block Diagram GS816218(B/D)/GS816236(B/D)/GS816272(C) ID Register Contents Die Revision Code Bit # x72 x36 x32 x18 x16 GSI Technology JEDEC Vendor ID Code Presence Register 0 1 1 1 1 1 Not Used 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 X 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 0 0 0 0 ed Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. 29/41 n ar eN ot Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. Re co m m Tap Controller Instruction Set en d fo rN X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001 ew X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 011011001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n I/O Configuration © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 1 Capture DR 0 1 Capture IR 0 fo rN 1 Shift DR 1 1 0 1 Shift IR ew 0 0 0 0 Exit2 DR 1 Re co m 1 0 m Pause DR en d 0 ed Exit1 DR Exit1 IR 0 Pause IR 1 0 Exit2 IR 1 Update DR 1 0 ar eN ot Update IR 1 Instruction Descriptions EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 2.17 11/2004 Th e x1 8a nd SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. x3 6 pa rt s in th BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. is sp ec if ica ti o 30/41 n Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n © 1999, GSI Technology 0 Run Test Idle Select DR 0 Select IR 0 . GS816218(B/D)/GS816236(B/D)/GS816272(C) Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU Code 000 001 010 011 100 101 110 ar eN ot JTAG TAP Instruction Set Summary Description Re co m m en d ed fo rN ew De sig n Places the Boundary Scan Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. . Notes 1 1, 2 1 1 1 1 1 1 Rev: 2.17 11/2004 Th e x1 8a nd BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. x3 6 pa Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. rt s in GSI private instruction. th Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. is sp ec if ica ti o 31/41 Preloads ID Register and places it between TDI and TDO. n © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218(B/D)/GS816236(B/D)/GS816272(C) JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 2.0 –0.3 0.6 * VDD2 –0.3 –300 –1 –1 1.7 — — Max. VDD3 +0.3 0.8 VDD2 +0.3 1 Unit Notes V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9 0.3 * VDD2 ew fo rN 100 1 — — 100 mV ed m VDDQ – 100 mV en d 0.4 JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level is sp ec if th Conditions VDD – 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ ica ti o Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA n ar eN ot Re co m JTAG Port AC Test Load rt s in De sig n 50Ω pa Output reference level x3 6 VDDQ/2 * Distributed Test Jig Capacitance Rev: 2.17 11/2004 Th e x1 8a nd Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. 32/41 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . V V uA uA V V V V uA 30pF* GS816218(B/D)/GS816236(B/D)/GS816272(C) JTAG Port Timing Diagram tTKC TCK tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS Min 50 — ica ti o n Max — sp ec if 20 — — — — 20 20 is Rev: 2.17 11/2004 Th e x1 8a nd Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. x3 6 pa rt s in tTH th 10 10 33/41 ar eN ot Unit ns ns ns ns ns ns Re co m m en d ed fo rN © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ew De sig n tTH . GS816218(B/D)/GS816236(B/D)/GS816272(C) 209 BGA Package Drawing (Package C) 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array C A1 A aaa D D1 e en d ed E1 ∅b Symbol A A1 ∅b c D Rev 1.0 Min — 0.40 0.50 0.31 21.9 Typ — 0.50 0.60 0.36 22.0 Max 1.70 0.60 ica ti o Units mm n ar eN ot Symbol D1 E E1 e aaa Re co m e m Min — 13.9 — — — Typ 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15 E fo rN Bottom View Max — 14.1 — — — ew De sig n Units mm mm mm mm mm © 1999, GSI Technology sp ec if mm mm mm mm 0.70 th Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in is 0.38 22.1 34/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. . Side View GS816218(B/D)/GS816236(B/D)/GS816272(C) Package Dimensions—165-Bump FPBGA (Package D; Variation 1) A1 TOP BOTTOM Ø0.10M C Ø0.25M C A B Ø0.40~0.50 A1 A ar eN ot A B C D E F G H J K L M N P R 15±0.0 14. 1.0 Re co m m en d 1.0 10. 13±0.0 0.45±0.05 0.25 C ica ti o n 0.15 C B 0.20(4 (0.26 Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th is 0.25~0.4 1.20 C SEATING sp ec if 35/41 ed fo rN 1.0 1.0 ew Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n A B C D E F G H J K L M N P R © 1999, GSI Technology 1 2 3 4 5 6 7 8 9 10 11 10 9 8 7 6 5 4 3 2 . GS816218(B/D)/GS816236(B/D)/GS816272(C) Package Dimensions—119-Bump FPBGA (Package B, Variation 2) A1 1 A B C D E F G H J K L M N P R T U TOP VIEW BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) 22±0.10 20.32 B 0.70±0.05 0.15 C ar eN ot Re co m m en d ica ti o n 7.62 A 0.20(4x) 14±0.10 0.56±0.05 Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th 0.50~0.70 1.86.±0.13 C SEATING PLANE is sp ec if 0.15 C 36/41 ed fo rN 1.27 1.27 ew Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n A B C D E F G H J K L M N P R T U 2 3 4 5 6 7 7 6 5 43 2 1 © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) Ordering Information for GSI Synchronous Burst RAMs Org 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 Part Number1 GS816218B-250 GS816218B-225 GS816218B-200 GS816218B-166 GS816218B-150 GS816218B-133 GS816236B-250 GS816236B-225 GS816236B-200 GS816236B-166 GS816236B-150 GS816236B-133 GS816218D-250 GS816218D-225 GS816218D-200 GS816218D-166 GS816218D-150 GS816218D-133 GS816236D-250 GS816236D-225 GS816236D-200 GS816236D-166 GS816236D-150 GS816236D-133 Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 250/5.5 225/6 200/6.5 166/7 ew fo rN 150/7.5 133/8.5 ed en d 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 Re co m m ar eN ot 119 BGA (var. 2) 119 BGA (var. 2) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) ica ti o n Pipeline/Flow Through sp ec if Pipeline/Flow Through in th Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through is Pipeline/Flow Through rt s pa x3 6 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 2.17 11/2004 Th e x1 8a nd 37/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n C C C C C C C C C C C C C C C C C C C C C C C C © 1999, GSI Technology Speed2 (MHz/ns) . TA3 Status GS816218(B/D)/GS816236(B/D)/GS816272(C) Ordering Information for GSI Synchronous Burst RAMs Org 256K x 72 256K x 72 256K x 72 256K x 72 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 Part Number1 GS816272C-200 GS816272C-166 GS816272C-150 GS816272C-133 GS816218B-250I GS816218B-225I GS816218B-200I GS816218B-166I GS816218B-150I GS816218B-133I GS816236B-250I GS816236B-225I GS816236B-200I GS816236B-166I GS816236B-150I GS816236B-133I GS816218D-250I GS816218D-225I GS816218D-200I GS816218D-166I GS816218D-150I GS816218D-133I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package 209 BGA 209 BGA 209 BGA 209 BGA 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) Speed2 (MHz/ns) 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 TA3 C Status ew fo rN ed 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 en d 119 BGA (var. 2) 119 BGA (var. 2) Re co m 119 BGA (var. 2) m ar eN ot 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) ica ti o n 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) Pipeline/Flow Through Pipeline/Flow Through sp ec if th Pipeline/Flow Through in Pipeline/Flow Through Pipeline/Flow Through is Rev: 2.17 11/2004 Th e x1 8a nd Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings x3 6 pa rt s 38/41 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n C C C I I I I I I I I I I I I I I I I I I © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) Ordering Information for GSI Synchronous Burst RAMs Org 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 256K x 72 256K x 72 256K x 72 256K x 72 Part Number1 GS816236D-250I GS816236D-225I GS816236D-200I GS816236D-166I GS816236D-150I GS816236D-133I GS816272C-200I GS816272C-166I GS816272C-150I GS816272C-133I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 209 BGA 209 BGA 209 BGA 209 BGA Speed2 (MHz/ns) 250/5.5 225/6 200/6.5 166/7 TA3 I Status fo rN 133/8.5 150/7.5 ew ed 200/6.5 166/7 150/7.5 133/8.5 en d m Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings th is DS/DateRev. Code: Old; New GS816218B-150IB 1.00 9/ 1999A;GS816218B-150IB 2.00 1/1999B Types of Changes Format or Content sp ec if 18Mb Sync SRAM Datasheet Revision History ica ti o n ar eN ot Content pa rt s • Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B • Added x72 Pinout. • Added GSI Logo. • Changed BGA package drawing for 209 pin package. Rev: 2.17 11/2004 Th e x1 8a nd x3 6 GS816218B 2.01 1/ 2000C;GS816218 B 2.02 1/ 2000D in 39/41 Re co m Page;Revisions;Reason Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n I I I I I I I I I © 1999, GSI Technology . GS816218(B/D)/GS816236(B/D)/GS816272(C) 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason • Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Core and Interface voltages - Changed paragraph to include information for 3.3V;Completeness • Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. • Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness • Electrical Characteristics - Added second Output High Voltage line to table; completeness. • Note: There was not a Rev 2.02 for the 8160Z or the 8161Z. 816218_r2_05; 816218_r2_06 816218_r2_06; 816218_r2_07 Content • Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 19 from 20 ns to 100 ns • Added 225 MHz speed bin • Updated numbers in page 1 table, AC Characteristics table, and Operating Currents table • Updated format to comply with Technical Publications standards Content/Format sp ec if 816218_r2_07; 816218_r2_08 816218_r2_08; 816218_r2_09 816218_r2_09; 816218_r2_10 Content th is Content in Content rt s x1 8a nd 816218_r2_10; 816218_r2_11 x3 6 pa Content Th e 816218_r2_11; 816218_r2_12 Content Rev: 2.17 11/2004 ica ti o 40/41 n • Changed VSSQ references to VSS • Changed K4 and K8 in 209-bump BGA to NC • Updated Capitance table—removed Input row and changed Output row to I/O • Updated numbers for Clock to Output Valid (PL) and Clock to Output Valid (FT) for 166 MHz and 133 MHz on AC Electrical Characteristics table • Updated Features list on page 1 • Completely reworked table on page 1 • Updated Mode Pin Functions table on page 9 • Added 3.3 V references to entire document • Updated Operating Conditions table • Updated JTAG section • Updated Boundary Scan Chain table • Updated Operating Currents table and added note • Updated Application Tips paragraph • Update table on page 1; added power numbers • Updated JTAG ID Register table • Updated Synchronous Truth table • Updated Operating Currents table • Updated table on page 1; updated power numbers • Updated Recommended Operating Conditions table (added VDDQ references) © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ar eN ot Re co m 816218_r2_04; 816218_r2_05 Content • Updated BGA pin description table to comply with JEDEC standards m en d GS18/362.03 2/2000E; 816218_r2_04 Content • Updated pad out and pin description table (7D changed from NC to GW) ed fo rN ew GS18/362.0 1/2000DGS18/ 362.03 2/2000E De sig n . GS816218(B/D)/GS816236(B/D)/GS816272(C) 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content Page;Revisions;Reason • Updated table on page 1 • Added 119-Bump BGA Pin Description table • Created recommended operating conditions tables on pages 16 and 17 • Updated AC Electrical Characteristics table • Added Sleep mode description on page 29 • Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) • Updated BSR table (2 and 3 changed to X (value undefined)) • Added 250 MHz speed bin • Deleted 180 MHz speed bin • Updated AC Characteristics table • Updated package designator for 209 BGA from B to C • Updated VIH from 1.7 to 2.0 • Updated FT power numbers • Updated Mb references from 16Mb to 18Mb • Removed ByteSafe references • Changed DP and QE pins to NC • Updated ZZ recovery time diagram • Add 165-bump FPBGA package • Updated AC Test Conditions table and removed Output Load 2 diagram • Removed parity I/O bit designation from 165 BGA pinout • Removed Preliminary banner • Removed BSR table • Removed pin locations from pin description tables • Removed 250 MHz and 225 MHz specs from x72 • Updated AC Characteristics table (tHZ, tOE, tOHZ equal to tKQ (PL) for 250 MHz and 225 MHz) • New timing diagrams added • Updated format • Updated timing diagrams 816218_r2_13; 816218_r2_14 Content 816218_r2_15; 816218_r2_16 816218_r2_16; 816218_r2_17 Content Rev: 2.17 11/2004 Th e x1 8a nd x3 6 pa rt s in th Format/Content is sp ec if ica ti o 816218_r2_14; 816218_r2_15 Content 41/41 n ar eN ot Re co m m en d ed fo rN ew 816218_r2_12; 816218_r2_13 Content Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. De sig n © 1999, GSI Technology .