GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
119, 165, & 209 BGA Commercial Temp Industrial Temp Features
• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 8M devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down • JEDEC-standard 119-, 165-, or 209-Bump BGA package
18Mb Pipelined and Flow Through Synchronous NBT SRAM
250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
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The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
2.5 4.0 280 330 n/a 275 320 n/a 5.5 5.5 175 200 n/a 175 200 n/a 2.7 4.4 255 300 n/a 250 295 n/a 6.0 6.0 165 190 n/a 165 190 n/a 3.0 5.0 230 270 350 230 265 335 6.5 6.5 160 180 225 160 180 225 3.4 6.0 200 230 300 195 225 290 7.0 7.0 150 170 115 150 170 115 3.8 6.7 185 215 270 180 210 260 7.5 7.5 145 165 210 145 165 210 4.0 7.5 165 190 245 165 185 235 8.5 8.5 135 150 185 135 150 185 ns ns mA mA mA mA mA mA ns ns mA mA mA mA mA mA
Pipeline 3-1-1-1
tKQ tCycle
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3.3 V
Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72)
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2.5 V Flow Through 2-1-1-1 3.3 V
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Functional Description
The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 & x36), or 209-bump (x72) BGA package.
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Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 1999, GSI Technology
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 Pad Out—209-Bump BGA—Top View (Package C)
1 A B C D E F G H J K L M N P R T U V W Rev 10 DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD 2 DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQH DQH DQH DQH DQPH DQD DQD DQD DQD 3 A BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS 5 A NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS 6 ADV W E1 G VDD ZQ MCH MCL MCH MCL FT 7 A A NC NC VDD VSS VDD VSS 8 E3 BB BE NC VDDQ VSS 9 A BF BA 10 DQB 11 DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC DQA DQA DQA DQA DQPE DQE DQE DQE DQE
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VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK
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VDDQ VSS
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VDD VSS
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VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
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VDD VSS
MCL
VDD VSS
MCH ZZ VDD LBO A A1 A0
VDD VSS VDD PE NC A A
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VDDQ NC A
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VDD NC NC A A
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11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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DQB DQB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE DQE DQE DQE
© 1999, GSI Technology
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z72 BGA Pin Description Symbol
A 0, A 1 An DQA DQB DQC DQD DQE DQF DQG DQH BA, BB, BC,BD, BE, BF, BG,BH NC CK W E1, E3 E2 G ZZ FT LBO MCH MCL PE ADV ZQ TMS TDI TDO TCK VDD VSS I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs
I I I I I I I I
Write Enable. Writes all enabled bytes; active low Chip Enable; active low Chip Enable; active high
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Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) Burst Address Counter Advance Enable; active high
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FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
VDDQ
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Output Enable; active low
Sleep Mode control; active high
Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect Low
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Clock Input Signal; active high
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No Connect
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Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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I/O
Data Input and Output pins
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQB NC LBO 2 A A NC DQB DQB DQB DQB MCH NC NC NC NC DNU NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC ZQ DQA DQA DQA DQA NC A A 11 A A
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NC DQA DQA DQA DQA DQA ZZ NC NC NC NC NC NC A
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TDI TMS
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11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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B C D E F G H J K L M N P R
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1 A B C D E F G H J K L M N P R NC NC DQC DQC DQC DQC DQC FT DQD DQD DQD DQD DQD NC LBO 2 A A NC DQC DQC DQC DQC MCH DQD DQD DQD DQD DNU NC NC 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB ZQ DQA DQA DQA DQA NC A A 11 NC A
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NC DQB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQA NC A
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TDI TMS
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11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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B C D E F G H J K L M N P R
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z36 Pad Out—119-Bump BGA—Top View (Package B)
1 A B C D E F G H J K L M N P R T VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD
2 A E2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC TMS
3 A A A VSS VSS VSS BC VSS NC
4 A ADV VDD ZQ E1 G
5 A A A VSS VSS VSS BB
6 A E3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC
7 VDDQ NC NC
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A17 W
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VSS NC VSS BA VSS VSS VSS FT A TDO
VDD CK NC
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VSS BD
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VDDQ DQD
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VSS VSS VSS LBO A TDI
CKE A1 A0 VDD A TCK
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DQD NC NC VDDQ
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DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA PE ZZ VDDQ © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z18 Pad Out—119-Bump BGA—Top View (Package B)
1 A B C D E F G H J K L M N VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB
2 A E2 A NC DQB NC DQB NC VDD DQB NC
3 A A A VSS VSS VSS BB VSS NC
4 A ADV VDD ZQ E1 G
5 A A A VSS VSS VSS NC
6 A E3 A DQPA NC
7 VDDQ NC NC
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A17 W
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DQA NC DQA VDD NC DQA NC DQA NC A A NC
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VSS NC VSS BA VSS VSS VSS FT A TDO
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VDD CK NC
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VSS NC
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VDDQ
DQB NC
VSS VSS VSS LBO A TDI
CKE A1 A0 VDD NC TCK
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DQB NC NC NC
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DQPB A A TMS
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VDDQ
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NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA PE ZZ VDDQ © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description Symbol
A 0, A 1 An DQA DQB DQC DQD BA , BB , BC , BD NC CK CKE PE W E1 E3 E2 G ADV ZZ FT LBO ZQ TMS TDI TDO TCK VDD VSS VDDQ
Type
I I I/O I — I I I I I I I I I I I I I I I O I I I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins
No Connect
Clock Input Signal; active high Clock Enable; active low Write Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) Chip Enable; active low
Burst address counter advance enable; active high Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low
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FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
BPR1999.05.18
Rev: 2.21 11/2004
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Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 1999, GSI Technology
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Functional Details
Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function Read Write Byte “a” Write Byte “b” Write Byte “c” Write Byte “d” Write all Bytes Write Abort/NOP W H L L L L L L BA X L H H H L H BB X H L H H L H BC X H H L H L H BD X H H H L L H
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 2.21 11/2004
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Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.
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Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.
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Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Synchronous Truth Table Operation
Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ
R B R B W B B D D D D D External Next External Next External Next Next None None None None None None Current L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X L-H L L L L L L L L L L L L H L H L H H L L L L H X H X L X X X X X L X X X X L L H X X X L X L X L X X H X H X H X L X L X L L L H H X L L
DQ
Q Q
Notes
1,10 2 1,2,10 3 1,3,10
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X X X X X X X X X
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X X X H X L X X X
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H X X L X X X
X
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X L H X X X
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L High-Z L L L L L L L L L H L High-Z D D High-Z High-Z High-Z High-Z High-Z High-Z -
High-Z 1,2,3,10
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L H X X
H X X X
X X X
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H
Rev: 2.21 11/2004
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Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles.
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Pipelined and Flow Through Read Write Control State Diagram
Deselect
R
W
D
D W R
B
R
W
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B
Burst Read
D
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R
W
Burst Write
D
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R
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New Read
New Write
B
Key
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n
Input Command Code
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. n+2 n+3
ƒ Transition
Current State (n)
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Next State (n+1)
Clock (CK)
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Command
ƒ
Current State
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Next State
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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D
B
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Pipeline Mode Data I/O State Diagram
R
High Z (Data In) D Intermediate Intermediate
W
Data Out (Q Valid) D
High Z B D
Intermediate
Key
Input Command Code
ƒ Transition
Current State (n)
Transition
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Clock (CK)
in
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n
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Intermediate State (N+1)
Next State (n+2)
n+1
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Re co m
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change.
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
n+2
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Command
ƒ
Current State
ƒ
Intermediate State
ƒ
Next State
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W
R
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Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Intermediate
BW
Intermediate
RB
Intermediate
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Flow Through Mode Data I/O State Diagram
BW High Z (Data In) D
W
Data Out (Q Valid) D
W
R
B D
Key
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Input Command Code
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ƒ Transition
Current State (n)
n
Next State (n+1)
n
sp ec if
n+1
Re co m
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
n+2
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High Z
Clock (CK)
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Command
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Current State
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Next State
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Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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R
RB
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. FLXDrive™ The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Name
Burst Order Control Output Register Control Power Down Control FLXDrive Output Impedance Control
Pin Name
LBO FT ZZ
State
L L H
Re co m
Mode Pin Functions
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H or NC L or NC H L
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sp ec if
ZQ
High Drive (Low Impedance) Low Drive (High Impedance)
H or NC
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
in
th
Note: There is a are pull-up devicesonthe ZQ and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
is
14/38
fo rN
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB
ew
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
2nd address 3rd address 4th address 01 10 11 00 11 10
ew
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
en d
ed
fo rN
Sleep Mode
th
CK
rt s
in
tKC
is
sp ec if
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKL
tKH
ica ti o
n
ar eN ot
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.
Re co m
m
tZZR tZZS tZZH
ZZ
Rev: 2.21 11/2004
Th e
Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.
x1 8a nd
x3 6
pa
15/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
11 10 00 01 01 00
BPR 1999.05.18
1st address
00
01
10
11
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
–0.5 to 4.6
Unit
De sig n
Unit
V V V V
–0.5 to 4.6
V V V V
–0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 1.5 +/–20
ew
fo rN
.
mA mA W
o o
en d
–55 to 125
ed
C C
Power Supply Voltage Ranges Parameter
3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage
Symbol
VDD3 VDD2
ar eN ot
Min.
3.0 2.3 3.0 2.3
Re co m
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Typ.
3.3 2.5 3.3 2.5
m
–55 to 125
Max.
3.6 2.7 3.6 2.7
Notes
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
in
th
is
sp ec if
ica ti o
VDDQ3 VDDQ2 16/38
n
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
VDDQ3 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
2.0 –0.3 2.0 –0.3
Typ.
— — — —
Max.
VDD + 0.3 0.8 VDDQ + 0.3 0.8
Unit
V V
Notes
De sig n
V V
.
1 1 1,3 1,3
VDDQ2 Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
–0.3
Re co m
Typ.
— — — —
m
en d
Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
ed
Max.
VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD
fo rN
ew
Unit
V V V V
Notes
1 1 1,3 1,3
ica ti o
Symbol
TA TA
n
pa
Parameter
rt s
Recommended Operating Temperatures Min.
0 –40
in
th
is
Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
sp ec if
ar eN ot
0.6*VDD –0.3
0.6*VDD
Typ.
25 25
Max.
70 85
Unit
°C °C
Notes
2 2
Rev: 2.21 11/2004
Th e
Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
x1 8a nd
Ambient Temperature (Industrial Range Versions)
x3 6
Ambient Temperature (Commercial Range Versions)
17/38
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Undershoot Measurement and Timing
VIH VDD + 2.0 V
Overshoot Measurement and Timing
50% tKC
50% VSS – 2.0 V 50% tKC
VDD
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Note: These parameters are sample tested.
Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
VDD – 0.2 V 0.2 V 1 V/ns VDD/2 Fig. 1
x3 6
pa
rt s
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
in
th
is
x1 8a nd
DQ 50Ω VDDQ/2
* Distributed Test Jig Capacitance
sp ec if
VDDQ/2
ica ti o
Output Load 1
n
ar eN ot
AC Test Conditions
Rev: 2.21 11/2004
Th e
18/38
Re co m
Input/Output Capacitance
CI/O
VOUT = 0 V
m
Input Capacitance
CIN
VIN = 0 V
en d
Parameter
Symbol
Test conditions
Typ.
4 6
ed
fo rN
Max.
5 7
ew
Unit
pF pF 30pF* © 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
VSS
50%
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current FT, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IIN1 IIN2 IOL VOH2 VOH3 VOL
Test Conditions
VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA
Min
–1 uA
Max
1 uA
De sig n
–1 uA –1 uA
.
1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V
ew
–100 uA –1 uA –1 uA 1.7 V 2.4 V —
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
in
th
is
sp ec if
ica ti o
19/38
n
ar eN ot
Re co m
m
en d
ed
fo rN
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-250 Mode Symbol 0 to 70°C Unit n/a
mA mA mA mA
-225 0 to 70°C n/a n/a 265 35 170 20 235 20 155 10 n/a n/a 290 45 300 45 250 40 260 40 195 30 215 20 165 15 195 10 150 10 10 10 10 10 10 30 20 30 20 30 20 165 10 150 10 160 10 140 10 150 10 135 10 225 35 180 30 190 20 150 15 170 10 135 245 20 215 15 225 15 185 15 195 15 170 15 180 15 145 10 235 35 190 30 200 20 160 15 180 10 145 10 30 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 155 10 125 10 205 30 165 20 170 15 140 10 155 10 125 10 20 275 35 240 30 250 30 205 25 215 25 190 25 200 25 170 20 180 20 150 10 165 10 135 10 215 30 175 20 180 15 150 10 165 10 135 10 30 n/a 195 30 205 30 185 30 195 30 180 30 190 30 165 20 175 20 n/a 290 60 300 60 250 50 260 50 225 45 235 45 205 40 215 40 –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C
-200
-166
-150
-133
Parameter
Test Conditions
–40 to 85°C n/a n/a 300 40 190 20 270 20
Th e
Pipeline (x72) Flow Through IDDQ IDD IDDQ IDD IDDQ IDD IDDQ 260 20
DD
IDD IDDQ IDD n/a 290 40 180 20
Rev: 2.21 11/2004
Operating Current Pipeline
x1 8a nd x3 6 p(x36) Flow ar ts Through in Pipeline th
(x18)
DDQ
3.3 V
Device Selected; All other inputs ≥VIH or ≤ VIL Output open
is
DD DDQ
mA mA mA mA mA mA mA mA mA
Flow Through Pipeline
20/38 (x72) Flow Through
DD
I sp 165 175 Ie cif 10 10 I ica n/a n/a I ti o n I n/a n/a IDDQ IDD IDDQ 290 30 180 20 260 15 165 10 20 20 85 IDD 60 IDD IDDQ IDD IDDQ IDD IDDQ ISB ISB IDD
Operating Current Pipeline (x36) Flow Through Pipeline (x18) Flow Through Pipeline — Flow Through Pipeline — Flow Through
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2.5 V
Device Selected; All other inputs ≥VIH or ≤ VIL Output open
ar n/a n/a 195 205 185 30 30 30 eN 300 265 275 ot30 240 250 205 30 30 Re 25 25 20 190 170 180 c 165 o 175 155 20 20 20 15 m 15 15 270 235 245 215 m 225 e 185 15 15 15 15 15 n 10 de d 175 155 165 150 160 140
30 90 65 20 80 60 30 85 65 20 75 50 30 80 55 20 64 50
Standby Current
ZZ ≥ VDD – 0.2 V
fo10 10 r 30 N 20 ew 30 20
70 55 60 50
30 55 50
mA mA mA
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
© 1999, GSI Technology
Deselect Current
Device Deselected; All other inputs ≥ VIH or ≤ VIL
30 De 20 s 65 ig 50 n. 55 45
Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
AC Electrical Characteristics
Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time Symbol tKC tKQ tKQX tLZ tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2
1
-250 Min 4.0 — 1.5 1.5 1.2 0.2 5.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 Max — 2.5 — — — — — 5.5 — — — — — — 2.5 2.5 — 2.5 — —
-225 Min 4.4 — 1.5 1.5 1.3 0.3 6.0 — 3.0 3.0 1.5 0.5 1.3 1.5 Max — 2.7 — — — — — 6.0 — — — — — —
-200 Min 5.0 — 1.5 1.5 1.4 0.4 6.5 — 3.0 3.0 1.5 0.5 Max — 3.0 — — — — — 6.5 — — — — — — 3.0 3.2 — 3.0 — —
-166 Min 6.0 — 1.5 1.5 1.5 0.5 7.0 — 3.0 Max — 3.4 — — — —
-150 Min 6.7 — 1.5 1.5 1.5 Max — 3.8 — —
-133 Min 7.5 — Max — 4.0 — — — — — 8.5 — — — — — — 3.0 4.0 — 3.0 — —
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ew
0.5 7.5 — 3.0 3.0 1.5 0.5 1.5 1.7 1.5 — 0 — 5 1
fo rN
— 7.0 — — — — — — 3.0 3.5 — 3.0 — —
ed
en d
Re co m
m
3.0
1.5 0.5 1.3 1.5 1.5 — 0 — 5 1
1.3
ar eN ot
1.5
1.5 — 0
2.7
1.5 — 0 — 5 1
n
2.7 —
ica ti o
— 5 1
2.7 — —
sp ec if
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
in
th
is
21/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
1.5 1.5 — — — 7.5 — — — — — — 3.0 3.8 — 3.0 — — 1.5 0.5 8.5 — 3.0 3.0 1.5 0.5 1.7 2 1.5 — 0 — 5 1
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Pipeline Mode Timing (NBT)
Write A Read B Suspend tKH tKL Read C tKC Write D writeno-op Read E Deselect
CK
tH tS
A
A tH tS
B
C
D
E
tH tS
tS
tS
W
tH tS
Bn
tH tS
ar eN ot
Re co m
tH
tH
tS
m
ADV
en d
tH
ed
E*
fo rN
tLZ tKQ Q(C) D(D) Q(E)
CKE
ew
tHZ tKQX D(A) Q(B)
DQ
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
in
th
is
sp ec if
ica ti o
22/38
n
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Flow Through Mode Timing (NBT)
Write A Write B Write B+1 tKL tKH
CK
Read C tKC
Cont
Read D
Write E
Read F
Write G
tH tS
CKE
tH tS
E
tH tS
ADV
tH tS
W
tH tS
Bn
tH tS
A0–An A B C
ar eN ot
Re co m
D
m
en d
ed
E
fo rN
F G
DQ
D(A)
D(B)
ica ti o
tS
n
tH
tKQ tLZ
tKQX tHZ
Q(C) Q(D)
ew
tKQ tLZ
D(E) Q(F)
De sig n
tKQX
D(G) D(B+1)
sp ec if
tOLZ tOE tOHZ
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
in
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
th
is
G
23/38
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions Pin
TCK TMS
Test Clock Test Mode Select
In In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.
TDI
Test Data In
In
Rev: 2.21 11/2004
Th e
Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
x1 8a nd
Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.
x3 6
pa
Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
rt s
in
th
is
JTAG Port Registers
sp ec if
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
ica ti o
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
24/38
n
ar eN ot
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
Re co m
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.
m
en d
ed
Pin Name
I/O
Description
fo rN
ew
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
· · ·
108
·
·
·
·
·
·
m
Boundary Scan Register
en d
·
Re co m
0
210
ID Code Register
th
TMS TCK
is
Rev: 2.21 11/2004
Th e
x1 8a nd
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
x3 6
pa
rt s
in
sp ec if
31 30 29
ica ti o
TDI
n
Instruction Register
ar eN ot
Bypass Register
ed
·
···
210
Control Signals Test Access Port (TAP) Controller
25/38
fo rN
·
1 0
TDO
ew
© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
ID Register Contents
Die Revision Code Bit # x72 x36 x32 x18 x16 GSI Technology JEDEC Vendor ID Code Presence Register 0 1 1 1 1 1
Not Used
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X X X
X X X
X X X
X X X
0 0 0
0 0 0
0 0 0
0 X 0
0 1 0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
1 0 1
0 1 1
0 0 0
0 0 0
ed
Rev: 2.21 11/2004
Th e
x1 8a nd
x3 6
pa
rt s
in
th
is
sp ec if
ica ti o
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
26/38
n
ar eN ot
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.
Re co m
m
Tap Controller Instruction Set
en d
fo rN
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
0
0
0
0 011011001 0 011011001 0 011011001 0 011011001
ew
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0 011011001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
I/O Configuration
© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
1
Capture DR
0
1
Capture IR
0
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1
Shift DR
1 1
0 1
Shift IR
ew
0 0 0 0
Exit2 DR
1
Re co m
1
0
m
Pause DR
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0
ed
Exit1 DR
Exit1 IR
0
Pause IR
1
0
Exit2 IR
1
Update DR
1 0
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Update IR
1
Instruction Descriptions
EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Rev: 2.21 11/2004
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SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins.
x3 6
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BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 1999, GSI Technology
0
Run Test Idle
Select DR
0
Select IR
0
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU
Code
000 001 010 011 100 101 110
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JTAG TAP Instruction Set Summary
Description
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Places the Boundary Scan Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
.
Notes
1 1, 2 1 1 1 1 1 1
Rev: 2.21 11/2004
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BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
x3 6
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Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
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GSI private instruction.
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Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
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Preloads ID Register and places it between TDI and TDO.
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
2.0 –0.3 0.6 * VDD2 –0.3 –300 –1 –1 1.7 — —
Max.
VDD3 +0.3 0.8 VDD2 +0.3 1
Unit Notes
V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
0.3 * VDD2
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100 1 — — 100 mV
ed
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VDDQ – 100 mV
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0.4
JTAG Port AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level
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Conditions
VDD – 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ
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Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA
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JTAG Port AC Test Load
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50Ω
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Output reference level
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VDDQ/2
* Distributed Test Jig Capacitance
Rev: 2.21 11/2004
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Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted.
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
.
V V uA uA V V V V uA 30pF*
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
JTAG Port Timing Diagram
tTKC TCK tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 — 20
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Max — 20 — — — —
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10
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Rev: 2.21 11/2004
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Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com.
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Unit ns ns ns ns ns ns
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© 1999, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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tTH
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C A1 A aaa D D1
e
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E1
∅b
Symbol A A1 ∅b c D Rev 1.0
Min — 0.40 0.50 0.31 21.9
Typ — 0.50 0.60 0.36 22.0
Max 1.70 0.60
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Units mm
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Symbol D1 E E1 e aaa
Re co m
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Min — 13.9 — — —
Typ 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15
E
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Bottom View
Max — 14.1 — — —
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Units mm mm mm mm mm © 1999, GSI Technology
sp ec if
mm mm mm mm
0.70
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Rev: 2.21 11/2004
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22.1
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Side View
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Package Dimensions—165-Bump FPBGA (Package D; Variation 1)
A1
TOP
A
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A B C D E F G H J K L M N P R
15±0.0
1.0
Re co m
m
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1.0 10. 13±0.0
0.45±0.05 0.25 C
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0.15 C
B 0.20(4
(0.26
Rev: 2.21 11/2004
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0.25~0.4 1.20
C
SEATING
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14.
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1.0
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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A B C D E F G H J K L M N P R © 1999, GSI Technology
1 2 3 4 5 6 7 8 9 10
11 10 9 8 7 6 5 4 3 2
.
BOTTOM Ø0.10M C Ø0.25M C A B Ø0.40~0.50
A1
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
A1 1
A B C D E F G H J K L M N P R T U
TOP VIEW
BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x)
22±0.10
20.32
B 0.70±0.05 0.15 C
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7.62 A 0.20(4x) 14±0.10
0.56±0.05
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0.50~0.70 1.86.±0.13
C
SEATING PLANE
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1.27
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Rev: 2.21 11/2004
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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A B C D E F G H J K L M N P R T U
BPR 1999.05.18
2
3
4
5
6
7
7 6 5 43 2 1
© 1999, GSI Technology
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Ordering Information—GSI NBT Synchronous SRAM
Org
1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 256K x 72 256K x 72 256K x 72 256K x 72 1M x 18 1M x 18 1M x 18
Part Number1
GS8162Z18B-250 GS8162Z18B-225 GS8162Z18B-200 GS8162Z18B-166 GS8162Z18B-150 GS8162Z18B-133 GS8162Z36B-250 GS8162Z36B-225 GS8162Z36B-200 GS8162Z36B-166 GS8162Z36B-150 GS8162Z36B-133 GS8162Z18D-250 GS8162Z18D-225 GS8162Z18D-200 GS8162Z18D-166 GS8162Z18D-150 GS8162Z18D-133 GS8162Z36D-250 GS8162Z36D-225 GS8162Z36D-200 GS8162Z36D-166 GS8162Z36D-150 GS8162Z36D-133 GS8162Z72C-200 GS8162Z72C-166 GS8162Z72C-150 GS8162Z72C-133
Type
NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
Package
119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2)
Speed2 (MHz/ns)
250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 225/6 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5
TA3
C C C
Status
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250/5.5 200/6.5
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165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 209 BGA 209 BGA 209 BGA 209 BGA 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2)
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NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
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GS8162Z18B-225I GS8162Z18B-200I
x3 6
GS8162Z18B-250I
NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
x1 8a nd
Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36B-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.21 11/2004
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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C C C C C C C C C C C C C C C C C C C C C C C C C I I I © 1999, GSI Technology
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GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
Org
1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 512K x 36 256K x 72 256K x 72 256K x 72 256K x 72
Part Number1
GS8162Z18B-166I GS8162Z18B-150I GS8162Z18B-133I GS8162Z36B-250I GS8162Z36B-225I GS8162Z36B-200I GS8162Z36B-166I GS8162Z36B-150I GS8162Z36B-133I GS8162Z18D-250I GS8162Z18D-225I GS8162Z18D-200I GS8162Z18D-166I GS8162Z18D-150I GS8162Z18D-133I GS8162Z36D-250I GS8162Z36D-225I GS8162Z36D-200I GS8162Z36D-166I GS8162Z36D-150I GS8162Z36D-133I GS8162Z72C-200I GS8162Z72C-166I GS8162Z72C-150I GS8162Z72C-133I
Type
NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
Package
119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 209 BGA 209 BGA 209 BGA 209 BGA
Speed2 (MHz/ns)
166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 200/6.5 166/7 150/7.5 133/8.5
TA3
I I I I I I I I I I I I I I I I I I I I I I I I I
Status
NBT Pipeline/Flow Through NBT Pipeline/Flow Through
Rev: 2.21 11/2004
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Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36B-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
New GS8162Z18/36/72B 1.00 9/ 1999A;GS8162Z18/36/ 72B2.0012/1999B GS8162Z18/36/72B2.00 12/ 1999BGS8162Z18/36/ 72B2.01 1/2000C GS8162Z18/36/72B2.01 1/ 2000C;GS8162Z18/36/ 72B2.02 1/2000D
Types of Changes Page;Revisions;Reason Format or Content
Content
• Added new GSI Logo Format
Content
• Added 209 Pin BGA Package diagram
GS8162Z18/36/72B2.02 1/ 2000DGS8162Z18/36/ 72B2.03 2/2000E
8162Z18_r2_04; 8162Z18_r2_05 8162Z18_r2_05; 8162Z18_42_06 8162Z18_r2_06; 8162Z18_r2_07 8162Z18_r2_07; 8162Z18_r2_08
Content Content
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Content/Format
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Content Content
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8162Z18_r2_08; 8162Z18_r2_09 8162Z18_r2_09; 8162Z18_r2_10
Content
Rev: 2.21 11/2004
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GS8162Z18/36/72B2.03 2/ 2000E; 8162Z18_r2_04
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Content
• Pin 6N changed to MCH. • Updated BGA pin description tables to meet JEDEC standards
• Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 22 from 20 ns to 100 ns • Added 225 MHz speed bin • Updated numbers in page 1 table, AC Characteristics table, and Operating Currents table • Updated format to comply with Technical Publications standards • Changed VSSQ references to VSS • Changed K4 and K8 in 209-bump BGA to NC • Updated numbers for Clock to Output Valid (PL) and Clock to Output Valid (FT) for 166 MHz and 133 MHz on AC Electrical Characteristics table • Updated Features list on page 1 • Completely reworked table on page 1 • Updated Mode Pin Functions table on page 14
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• Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Completeness • Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. • Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness • Electrical Characteristics - Added second Output High Voltage line to table; completeness. • Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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• Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B • Added x72 Pinout.
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
New
Types of Changes Page;Revisions;Reason Format or Content
• Added 3.3 V references to entire document • Updated Operating Conditions table • Updated JTAG section • Updated Operating Currents table and added note • Updated Boundary Scan Chain table • Updated table on page 1; added power numbers
8162Z18_r2_10; 8162Z18_r2_11
Content
8162Z18_r2_13; 8162Z18_r2_14 8162Z18_r2_14; 8162Z18_r2_15
Content Content
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8162Z18_r2_15; 8162Z18_r2_16
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Content
8162Z18_r2_16; 8162Z18_r2_17
x1 8a nd
Content
Rev: 2.21 11/2004
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• Added parity bit references to x18 pad out and pin description table • Updated x36 pinout (DQA pins listed twice) • Updated pin description tables to match pinouts • Updated Flow Through power numbers in table on page 1 and Operating Currents table • Updated Pipeline and Flow Through numbers in AC Characteristics table • Added 165-bump BGA package, pinout, and pinout description • Removed ByteSafe pins and references • Updated AC Test Conditions table and removed Output Load 2 diagram
• Removed parity I/O bit designation from 165 BGA pinout • Updated both 209 BGA and 119 BGA pin description tables • Removed pin locations from pin description tables • Removed Preliminary banner • Removed BSR table
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8162Z18_r2_12; 8162Z18_r2_13
Content
• Updated table on page 1 • Added 119-Bump BGA Pin Description table • Created recommended operating conditions tables on pages 19 and 20 • Updated AC Electrical Characteristics table • Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) • Updated BSR table (2 and 3 changed to X (value undefined)) • Added 250 MHz speed bin • Deleted 180 MHz speed bin
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8162Z18_r2_11; 8162Z18_r2_11
Content
• Updated DQ on page 24 • Updated DQ on page 26 (Q(A3)) • Updated ID Register Contents table • Updated Operating Currents table • Updated power numbers in table on page 1 • Updated Recommended Operating Conditions table (added VDDQ references)
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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© 1999, GSI Technology
.
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
New
Types of Changes Page;Revisions;Reason Format or Content
• Removed 250 MHz and 225 MHz specs from x72 • Updated AC Characteristics table (tHZ, tOE, tOHZ equal to tKQ (PL) for 250 MHz and 225 MHz) • Added new timing diagrams • Added specific address locations to 165 BGA
Content
Content Content Content
8162Z18_r2_19; 8162Z18_r2_20 8162Z18_r2_20; 8162Z18_r2_21
• Corrected incorrect DQ designations for x36 “B” • Updated format • Updated timing diagrams • Updated truth table
Rev: 2.21 11/2004
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ed
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ew
8162Z18_r2_18; 8162Z18_r2_19
• Corrected 209 BGA pin description table (removed BW reference and replaced with ADV reference)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
De sig n
8162Z18_r2_17; 8162Z18_r2_18
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