GS8182Q18D

Preliminary GS8182Q18D-200/167/133 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 1.8 V +150/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices 18Mb Burst of 2 SigmaQuad-II SRAM 200MHz–133MHz 1.8 V VDD 1.8 V and 1.5 V I/O Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512K addressable index). SigmaRAM™ Family Overview GS8182Q18 are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2 SigmaQuad-II SRAM is a synchronous device. It employs two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are Parameter Synopsis -200 tKHKH tKHQV 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns -133 7.5 ns 0.5 ns Rev: 1.02 11/2004 1/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 1M x 18 SigmaQuad-II SRAM — Top View 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 MCL/SA (144Mb) Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/SA (36Mb) D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA 4 W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 R SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 MCL/SA (72Mb) NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI 11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch Notes: 1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb 2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 3. MCL = Must Connect Low 4. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.02 11/2004 2/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Pin Description Table Symbol SA NC R W BW0–BW1 K K C C TMS TDI TCK TDO VREF ZQ MCL D0–D17 Q0–Q17 Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Data Input Test Clock Input Test Data Output HSTL Input Reference Voltage Output Impedance Matching Input Must Connect Low Synchronous Data Inputs Synchronous Data Outputs Disable DLL when low Output Echo Clock Output Echo Clock Power Supply Isolated Output Buffer Supply Power Supply: Ground Type Input — Input Input Input Input Input Input Input Input Input Input Output Input Input — Input Output Input Output Output Supply Supply Supply Comments — — Active Low Active Low Active Low Active High Active Low Active High Active Low — — — — — — — — — Active Low — — 1.8 V Nominal 1.8 or 1.5 V Nominal — Rev: 1.02 11/2004 3/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Background Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the RAM’s bandwidth in half. A SigmaQuad-II SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad-II SRAMs support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the truth tables of the different SigmaQuad-II SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand. Alternating Read-Write Operations SigmaQuad-II SRAMs follow a few simple rules of operation. - Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port. - Read or Write data transfers in progress may not be interrupted and re-started. - R and W high always deselects the RAM. - All address, data, and control inputs are sampled on clock edges. In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details. Rev: 1.02 11/2004 4/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 SigmaQuad-II B2 SRAM DDR Read The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle. Burst of 2 Double Data Rate SigmaQuad-II SRAM Read First Read A K K Address R W BWx D C C Q CQ CQ A A+1 C C+1 E E+1 G B B+1 D D+1 F F+1 H H+1 A B C D E F G H NOP Write B Read C Write D Read E Write F Read G Write H NOP Rev: 1.02 11/2004 5/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Burst of 2 SigmaQuad-II SRAM DDR Write The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write address. A high on W causes a write port deselect cycle. Burst of 2 Double Data Rate SigmaQuad-II SRAM Write First Write A K K Address R W BWx D C C Q CQ CQ B B+1 C C+1 E E+1 G A A+1 D D+1 F F+1 H H+1 A B C D E F G H Read B Read C Write D NOP Read E Write F Read G Write H NOP Special Functions Byte Write Control Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence. Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence. Rev: 1.02 11/2004 6/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Example x18 RAM Write Sequence using Byte Write Enables Data In Sample Time Beat 1 Beat 2 BW0 0 1 BW1 1 0 D0–D8 Data In Don’t Care D9–D17 Don’t Care Data In Resulting Write Operation Byte 1 D0–D8 Written Byte 2 D9–D17 Unchanged Byte 3 D0–D8 Unchanged Byte 4 D9–D17 Written Output Register Control SigmaQuad-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM. Rev: 1.02 11/2004 7/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Example Four Bank Depth Expansion Schematic R3 W3 R2 W2 R1 W1 R0 W0 A0–An K D1–Dn Bank 0 A W R K D C C Q1–Qn CQ0 CQ1 CQ2 CQ3 CQ Q Bank 1 A W R K D C CQ Q Bank 2 A W R K D C CQ Q Bank 3 A W R K D C CQ Q Note: For simplicity BWn, NWn, K, and C are not shown. Rev: 1.02 11/2004 8/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Burst of 2 SigmaQuad-II SRAM Depth Expansion Read A Write B K K Address R1 R2 W1 W2 BWx Bank1 D Bank1 BWx Bank2 D Bank2 C Bank1 C Bank1 Q Bank1 CQ Bank1 CQ Bank1 C Bank2 C Bank2 Q Bank2 CQ Bank2 CQ Bank2 C C+1 E E+1 A A+1 G G+1 I I+1 B B+1 D D+1 F F+1 H H+1 J J+1 L L L+1 L+1 A B C D E F G H I J K L Read C Write D Read E Write F Read G Write H Read I Write J Read K Write L NOP Rev: 1.02 11/2004 9/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Burst of 2 Coherency and Pass Through Functions Because the Burst of 2 read and write commands are loaded at the same time, there may be some confusion over what constitutes “coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a write. This is true of the Burst of 2 except in one case, as is illustrated in the following diagram. If the user holds the same address value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the Burst of 2 will read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation. Burst of 2 Coherency and Pass Through Functions Dwg Rev. G K Read Write Read Write Read Write Read Write /K A B OI C OI D OO E OO F OO G OI H IO I OO Address OO /R /W /BWx DB0 DB1 6 DD0 8 DD1 2 DF0 7 DF1 1 DH0 9 DH1 3 DI0 4 D 5 C COHERENT PASS-THRU /C QA0 QA1 ? QC0 5 QC1 6 QE0 7 QE1 1 Q ? Rev: 1.02 11/2004 10/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Separate I/O Burst of 2 SigmaQuad-II SRAM Read Truth Table A K↑ (tn) X V R K↑ (tn) 1 0 Output Next State K↑ (tn) Deselect Read Q K↑ (tn+1) Hi-Z Q0 Q K↑ (tn+1½) Hi-Z Q1 Notes: 1. X = Don’t Care, 1 = High, 0 = Low, V = Valid. 2. R is evaluated on the rising edge of K. 3. Q0 and Q1 are the first and second data output transfers in a read. Separate I/O Burst of 2 SigmaQuad-II SRAM Write Truth Table A K↑ (tn + ½) V V V X X W K↑ (tn) 0 0 0 0 1 BWn K↑ (tn) 0 0 1 1 X BWn K↑ (tn + ½) 0 1 0 1 X Input Next State K ↑, K ↑ (tn), (tn + ½) Write Byte Dx0, Write Byte Dx1 Write Byte Dx0, Write Abort Byte Dx1 Write Abort Byte Dx0, Write Byte Dx1 Write Abort Byte Dx0, Write Abort Byte Dx1 Deselect D K↑ (tn) D0 D0 X X X D K↑ (tn + ½) D1 X D1 X X Notes: 1. X = Don’t Care, H = High, L = Low, V = Valid. 2. W is evaluated on the rising edge of K. 3. D0 and D1 are the first and second data input transfers in a write. 4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.). x18 Byte Write Enable (BWn) Truth Table BW0 BW1 1 0 1 0 1 1 0 0 D0–D8 Don’t Care Data In Don’t Care Data In D9–D17 Don’t Care Don’t Care Data In Data In Rev: 1.02 11/2004 11/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 State Diagram Power-Up Read NOP READ WRITE Write NOP READ WRITE READ Load New Read Address Always (Fixed) Load New Write Address Always (Fixed) WRITE READ WRITE DDR Read DDR Write Notes: 1. Internal burst counter is fixed as 1-bit linear (i.e., when first address is A0+), next internal burst address is A0+1. 2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is true for “WRITE” and “WRITE”. 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K. Rev: 1.02 11/2004 12/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature Value –0.5 to 2.9 –0.5 to VDD –0.5 to VDDQ –0.5 to VDDQ +0.5 (≤ 2.9 V max.) –0.5 to VDDQ +0.5 (≤ 2.9 V max.) +/–100 +/–100 125 –55 to 125 Unit V V V V V mA dc mA dc oC o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Supply Voltage 1.8 V I/O Supply Voltage 1.5 V I/O Supply Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol VDD VDDQ VDDQ TA TA Min. 1.7 1.7 1.4 0 –40 Typ. 1.8 1.8 1.5 25 25 Max. 1.95 1.95 1.6 70 85 Unit V V V °C °C Notes 1 1 2 2 Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O) and 1.7 V ≤ VDDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case. 2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Rev: 1.02 11/2004 13/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 HSTL I/O DC Input Characteristics Parameter DC Input Logic High DC Input Logic Low VREF DC Voltage Note: Compatible with both 1.8 V and 1.5 V I/O drivers Symbol VIH (dc) VIL (dc) VREF (dc) Min VREF + 200 Max VREF – 200 Units mV mV V Notes — — — VDDQ (min)/2 VDDQ (max)/2 HSTL I/O AC Input Characteristics Parameter AC Input Logic High AC Input Logic Low VREF Peak to Peak AC Voltage Symbol VIH (ac) VIL (ac) VREF (ac) Min VREF + 400 Max VREF – 400 5% VREF (DC) Units mV mV mV Notes 3,4 3,4 1 Notes: 1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other. 3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers. 4. See AC Input Definition drawing below. HSTL I/O AC Input Definitions VIH (ac) VREF VIL (ac) Undershoot Measurement and Timing VIH Overshoot Measurement and Timing 20% tKHKH VDD + 1.0 V VSS 50% VSS – 1.0 V 20% tKHKH 50% VDD VIL Rev: 1.02 11/2004 14/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Input Capacitance Output Capacitance Note: This parameter is sample tested. Symbol CIN COUT Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF AC Test Conditions Parameter Input high level Input low level Max. input slew rate Input reference level Output reference level Notes: Test conditions as specified with output loading as shown unless otherwise noted. Conditions VDDQ 0V 2 V/ns VDDQ/2 VDDQ/2 AC Test Load Diagram DQ 50Ω VT = VDDQ/2 RQ = 250 Ω (HSTL I/O) VREF = 0.75 V Input and Output Leakage Characteristics Parameter Input Leakage Current (except mode pins) Output Leakage Current Symbol IIL IOL Test Conditions VIN = 0 to VDD Output Disable, VOUT = 0 to VDDQ Min. –2 uA –2 uA Max 2 uA 2 uA Notes Rev: 1.02 11/2004 15/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Programmable Impedance HSTL Output Driver DC Electrical Characteristics Parameter Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Symbol VOH1 VOL1 VOH2 VOL2 Min. VDDQ/2 Vss VDDQ – 0.2 Vss Max. VDDQ VDDQ/2 VDDQ 0.2 Units V V V V Notes 1, 3 2, 3 4, 5 4, 6 Notes: 1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω). 3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V 4. Minimum Impedance mode, ZQ = VSS 5. IOH = –1.0 mA 6. IOL = 1.0 mA Operating Currents -200 Parameter Org Symbol 0°C to 70°C 460 mA 55 mA 130 mA 5 mA -167 0°C to 70°C 400 mA 45 mA 120 mA 5 mA -133 0°C to 70°C 340 mA 40 mA 115 mA 5 mA –40°C to +85°C TBD TBD TBD TBD –40°C to +85°C TBD TBD TBD TBD –40°C to +85°C TBD TBD TBD TBD Test Conditions Operating Current IDD x18 IDDQ ISB1 x18 ISBQ1 R and W ≤ VIL Max. tKHKH ≥ tKHKH Min. All other inputs VIN ≤ VIL Max. or VIN ≥ VIH Min. R and W ≥ VIH Min. tKHKH ≥ tKHKH Min. All other inputs VIN ≤ VIL Max. or VIN ≥ VIH Min. Chip Disable Current Note: Power measured with output pins floating. Rev: 1.02 11/2004 16/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 AC Electrical Characteristics Parameter K, K Clock Cycle Time C, C Clock Cycle Time K, K Clock High Pulse Width C, C Clock High Pulse Width K, K Clock Low Pulse Width C, C Clock Low Pulse Width K to K High C to C High tKC Variable K, K Clock High to C, C Clock High Address Input Setup Time Address Input Hold Time Control Input Setup Time Control Input Hold Time Data Input Setup Time Data Input Hold Time K, K Clock High to Data Output Valid C, C Clock High to Data Output Valid K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold K Clock High to Data Output Low-Z C Clock High to Data Output Low-Z K Clock High to Data Output High-Z C Clock High to Data Output High-Z K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid K, K Clock High to Echo Clock Invalid C, C Clock High to Echo Clock Invalid C, CQ High to Output Valid C, CQ High to Output Invalid Symbol tKHKH tCHCH tKHKL tCHCL tKLKH tCLCH tKHKH tKCVar tKHCH tAVKH tKHAX tBVKH tKHBX tDVKH tKHDX tKHQV tCHQV tKHQX tCHQX tKHQX1 tCHQX1 tKHQZ tCHQZ tKHCQV tCHCQV tKHCQX tCHCQX tCQHQV tCQHQX -200 Min 5.0 2.0 2.0 2.2 0.2 0 0.4 0.4 0.4 0.4 0.4 0.4 — –0.45 –0.45 — — –0.45 — –0.35 Max 7.88 — — 2.75 — 2.3 — — — — — — 0.45 — — 0.45 0.45 — 0.35 — Min 6.0 2.4 2.4 2.7 0.2 0 0.5 0.5 0.5 0.5 0.5 0.5 — –0.5 –0.5 — — –0.5 — –0.4 -167 Max 7.88 — — 3.3 — 2.8 — — — — — — 0.5 — — 0.5 0.5 — 0.4 — Min 7.5 3.0 3.0 3.38 0.2 0 0.5 0.5 0.5 0.5 0.5 0.5 — –0.5 –0.5 — — –0.5 — –0.4 -133 Max 8.40 — — 4.13 — 3.5 — — — — — — 0.5 — — 0.5 0.5 — 0.4 — Units ns ns ns ns 0.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2,3 2,3 2 2 2 2 1 1 — Notes Notes: 1. These parameters apply to control inputs R and W. 2. These parameters are guaranteed by design and characterization. Not 100% tested. 3. These parameters are measured at ±50mV from steady state voltage. 4. tKHKH Max is specified by tKHKH Min. tCHCH Max is specified by tCHCH Min. Rev: 1.02 11/2004 17/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 K and K Controlled Read-Write-Read Timing Diagram Read A Write B KHKH K NOP KHKL KLKH Read C Read D Write E Write F Read G Write H NOP KHKHbar K AVKH Address A B C KHAX D E F G H BVKH R KHBX KHBX KHBX BVKH W BVKH BWx DVKH D B B+1 KHDX E E+1 F F+1 H H+1 KHCQV KHCQX CQ KHCQV KHCQX CQ KHQX1 Q A A+1 KHQX C KHQV C+1 D D+1 KHQZ G Rev: 1.02 11/2004 18/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 C and C Controlled Read-Write-Read Timing Diagram Read A Write B KHKH K NOP KHKL KLKH Write C Read D Write E Read F Write G Read H NOP KHKHbar K AVKH KHAX Address A B C D E F G H BVKH KHBX R BVKH KHBX W BVKH D1 KHBX KHDX B+1 C C+1 E E+1 G G+1 DVKH D B KHKL KHKH C KLKH KHKHbar C CHQX1 Q A A+1 CHQZ CHQV D D+1 CHQX F F+1 CHCQV CHCQX CQ CHCQV CHCQX CQ JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDD. Rev: 1.02 11/2004 19/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up. JTAG Port Registers Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.02 11/2004 20/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 JTAG TAP Block Diagram · · · 108 · · · · · · · 2 Boundary Scan Register 1 0 Bypass Register 210 0 Instruction Register TDI ID Code Register 31 30 29 TDO · ··· 210 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents GSI Technology JEDEC Vendor ID Code Bit # x36 x18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X 0 0 0 0 0 0 X X 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 011011001 0 011011001 Presence Register 0 1 1 Rev: 1.02 11/2004 21/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 1 Update IR 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.02 11/2004 22/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.02 11/2004 23/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD RFU RFU BYPASS Code 000 001 010 011 100 101 110 111 Description Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Do not use this instruction; Reserved for Future Use. Do not use this instruction; Reserved for Future Use. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 1 1 1 1 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.02 11/2004 24/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ VILJ IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 0.6 * VDD –0.3 –300 –1 –1 1.7 — VDDQ – 100 mV — Max. VDD +0.3 0.3 * VDD 1 100 1 — 0.4 — 100 mV Unit Notes V V uA uA uA V V V V 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9 Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Notes: 1. Distributed scope and test jig capacitance. 2. Test conditions as shown unless otherwise noted. Symbol VIH/VIL TR/TF Min 1.3/0.5 1.0/1.0 0.9 Unit V ns V Rev: 1.02 11/2004 25/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 JTAG Port Timing Diagram tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time SRAM Input Setup Time SRAM Input Hold Time Clock Low to Output Valid Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV Min. 50 20 20 5 5 5 5 5 5 0 Max — — — — — — — — — 10 Unit ns ns ns ns ns ns ns ns ns ns Rev: 1.02 11/2004 26/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Package Dimensions—165-Bump FPBGA (Package D; Variation 3) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.44~0.64 (165x) A1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1.0 10.0 1.0 15±0.05 14.0 A 0.53 REF 0.35 C 1.0 1.0 0.20 C B 0.20(4x) 13±0.05 Rev: 1.02 11/2004 0.36~0.46 1.40 MAX. 0.36 REF C SEATING PLANE 27/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8182Q18D-200/167/133 Ordering Information—GSI SigmaQuad-II SRAM Org 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 1M x 18 Part Number1 GS8182Q18D-200 GS8182Q18D-167 GS8182Q18D-133 GS8182Q18D-200I GS8182Q18D-167I GS8182Q18D-133I Type SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM SigmaQuad-II SRAM Package 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) 1 mm Pitch, 165-Pin BGA (var. 3) Speed (MHz) 200 167 133 200 167 133 TA3 C C C I I I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS818x36D-200T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. SigmaQuad-II Revision History File Name 8182Qxx_r1 8182Qxx_r1; 8182Qxx_r1_01 8182Qxx_r1_01; 8182Qxx_r1_02 Content Content/Format Format/Content Description of changes Creation of datasheet • Updated AC Specs • Removed x36 configuration • Updated Format • Removed 250 MHz speed bin • Removed x36 configuration • Updated Format • Removed erroneous speed bins • Updated Read description • Updated timing diagrams • Corrected erroneous VDD information in pin description table • Deleted erroneous sentent in FLXDrive section 8182Qxx_r1_01; 8182Qxx_r1_02 Content/Format 8182Qxx_r1_02; 8182Qxx_r1_03 Content Rev: 1.02 11/2004 28/28 © 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.