GS82032AT-133I

GS82032AT-180/166/150/133/100/66/4/5/6 TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC standard 100-lead TQFP package • Pb-Free 100-lead TQFP package available 64K x 32 2Mb Synchronous Burst SRAM 180 MHz–66 MHz 3.3 V VDD 3.3 V and 2.5 V I/O counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output Register can be controlled by the user via the FT mode pin (Pin 14 in the TQFP). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS82032A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS82032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. Functional Description Applications The GS82032A is a 2,097,152-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 tCycle tKQ IDD tCycle tKQ IDD -180 5.5 ns 3.2 ns 155 mA 9.1 ns 8 ns 100 mA -166 6 ns 3.5 ns 140 mA 10 ns 8.5 ns 90 mA -150 6.6 ns 3.8 ns 130 mA 10.5 ns 9 ns 85 mA -133 (-4) 7.5 ns 4 ns 115 mA 12 ns 10 ns 80 mA -100 (-5) 10 ns 5 ns 90 mA 15 ns 12 ns 65 mA -66 (-6) 12.5 ns 6 ns 65 mA 20 ns 18 ns 50 mA Rev: 1.12 10/2004 1/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 GS82032A 100-Pin TQFP Pinout NC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC FT VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 64K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC Rev: 1.12 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC 2/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 TQFP Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD NC BW BA , BB BC , BD CK GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ I I I I I I I I I I I I I I I I Type I I I/O Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins No Connect Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply Rev: 1.12 10/2004 3/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 GS82032A Block Diagram A0–An Register D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 32 4 32 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E2 E3 Register D Q Register D Q FT G Power Down Control DQx1–DQx8 ZZ Rev: 1.12 10/2004 4/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name LBO FT ZZ State L H or NC L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There are pull-up devices on LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Linear Burst Sequence A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10 1st address 2nd address 3rd address 4th address Interleaved Burst Sequence A[1:0] 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.12 10/2004 5/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Byte Write Truth Table Function Read Read Write byte A Write byte B Write byte C Write byte D Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. Rev: 1.12 10/2004 6/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X E2 X F F T T T X X X X X X X ADSP ADSC X L H L H H H X H X H X H L X L X L L H H H H H H H ADV X X X X X X L L L L H H H W3 X X X X F T F F T T F F T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.12 10/2004 7/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.12 10/2004 8/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.12 10/2004 9/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to VDD –0.5 to 6 –0.5 to VDDQ+0.5 (≤ 4.6 V max.) –0.5 to VDD+0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V V mA mA W oC o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Symbol VDD VDDQ VIH VIL TA Min. 3.135 2.375 1.7 –0.3 0 Typ. 3.3 2.5 — — 25 Max. 3.6 VDD VDD+0.3 0.8 70 Unit V V V V °C Notes 1 1 2 2 3 TA –40 25 85 °C 3 Ambient Temperature (Industrial Range Versions) Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC. Rev: 1.12 10/2004 10/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Undershoot Measurement and Timing VIH VDD +- 2.0 V VSS 50% VSS – 2.0 V 20% tKC VIL 50% VDD Overshoot Measurement and Timing 20% tKC Capacitance (TA = 25°C, f = 1 MHZ, VDD = 3.3 V) Parameter Control Input Capacitance Input Capacitance Output Capacitance Note: This parameter is sample tested. Symbol CI CIN COUT Test conditions VDD = 3.3 V VIN = 0 V VOUT = 0 V Typ. 3 4 6 Max. 4 5 7 Unit pF pF pF AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VT = 1.25 V * Distributed Test Jig Capacitance Output Load 2 2.5 V 30pF* DQ 5pF* 225Ω 225Ω Rev: 1.12 10/2004 11/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IINZZ IINM IOL VOH VOH VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –4 mA, VDDQ = 2.375 V IOH = –4 mA, VDDQ = 3.135 V IOL = 4 mA Min –1 uA –1 uA –1 uA –300 uA –1 uA –1 uA 1.7 V 2.4 V Max 1 uA 1 uA 300 uA 1 uA 1 uA 1 uA 0.4 V Rev: 1.12 10/2004 12/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Operating Currents -180 Test Conditions Symbol 0 to 70°C 155 100 10 35 25 30 25 30 25 30 20 25 40 30 35 30 35 30 35 25 20 15 10 15 10 15 10 15 10 15 30 25 105 90 95 85 90 80 85 65 70 50 10 25 20 160 140 145 130 135 115 120 90 95 65 70 55 15 30 25 –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Unit -166 -150 -133 -100 -66 Rev: 1.12 10/2004 IDD Pipeline IDD Flow Through ISB Flow Through IDD Pipeline IDD Flow Through mA mA mA mA mA Parameter Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open Standby Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL 13/22 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 © 2000, GSI Technology GS82032AT-180/166/150/133/100/66/4/5/6 AC Electrical Characteristics Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ1 tKC tKQ tKQX tLZ1 tKH tKL tHZ 1 -180 Min 5.5 — 1.5 1.5 9.1 — 3 3 1.3 1.5 1.5 — 0 — 1.5 0.5 Max — 3.2 — — — 8 — — — — 3.2 3.2 — 3.2 — — — — — 6 — -166 Min Max — 3.5 — — — 8.5 — — — — 3.5 3.5 — 3.5 — — — — — -150 Min 6.6 — 1.5 1.5 10.5 — 3 3 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 Max — 3.8 — — — 9 — — — — 3.8 3.8 — 3.8 — — — — — -133 Min 7.5 — 1.5 1.5 12 — 3 3 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 Max — 4 — — — 10 — — — — 4 4 — 4 — — — — — 10 — -100 Min Max — 5 — — — 12 — — — — 5 5 — 5 — — — — — -66 Min 12.5 — 1.5 1.5 20 — 3 3 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 Max — 6 — — — 18 — — — — 6 6 — 6 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 1.5 10 — 3 3 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 1.5 1.5 15 — 3 3 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 tOE tOLZ1 tOHZ1 tS tH tZZS 2 5 1 20 tZZH2 tZZR Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.12 10/2004 14/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Pipeline Mode Timing Begin Read A Cont Cont Deselect Write B Single Write tKL tKH tKC Read C Read C+1 Read C+2 Read C+3 Cont Burst Read Deselect Single Read CK ADSP tS tH ADSC tS ADV tS tH A0–An A B C ADSC initiated read tH tS GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa–DQd tOHZ Q(A) D(B) E2 and E3 only sampled with ADSP and ADSC E1 masks ADSP Deselected with E1 tH tKQ tH tLZ Q(C) Q(C+1) Q(C+2) tKQX tHZ Q(C+3) Rev: 1.12 10/2004 15/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Flow Through Mode Timing Begin Read A Cont tKL tKH Cont tKC Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect CK ADSP tS tH ADSC tS tH ADV tS tH A0–An A B C Fixed High tS tH ADSC initiated read tS tH GW tS tH BW tS tH Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tH tS tOE DQa–DQd Q(A) Deselected with E1 E2 and E3 only sampled with ADSC tOHZ D(B) tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) tHZ tKQX Rev: 1.12 10/2004 16/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Sleep Mode Timing tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.12 10/2004 17/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 GS82032A Output Driver Characteristics 60 Pull Down Drivers 40 20 VDDQ I Out 0 I Out (mA) VOut VSS -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Dow n) VDDQ - V Out (Pull Up) 3.6V PD LD 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD Rev: 1.12 10/2004 18/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 TQFP Package Drawing (Package T) L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c Pin 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — 0.45 — 0.10 1.40 0.30 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 0.75 — 0.10 L1 e b D D1 A1 Y A2 0° — 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.12 10/2004 19/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Ordering Information for GSI Synchronous Burst RAMs Org 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 Part Number1 GS82032AT-180 GS82032AT-166 GS82032AT-150 GS82032AT-133 GS82032AT-100 GS82032AT-66 GS82032AT-4 GS82032AT-5 GS82032AT-6 GS82032AT-180I GS82032AT-166I GS82032AT-150I GS82032AT-133I GS82032AT-100I GS82032AT-66I GS82032AT-4I GS82032AT-5I GS82032AT-6I GS82032AGT-180 GS82032AGT-166 GS82032AGT-150 GS82032AGT-133 GS82032AGT-100 GS82032AGT-66 GS82032AGT-4 GS82032AGT-5 GS82032AGT-6 GS82032AGT-180I GS82032AGT-166I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Speed2 TA (MHz/ns) 3 180/8 166/8.5 150/9 133/10 100/12 66/18 133/10 100/12 66/18 180/8 166/8.5 150/9 133/10 100/12 66/18 133/10 100/12 66/18 180/8 166/8.5 150/9 133/10 100/12 66/18 133/10 100/12 66/18 180/8 166/8.5 C C C C C C C C C I I I I I I I I I C C C C C C C C C I I Status 64K x 32 GS82032AGT-150I Pipeline/Flow Through Pb-free TQFP 150/9 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.12 10/2004 20/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Ordering Information for GSI Synchronous Burst RAMs Org 64K x 32 64K x 32 64K x 32 64K x 32 64K x 32 Part Number1 GS82032AGT-133I GS82032AGT-100I GS82032AGT-66I GS82032AGT-4I GS82032AGT-5I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Speed2 TA (MHz/ns) 3 133/10 100/12 66/18 133/10 100/12 I I I I I Status 64K x 32 GS82032AGT-6I Pipeline/Flow Through Pb-free TQFP 66/18 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS82032AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.12 10/2004 21/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT-180/166/150/133/100/66/4/5/6 Revision History DS/DateRev. Code: Old; New GS82032 Rev 1.03 2/ 2000D;GS820321.04 3/ 2000E GS820321.04 3/2000E; GS82032A_r1_05 Types of Changes Revisions Format or Content Content • First Release of A version. Added “A” Version to 82032T/Q, 820E32TQ, and 820H32TQ • Updated ADSC in timing diagrams on pages 16 and 18 • Added 200 MHz, 180 MHz, and 166 MHz speed bins (all references updated) • Deleted 150 MHz, 138 MHz, and 66 MHz speed bins (all references deleted) • Deleted BGA reference in “Flow Through/Pipeline Reads” on page 1 • Updated entire datasheet with new standards • Updated table on page 1 • Updated Operating Currents table on page 12 • Updated Electrical Characteristics table on page 13 • Updated format to comply with Technical Publications standards • Added the following part numbers to the Ordering Information table on page 22: – GS82032AT-4 – GS82032AT-6 – GS82032AT-4I – GS82032AT-6I – GS82032AQ-4 – GS82032AQ-6 – GS82032AQ-4I – GS82032AQ-6I • Removed all references to 200 MHz parts (no longer active) • Complete rewrite of datasheet in order to reflect parts available • Reactiviated 180 MHz speed bin • Updated format • Added Pb-free information for TQFP Content 82032A_r1_05; 82032A_r1_06 Content 82032A_r1_06; 82032A_r1_07 Content 82032A_r1_07; 82032A_r1_08 Content 82032A_r1_08; 82032A_r1_09 82032A_r1_09; 82032A_r1_10 82032A_r1_10; 82032A_r1_11 82032A_r1_11; 82032A_r1_12 Content Content Content Content Rev: 1.12 10/2004 22/22 © 2000, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.