GS832418C-150

Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 119- and 209-Pin BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable (x36 and x72) • Dual Cycle Deselect only (x18) • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x36/x72 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119- and 209-bump BGA package 2M x 18, 1M x 36, 512K x 72 36Mb S/DCD Sync Burst SRAMs 250 MHz–133MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS832436(B/C) and the GS832472(C) are SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAMs. The GS832418(B/C) is a DCD-only SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure the x36 or x72 versions of this SRAM for either mode of operation using the SCD mode input. Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V tKQ tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) -250 -225 -200 -166 -150 -133 Unit 2.3 2.5 3.0 3.5 3.8 4.0 ns 4.0 4.4 5.0 6.0 6.6 7.5 ns 365 560 660 360 550 640 6.0 7.0 235 300 350 235 300 340 335 510 600 330 500 590 6.5 7.5 230 300 350 230 300 340 305 460 540 305 460 530 7.5 8.5 210 270 300 210 270 300 265 400 460 260 390 450 8.5 10 200 270 300 200 270 300 245 370 430 240 360 420 10 10 195 270 300 195 270 300 215 330 380 215 330 370 11 15 150 200 220 145 190 220 mA mA mA mA mA mA ns ns mA mA mA mA mA mA Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. 2.5 V FLXDrive™ The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Functional Description Applications The GS832418/36/72 is a 37,748,736-bit high performance 2-die synchronous SRAM module with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated Rev: 1.00 10/2001 1/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology). Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832472B Pad Out 209-Bump BGA—Top View 1 A B C D E F G H J K L M N P R T U V W DQG5 DQG6 DQG7 DQG8 DQPG9 DQC4 DQC3 DQC2 DQC1 NC DQH1 DQH2 DQH3 DQH4 DQPD9 DQD8 DQD7 DQD6 DQD5 2 DQG1 DQG2 DQG3 DQG4 DQPC9 DQC8 DQC7 DQC6 DQC5 NC DQH5 DQH6 DQH7 DQH8 DQPH9 DQD4 DQD3 DQD2 DQD1 3 A15 BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A9 TMS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A14 A8 TDI 5 ADSP NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A13 A7 A3 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A12 A1 A0 7 ADV A16 NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A11 A6 A2 8 E3 BB BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A10 A5 TDO 9 A17 BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A18 A4 TCK 10 DQB1 DQB2 DQB3 DQB4 DQPF9 DQF8 DQF7 DQF6 DQF5 NC DQA5 DQA6 DQA7 DQA8 DQPA9 DQE4 DQE3 DQE2 DQE1 11 DQB5 DQB6 DQB7 DQB8 DQPB9 DQF4 DQF3 DQF2 DQF1 NC DQA1 DQA2 DQA3 DQA4 DQPE9 DQE8 DQE7 DQE6 DQE5 A B C D E F G H J K L M N P R T U V W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.00 10/2001 2/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832436C Pad Out 209-Bump BGA—Top View 1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC DQC4 DQC3 DQC2 DQC1 NC NC NC NC NC DQPD9 DQD8 DQD7 DQD6 DQD5 2 NC NC NC NC DQPC9 DQC8 DQC7 DQC6 DQC5 NC NC NC NC NC NC DQD4 DQD3 DQD2 DQD1 3 A15 BC NC VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A9 TMS 4 E2 NC BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A14 A8 TDI 5 ADSP A19 NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A13 A7 A3 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL SCD ZZ VDD LBO A12 A1 A0 7 ADV A16 NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A11 A6 A2 8 E3 BB NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A10 A5 TDO 9 A17 NC BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A18 A4 TCK 10 DQB1 DQB2 DQB3 DQB4 NC NC NC NC NC NC DQA5 DQA6 DQA7 DQA8 DQPA9 NC NC NC NC 11 DQB5 DQB6 DQB7 DQB8 DQPB9 NC NC NC NC NC DQA1 DQA2 DQA3 DQA4 NC NC NC NC NC A B C D E F G H J K L M N P R T U V W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.00 10/2001 3/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418C Pad Out 209-Bump BGA—Top View 1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC DQB4 DQB3 DQB2 DQB1 NC NC NC NC NC NC NC NC NC NC 2 NC NC NC NC DQPB9 DQB8 DQB7 DQB6 DQB5 NC NC NC NC NC NC NC NC NC NC 3 A15 BB NC VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A9 TMS 4 MCH NC NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A14 A8 TDI 5 ADSP A19 NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A13 A7 A3 6 ADSC BW E1 G VDD ZQ MCH MCL MCL MCL FT MCL MCL ZZ VDD LBO A12 A1 A0 7 ADV A16 A20 GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A11 A6 A2 8 MCL NC NC NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A10 A5 TDO 9 A17 NC BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A18 A4 TCK 10 NC NC NC NC NC NC NC NC NC NC DQA5 DQA6 DQA7 DQA8 DQPA9 NC NC NC NC 11 NC NC NC NC NC NC NC NC NC NC DQA1 DQA2 DQA3 DQA4 NC NC NC NC NC A B C D E F G H J K L M N P R T U V W 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Rev: 1.00 10/2001 4/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 209-Bump BGA Pin Description Pin Location W6, V6 W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6, U5, U4, A3, B7, A9, U9 B5 C7 L11, M11, N11, P11, L10, M10, N10, P10, R10 A10, B10, C10, D10, A11, B11, C11, D11, E11 J1, H1, G1, F1, J2, H2, G2, F2, E2 W2, V2, U2, T2, W1, V1, U1, T1, R1 W10, V10, U10, T10, W11, V11, U11, T11, R11 J11, H11, G11, F11, J10, H10, G10, F10, E10 A2, B2, C2, D2, A1, B1, C1, D1, E1 L1, M1, N1, P1, L2, M2, N2, P2, R2 L11, M11, N11, P11, L10, M10, N10, P10, R10 A10, B10, C10, D10, A11, B11, C11, D11, E11 J1, H1, G1, F1, J2, H2, G2, F2, E2 W2, V2, U2, T2, W1, V1, U1, T1, R1 L11, M11, N11, P11, L10, M10, N10, P10, R10 J1, H1, G1, F1, J2, H2, G2, F2, E2 C9, B8 B3, C4 C8, B9, B4, C3 B5 C7 W10, V10, U10, T10, W11, V11, U11, T11, R11 J11, H11, G11, F11, J10, H10, G10, F10, E10 A2, B2, C2, D2, A1, B1, C1, D1, E1 L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9, B4, C3 B3, C4 C5, D4, D5, D8, K1, K2, K4, K8, K9, K10, K11, T4, T5, T7, T8, U3 K3 D7 C6 A8 A4 Rev: 1.00 10/2001 Symbol A0, A1 An A19 A20 DQA1–DQA9 DQB1–DQB9 DQC1–DQC9 DQD1–DQD9 DQE1–DQE9 DQF1–DQF9 DQG1–DQG9 DQH1–DQH9 DQA1–DQA9 DQB1–DQB9 DQC1–DQC9 DQD1–DQD9 DQA1–DQA9 DQB1–DQB9 BA, BB BC,BD BE, BF, BG,BH NC NC Type I I I I Description Address field LSBs and Address Counter Preset Inputs. Address Inputs Address Inputs (x36/x18 Versions) Address Inputs (x18 Version) I/O Data Input and Output pins (x72 Version) I/O Data Input and Output pins (x36 Version) I/O I I I — — Data Input and Output pins (x18 Version) Byte Write Enable for DQA, DQB I/Os; active low Byte Write Enable for DQC, DQD I/Os; active low (x72/x36 Versions) Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low (x72 Version) No Connect (x72 Version) No Connect (x72/x36 Versions) NC — No Connect (x36/x18 Versions) NC NC CK GW E1 E3 E2 5/46 — — I I I I I No Connect (x18 Version) No Connect Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active low (x72/x36 Versions) Chip Enable; active high (x72/x36 Versions) © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 209-Bump BGA Pin Description Pin Location D6 A7 A5, A6 P6 L6 T6 N6 G6 A4 H6, J6, K6, M6 A8, N6 B6 F6 W3 W4 W8 W9 E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9, L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 Symbol G ADV ADSP, ADSC ZZ FT LBO SCD MCH MCH MCL MCL BW ZQ TMS TDI TDO TCK VDD VSS VDDQ Type I I I I I I I I I Description Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control ( x72/x36 Versions) Must Connect High Must Connect High (x18 version) Must Connect Low Must Connect Low (x18 version) I I I I O I I I I Byte Enable; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply Rev: 1.00 10/2001 6/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832436B Pad Out 119-Bump BGA—Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQ 2 A6 A18 A5 DQPC9 DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD7 DQD8 DQPD9 A2 NC TMS 3 A7 A4 A3 VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A10 TDI 4 ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD A11 TCK 5 A8 A15 A14 VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A12 TDO 6 A9 A17 A16 DQPB9 DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 DQPA9 A13 A19 NC 7 VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA4 DQA3 VDDQ DQA2 DQA1 NC ZZ VDDQ A B C D E F G H J K L M N P R T U 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch Rev: 1.00 10/2001 7/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418B Pad Out 119-Bump BGA—Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ 2 A6 A18 A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQPB9 A2 A10 TMS 3 A7 A4 A3 VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A11 TDI 4 ADSP ADSC VDD ZQ E1 G ADV GW VDD CK VSS BW A1 A0 VDD A20 TCK 5 A8 A15 A14 VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A12 TDO 6 A9 A17 A16 DQPA9 NC DQA7 NC DQA5 VDD NC DQA3 NC DQA2 NC A13 A19 NC 7 VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ NC DQA1 NC ZZ VDDQ A B C D E F G H J K L M N P R T U 7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch Rev: 1.00 10/2001 8/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36 119-Bump BGA Pin Description Pin Location P4, N4 R2, C3, B3, C2, A2, A3, A5, A6, T3, T5, R6, C5, B5, C6, B6, B2 T4, T6 T2 T2, T6, T4 K7, L7, N7, P7, K6, L6, M6, N6 H7, G7, E7, D7, H6, G6, F6, E6 H1, G1, E1, D1, H2, G2, F2, E2 K1, L1, N1, P1, K2, L2, M2, N2 P6, D6, D2, P2 L5, G5, G3, L3 P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 L5, G3 B1, C1, R1, T1, U6, B7, C7, J3, J5, R7 P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3 K4 M4 H4 E4 F4 G4 A4, B4 T7 R5 R3 D4 L4 U2 Symbol A0, A1 An An NC An DQA1–DQA8 DQB1–DQB8 DQC1–DQC8 DQD1–DQD8 DQA9, DQB9, DQC9, DQD9 BA, BB, BC, BD DQA1–DQA9 DQB1–DQB9 BA, BB NC NC CK BW GW E1 G ADV ADSP, ADSC ZZ FT LBO ZQ SCD TMS Type I I Description Address field LSBs and Address Counter Preset Inputs Address Inputs Address Input (x36 Version) — I I/O No Connect (x36 Version) Address Input (x18 Version) Data Input and Output pins. (x36 Version) I/O I I/O I — — I I I I I I I I I I I I I Data Input and Output pins. (x36 Version) Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) Data Input and Output pins (x18 Version) Byte Write Enable for DQA, DQB I/Os; active low (x18 Version) No Connect No Connect (x18 Version) Clock Input Signal; active high Byte Write—Writes all enabled bytes; active low Global Write Enable—Writes all bytes; active low Chip Enable; active low Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Single Cycle Deselect/Dual Cyle Deselect Mode Control (x36 version) Scan Test Mode Select Rev: 1.00 10/2001 9/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36 119-Bump BGA Pin Description Pin Location U3 U5 U4 J2, C4, J4, R4, J6 D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 L4 A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 Symbol TDI TDO TCK VDD VSS VSS VDDQ Type I O I I I I I Description Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground I/O and Core Ground Output driver power supply Rev: 1.00 10/2001 10/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 Block Diagram Register A0–An D Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1 LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q 36 D 36 Register D BB Q 4 Register D BC Q Q Register D Register Q Register D D BD Q Register 36 36 D Q Register E1 D Q 36 Register D Q FT G Power Down Control 36 SCD ZZ DQx0–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.00 10/2001 11/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418 Die Layout Inputs TDI Die A x18 16Mb TDO TDI Die B x18 16Mb TDO 18 I/Os GS832436 Die Layout Inputs TDI Die A x18 16Mb TDO TDI Die B x18 16Mb TDO 18 I/Os 18 I/Os GS832472 Die Layout Inputs TDI Die A x36 32Mb TDO TDI Die B x36 32Mb TDO 36 I/Os 36 I/Os Rev: 1.00 10/2001 12/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control Pin Name LBO FT ZZ SCD ZQ State L H L H or NC L or NC H L H or NC L H or NC Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance) Note: There are pull-up devices on the ZQ, SCD and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 01 10 11 00 10 11 00 01 11 00 01 10 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.00 10/2001 13/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x36 version. Rev: 1.00 10/2001 14/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Synchronous Truth Table (x72 and x36 209-Bump BGA) Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst State Address Used Diagram Key5 None None None External External External Next Next Next Next Current Current Current Current X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X H E2 X F F T T T X X X X X X X X ADSP X L H L H H H X H X H X H X ADSC L X L X L L H H H H H H H H ADV X X X X X X L L L L H H H H W3 X X X X F T F F T T F F T T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D D Note: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 10/2001 15/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Synchronous Truth Table (x18 209-Bump BGA and x36/x18 119-Bump BGA) State Operation Address Used Diagram E1 ADSP ADSC 5 Key Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst None External External External Next Next Next Next Current Current Current Current X R R W CR CR CW CW H L L L X H X H X H X H X L H H H X H X H X H X L X L L H H H H H H H H ADV X X X X L L L L H H H H W3 X X F T F F T T F F T T DQ4 High-Z Q Q D Q Q D D Q Q D D Notes: 1. X = Don’t Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.00 10/2001 16/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.00 10/2001 17/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.00 10/2001 18/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to 4.6 –0.5 to 6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V V mA mA W o C oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.00 10/2001 19/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 VDDQ3 VDDQ2 Min. 3.0 2.3 3.0 2.4 Typ. 3.3 2.5 3.3 2.5 Max. 3.6 2.7 3.6 2.7 Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 1.7 –0.3 1.7 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 0.6*VDD –0.3 0.6*VDD –0.3 Typ. — — — — Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.00 10/2001 20/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing VIH Overshoot Measurement and Timing 20% tKC VDD + 2.0 V VSS 50% VSS – 2.0 V 20% tKC 50% VDD VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance (x36/x72) Input/Output Capacitance (x18) Note: These parameters are sample tested. Symbol CIN CI/O CI/O Test conditions VIN = 0 V VOUT = 0 V VOUT = 0 V Typ. 6.5 6 8.5 Max. 7.5 7 9.5 Unit pF pF pF Package Thermal Characteristics Rating Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Layer Board single four — Symbol RΘJA RΘJA RΘJC Max 40 24 9 Unit °C/W °C/W °C/W Notes 1,2 1,2 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1.00 10/2001 21/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VT = 1.25 V * Distributed Test Jig Capacitance Output Load 2 2.5 V 30pF* DQ 5pF* 225Ω 225Ω DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ and PE Input Current FT, SCD, ZQ, DP Input Current Output Leakage Current (x36/x72) Output Leakage Current (x18) Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –2 uA –1 uA –1 uA –100 uA –1 uA –1 uA –2 uA 1.7 V 2.4 V — Max 2 uA 1 uA 100 uA 1 uA 1 uA 1 uA 2 uA — — 0.4 V Rev: 1.00 10/2001 22/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Operating Currents -250 Mode Symbol 0 to 70°C Unit 580 80 mA mA - 225 0 to 70°C 530 70 340 40 470 40 280 20 315 20 200 10 530 60 310 30 470 30 280 20 315 15 300 20 330 15 490 30 430 30 250 20 290 15 330 30 270 30 290 30 450 30 270 20 305 15 550 60 480 50 500 50 410 40 270 30 370 20 250 20 250 10 215 10 175 10 190 10 175 10 190 10 430 40 290 30 390 20 270 20 265 10 330 20 290 15 305 15 250 15 265 15 230 15 175 10 380 40 270 30 340 20 250 20 230 10 300 20 250 20 270 20 350 20 270 20 250 20 270 20 245 15 190 10 400 40 290 30 360 20 270 20 245 10 490 40 430 30 450 30 370 30 390 30 340 30 360 30 310 20 180 20 205 10 135 10 340 30 200 20 310 20 180 10 205 10 330 20 200 20 220 10 150 10 360 30 220 20 330 20 200 10 220 10 330 40 270 30 290 30 270 30 290 30 270 30 290 30 200 20 220 20 550 70 480 60 500 60 410 50 430 50 380 50 400 50 340 40 360 40 –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85° C 0 to 70° C – 40 to 85°C 0 to 70°C –40 to 85°C - 200 - 166 -150 - 133 Parameter Test Conditions – 40 to 85°C 560 80 330 40 540 40 300 20 360 20 215 10 600 60 330 30 540 30 300 20 360 15 215 10 Pipeline ( x72) Flow Through IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ 310 30 520 30 280 20 345 15 200 10 40 40 IDD IDD 170 120 IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB ISB 580 60 200 10 345 20 280 20 520 40 Pipeline ( x36) Flow Through Pipeline ( x18) Flow Through Pipeline ( x72) Flow Through Pipeline ( x36) Flow Through Pipeline ( x18) Flow Through Pipeline — Flow Through Pipeline — Flow Through IDD 310 40 Rev: 1.00 10/2001 IDD IDDQ mA mA mA mA mA mA mA mA mA Operating Current 3 .3 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open 23/46 200 10 60 60 180 130 40 40 160 120 215 10 60 60 170 130 175 10 40 40 150 100 190 10 60 60 160 110 Operating Current Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 2 .5 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open 175 10 40 40 130 100 190 10 60 60 140 110 175 10 40 40 120 100 190 10 60 60 130 110 135 5 40 40 100 90 150 5 60 60 110 100 mA mA mA mA mA S ta n d b y Current ZZ ≥ VDD – 0.2 V Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) © 2001, Giga Semiconductor, Inc. Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) AC Electrical Characteristics Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ 1 -250 Min 4.0 — 1.5 1.5 7.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 100 Max — 2.3 — — — 6.0 — — — — 2.3 2.3 — 2.3 — — — — — -225 Min 4.4 — 1.5 1.5 7.5 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 100 Max — 2.5 — — — 6.0 — — — — 2.5 2.5 — 2.5 — — — — — -200 Min 5.0 — 1.5 1.5 8.5 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 100 Max — 3.0 — — — 7.5 — — — — 3.0 3.2 — 3.0 — — — — — -166 Min 6.0 — 1.5 1.5 10.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 100 Max — 3.4 — — — 8.5 — — — — 3.5 3.5 — 3.5 — — — — — -150 Min 6.7 — 1.5 1.5 10.0 — 3.0 3.0 1.5 1.7 1.5 — 0 — 1.5 0.5 5 1 100 Max — 3.8 — — — 10.0 — — — — 3.8 3.8 — 3.8 — — — — — -133 Min 7.5 — 1.5 1.5 15.0 — 3.0 3.0 1.7 2 1.5 — 0 — 1.5 0.5 5 1 100 Max — 4.0 — — — 10.0 — — — — 4.0 4.0 — 4.0 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.00 10/2001 24/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Write Cycle Timing Single Write Burst Write Write Deselected CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH ADV must be inactive for ADSP Write WR2 WR3 A0–An WR1 tS tH GW tS tH BW tS tH BA–BD tS tH WR1 WR1 WR2 WR3 WR3 E1 masks ADSP E1 E1 only sampled with ADSP or ADSC G tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D D2A D2B D2C D2D D3A DQA–DQD Hi-Z D1A Rev: 1.00 10/2001 25/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Flow Through Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0–An RD1 tS RD2 RD3 tH GW tS tH BW BA–BD tS tH E1 masks ADSP E1 tOE tOHZ G tOLZ tKQX Q1A tLZ tHZ tKQ Q2A Q2B Q2c Q2D Q3A tKQX DQA–DQD Hi-Z Rev: 1.00 10/2001 26/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Flow Through Read-Write Cycle Timing Single Read Single Write Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BA–BD tS tH WR1 E1 masks ADSP E1 tOE tOHZ G tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A Hi-Z DQA–DQD D1A Burst wrap around to it’s initial state Rev: 1.00 10/2001 27/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined SCD Read Cycle Timing Single Read Burst Read tKH tKL tKC tS tH ADSC initiated read ADSP is blocked by E inactive CK tS tH ADSP ADSC tS tH Suspend Burst ADV tS tH A0–An RD1 tS RD2 RD3 tH GW tS tH BW BWA–BWD tS tH E1 masks ADSP E1 tOE G DQA–DQD Hi-Z tOLZ Q1A tLZ tOHZ tKQX Q2A Q2B Q2c Q2D tKQX Q3A tHZ tKQ Rev: 1.00 10/2001 28/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined SCD Read-Write Cycle Timing Single Read tKL Single Write Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BWA– BWD tS tH WR1 E1 masks ADSP E1 tOE tOHZ G DQA–DQD Hi-Z tKQ Q1A tS tH D1A Q2A Q2B Q2c Q2D Rev: 1.00 10/2001 29/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0–An GW RD1 tS RD2 RD3 tH tS tH BW BA–BD tS tH E1 masks ADSP E1 tOE G tOHZ Hi-Z tOLZ Q1A tLZ tHZ tKQ tKQX Q2A Q2B Q2c Q2D tKQX Q3A DQA–DQD Rev: 1.00 10/2001 30/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Pipelined DCD Read-Write Cycle Timing Single Write Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An RD1 WR1 RD2 tS tH GW tS tH tS tH BW BA–BD tS tH WR1 E1 masks ADSP E1 tOE tOHZ G DQA–DQD Hi-Z tKQ Q1A tS tH D1A Q2A Q2B Q2c Q2D Rev: 1.00 10/2001 31/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram CK tS tH tKC tKH tKL ADSP ADSC tZZS ~ ~~~~ ~ ~~~~ ~ tZZH tZZR ZZ Snooze Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation Due to the fact that this device is built from two die, the two JTAG parts are chained together internally. The following describes the behavior of each die. Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Rev: 1.00 10/2001 32/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Rev: 1.00 10/2001 33/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram 0 Bypass Register 210 Instruction Register TDI ID Code Register 31 30 29 TDO · ··· 210 Boundary Scan Register n ······ ··· 210 TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents Presence Register 0 1 1 1 1 1 Die Revision Code Bit # x72 x36 x32 x18 x16 Not Used I/O Configuration GSI Technology JEDEC Vendor ID Code 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 011011001 0 011011001 0 011011001 0 011011001 0 011011001 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be Rev: 1.00 10/2001 34/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Rev: 1.00 10/2001 35/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.00 10/2001 36/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z Code 000 001 010 Description Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 RFU SAMPLE/ PRELOAD GSI RFU BYPASS 011 100 101 110 111 1 1 1 1 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.00 10/2001 37/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 2.0 –0.3 0.6 * VDD2 –0.3 –300 –1 –1 1.7 — VDDQ – 100 mV — Max. VDD3 +0.3 0.8 VDD2 +0.3 0.3 * VDD2 1 100 1 — 0.4 — 100 mV Unit Notes V V V V uA uA uA V V V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9 Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V DQ JTAG Port AC Test Load 50Ω VT = 1.25 V * Distributed Test Jig Capacitance 30pF* Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.00 10/2001 38/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) JTAG Port Timing Diagram tTKH TCK tTS tTH tTKL tTKC TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 — 20 20 10 10 Max — 20 — — — — Unit ns ns ns ns ns ns Rev: 1.00 10/2001 39/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) GS832418/36/72 Boundary Scan Chain Order Order x72 x36 x18 1(TBD) Bump x72 x36 x18 Notes: 1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1, PE = 0, SD = 0, ZZ = 0, FT = 1, DP = 1, and SCD = 1. 2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture. 3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control is effective after JTAG EXTEST instruction is executed. 4. 1 = no connect, internally set to logic value 1 5. 0 = no connect, internally set to logic value 0 6. X = no connect, value is undefined Rev: 1.00 10/2001 40/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 209 BGA Package Drawing 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array C A1 A aaa D D1 Side View e Bottom View E1 ∅b e Symbol A A1 ∅b c D D1 E E1 e aaa Rev 1.0 13.9 0.40 0.50 0.31 21.9 0.50 0.60 0.36 22.0 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15 14.1 Min Typ Max 1.70 0.60 0.70 0.38 22.1 Units mm mm mm mm mm mm mm mm mm mm Rev: 1.00 10/2001 41/46 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. E Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Package Dimensions—119-Pin PBGA 119-Bump BGA Package Pin 1 Corner A B C D E F G H J K L M N P R T U A 7654321 G B S D A B C D E F G H J K L M N P R T U R Top View Bottom View Package Dimensions—119-Pin PBGA Symbol A B C D E F G K R S Description Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Width of package between balls Length of package between balls Variance of Ball Height 0.65 Min. 13.9 21.9 1.73 0.60 0.50 1.16 Nom. 14.0 22.0 1.86 0.75 0.60 1.26 1.27 0.70 7.62 20.32 0.15 0.75 Max 14.1 22.1 1.99 0.90 0.70 1.36 T F E K T C Unit: mm Side View Rev: 1.00 10/2001 42/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Ordering Information for GSI Synchronous Burst RAMs Org 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 512K x 72 512K x 72 512K x 72 512K x 72 512K x 72 Part Number1 GS832418B-250 GS832418B-225 GS832418B-200 GS832418B-166 GS832418B-150 GS832418B-133 GS832418C-250 GS832418C-225 GS832418C-200 GS832418C-166 GS832418C-150 GS832418C-133 GS832436B-250 GS832436B-225 GS832436B-200 GS832436B-166 GS832436B-150 GS832436B-133 GS832436C-250 GS832436C-225 GS832436C-200 GS832436C-166 GS832436C-150 GS832436C-133 GS832472C-250 GS832472C-225 GS832472C-200 GS832472C-166 GS832472C-150 Type DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through Package 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA Speed2 (MHz/ns) 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 TA3 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 10/2001 43/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Ordering Information for GSI Synchronous Burst RAMs (Continued) Org 512K x 72 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 2M x 18 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 1M x 36 512K x 72 Part Number1 GS832472C-133 GS832418B-250I GS832418B-225I GS832418B-200I GS832418B-166I GS832418B-150I GS832418B-133I GS832418C-250I GS832418C-225I GS832418C-200I GS832418C-166I GS832418C-150I GS832418C-133I GS832436B-250I GS832436B-225I GS832436B-200I GS832436B-166I GS832436B-150I GS832436B-133I GS832436C-250I GS832436C-225I GS832436C-200I GS832436C-166I GS832436C-150I GS832436C-133I GS832472C-250I Type SCD/DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through Package 209 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 119 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA Speed2 (MHz/ns) 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 225/6.5 200/7.5 166/8.5 150/10 133/11 250/6 TA3 C I I I I I I I I I I I I I I I I I I I I I I I I I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 10/2001 44/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) Ordering Information for GSI Synchronous Burst RAMs (Continued) Org 512K x 72 512K x 72 512K x 72 512K x 72 512K x 72 Part Number1 GS832472C-225I GS832472C-200I GS832472C-166I GS832472C-150I GS832472C-133I Type SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through SCD/DCD Pipeline/Flow Through Package 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA Speed2 (MHz/ns) 225/6.5 200/7.5 166/8.5 150/10 133/11 TA3 I I I I I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832418B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00 10/2001 45/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS832418(B/C)/GS832436(B/C)/GS832472(C) 36Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 832418_r1 Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet Rev: 1.00 10/2001 46/46 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.