GS84036T-150I

GS84018/32/36T/B-180/166/150/100 TQFP, BGA Commercial Temp Industrial Temp Features • FT pin for user configurable flow through or pipelined operation. • Single Cycle Deselect (SCD) Operation. • 3.3V +10%/-5% Core power supply • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. • Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Internal Self-Timed Write cycle. • Automatic power-down for portable applications. • JEDEC standard 100-lead TQFP or 119 Bump BGA package. -180 5.5ns 3.2ns 330mA 8ns 10ns 190mA -166 6.0ns 3.5ns 310mA 8.5ns 10ns 190mA -150 6.6ns 3.8ns 275mA 10ns 10ns 190mA -100 10ns 4.5ns 190mA 12ns 15ns 140mA 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs Flow Through / Pipeline Reads 180Mhz - 100Mhz 3.3V VDD 3.3V & 2.5V I/O be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register. SCD Pipelined Reads The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available.SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Pipeline 3-1-1-1 Flow Through 2-1-1-1 tCycle tKQ IDD tKQ tCycle IDD Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Functional Description Applications The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version) high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS84018/32/36 is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA package. Core and Interface Voltages The GS84018/32/36 operates on a 3.3V power supply and all inputs/ outputs are 3.3V and 2.5V compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Controls Addresses, data I/O’s, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive edge triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not Rev: 2.05 6/2000 1/31 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS84018/32/36T/B-180/166/150/100 GS84018 100 Pin TQFP Pinout NC NC NC VDDQ VSS NC NC DQB1 DQB2 VSS VDDQ DQB3 DQB4 FT VDD NC VSS DQB5 DQB6 VDDQ VSS DQB7 DQB8 DQB9 NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G A DS C A DS P A DV A8 A9 A17 NC NC VDDQ VSS NC DQA9 DQA8 DQA7 VSS VDDQ DQA6 DQA5 VSS NC VDD ZZ DQA4 DQA3 VDDQ VSS DQA2 DQA1 NC NC VSS VDDQ NC NC NC Rev: 2.05 6/2000 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A12 A13 A14 A15 A16 2/31 © 1999, Giga Semiconductor, Inc. . GS84018/32/36T/B-180/166/150/100 GS84032 100 Pin TQFP Pinout NC DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G A DS C A DS P A DV A8 A9 NC DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 NC Rev: 2.05 6/2000 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A12 A13 A14 A15 A16 3/31 © 1999, Giga Semiconductor, Inc. . GS84018/32/36T/B-180/166/150/100 GS84036 100 Pin TQFP Pinout DQC9 DQC8 DQC7 VDDQ VSS DQC6 DQC5 DQC4 DQC3 VSS VDDQ DQC2 DQC1 FT VDD NC VSS DQD1 DQD2 VDDQ VSS DQD3 DQD4 DQD5 DQD6 VSS VDDQ DQD7 DQD8 DQD9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A6 A7 E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G A DS C A DS P A DV A8 A9 DQB9 DQB8 DQB7 VDDQ VSS DQB6 DQB5 DQB4 DQB3 VSS VDDQ DQB2 DQB1 VSS NC VDD ZZ DQA1 DQA2 VDDQ VSS DQA3 DQA4 DQA5 DQA6 VSS VDDQ DQA7 DQA8 DQA9 Rev: 2.05 6/2000 LBO A5 A4 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com A3 A2 A1 A0 NC NC V SS VDD NC NC A10 A11 A12 A13 A14 A15 A16 4/31 © 1999, Giga Semiconductor, Inc. . GS84018/32/36T/B-180/166/150/100 TQFP Pin Description Pin Location 37, 36 35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 47, 48, 49, 50 80 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 51, 80, 1, 30 51, 80, 1, 30 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 51, 52, 53, 56, 57 75, 78, 79 1, 2, 3, 6, 7 25, 28, 29, 30 87 93, 94 95, 96 95, 96 89 88 98, 92 97 86 83 84, 85 64 14 31 15, 41, 65, 91 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 16, 38, 39, 42, 43, 66 Symbol A0, A1 A2-16 A17 DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 DQA9, DQB9, DQC9, DQD9 NC DQA1-DQA9 DQB1-DQB9 NC BW BA, BB BC, BD NC CK GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC Type I I I I/O Description Address field LSB’s and Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input and Output pins. (x32, x36 Version) I/O Data Input and Output pins. (x36 Version) No Connect (x32 Version) I/O Data Input and Output pins. (x18 Version) I I I I I I I I I I I I I I I I - No Connect (x18 Version) Byte Write. Writes all enabled bytes. Active Low. Byte Write Enable for DQA, DQB Data I/O’s. Active Low. Byte Write Enable for DQC, DQD Data I/O’s. Active Low. (x32, x36 Version) No Connect (x18 Version) Clock Input Signal. Active High. Global Write Enable. Writes all bytes. Active Low. Chip Enable. Active Low. Chip Enable. Active High. Output Enable. Active Low. Burst address counter advance enable. Active Low. Address Strobe (Processor, Cache Controller). Active Low. Sleep Mode control. Active High. Flow Through or Pipeline mode. Active Low. Linear Burst Order mode. Active Low. Core power supply. I/O and Core Ground. Output driver power supply. No Connect. Rev: 2.05 6/2000 5/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 GS84018 Pad Out 119 Bump BGA - Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ 2 A6 E2 A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQB9 A2 A10 NC 3 A7 A4 A3 VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A11 NC 4 ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD NC NC 5 A8 A15 A14 VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A12 NC 6 A9 E3 A16 DQA9 NC DQA7 NC DQA5 VDD NC DQA3 NC DQA2 NC A13 A17 NC 7 VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ NC DQA1 NC ZZ VDDQ Rev: 2.05 6/2000 6/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 GS84032 Pad Out 119 Bump BGA - Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQ 2 A6 E2 A5 NC DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD78 DQD8 NC A2 NC NC 3 A7 A4 A3 VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A10 NC 4 ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD A11 NC 5 A8 A15 A14 VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A12 NC 6 A9 E3 A16 NC DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 NC A13 NC NC 7 VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 NC ZZ VDDQ Rev: 2.05 6/2000 7/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 GS84036Pad Out 119 Bump BGA - Top View 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQ 2 A6 E2 A5 DQC9 DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD78 DQD8 DQD9 A2 NC NC 3 A7 A4 A3 VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A10 NC 4 ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD A11 NC 5 A8 A15 A14 VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A12 NC 6 A9 E3 A16 DQB9 DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 DQA9 A13 NC NC 7 VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 NC ZZ VDDQ Rev: 2.05 6/2000 8/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 BGA Pin Description Pin Location N4, P4 A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, R2, R6, T3, T5 T4 T2, T6 T2, T6 K7, K6, L7, L6, M6, N7, N6, P7 H7, H6, G7, G6, F6, E7, E6, D7 H1, H2, G1, G2, F2, E1, E2, D1 K1, K2, L1, L2, M2, N1, N2, P1 P6, D6, D2, P2 P6, D6, D2, P2 L5, G5, G3, L3 P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 L5, G3 B1, C1, R1, T1, U2, J3, U3, D4, L4, U4, J5, U5, U6, B7, C7, R7 P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, B1, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3, T4 K4 M4 H4 E4, B6 B2 F4 G4 A4, B4 T7 R5 R3 J2, C4, J4, R4, J6 D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 Symbol A0, A1 An An NC An DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 DQA9, DQB9, DQC9, DQD9 NC BA, BB, BC, BD DQA1-DQA9 DQB1-DQB9 BA, BB NC NC CK BW GW E1, E3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ Type I I Description Address field LSB’s and Address Counter Preset Inputs. Address Inputs Address Input (x32/36 Versions) I I/O No Connect (x32/36 Versions) Address Input (x18 Version) Data Input and Output pins. (x32/36 Versions) I/O I I/O I I I I I I I I I I I I I I I Data Input and Output pins. (x36 Version) No Connect (x32 Version) Byte Write Enable for DQA, DQB, DQC, DQD I/O’s. Active Low. ( x36 Version) Data Input and Output pins. (x18 Version) Byte Write Enable for DQA, DQB I/O’s. Active Low. ( x18 Version) No Connect No Connect (x18 Version) Clock Input Signal. Active High. Byte Write. Writes all enabled bytes. Active Low. Global Write Enable. Writes all bytes. Active Low. Chip Enable. Active Low. Chip Enable. Active High. Output Enable. Active Low. Burst address counter advance enable. Active Low. Address Strobe (Processor, Cache Controller). Active Low. Sleep Mode control. Active High. Flow Through or Pipeline mode. Active Low. Linear Burst Order mode. Active Low. Core power supply. I/O and Core Ground. Output driver power supply. Rev: 2.05 6/2000 9/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 GS84018/32/36 Block Diagram Register A0-An D Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1 LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q Register E1 E3 E2 D Q Register D Q FT G Power Down Control ZZ 1 DQx0-DQx9 Note: Only x36 version shown for simplicity. Rev: 2.05 6/2000 10/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name State LBO FT ZZ L H or NC L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There are pull up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10 1st address 2nd address 3rd address 4th address Interleaved Burst Sequence A[1:0] 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. Byte Write Truth Table Function Read Read Write byte A Write byte B Write byte C Write byte D Write all bytes Write all bytes GW H H H H H H H L BW H L L L L L L X BA X H L H H H L X BB X H H L H H L X BC X H H H L H L X BD X H H H H L L X Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Note: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 2.05 6/2000 11/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst State Address Used Diagram Key5 None None None External External External Next Next Next Next Current Current Current Current X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X H E2 X F F T T T X X X X X X X X ADSP X L H L H H H X H X H X H X ADSC L X L X L L H H H H H H H H ADV X X X X X X L L L L H H H H W3 X X X X F T F F T T F F T T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D D Note: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 2.05 6/2000 12/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 2.05 6/2000 13/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 2.05 6/2000 14/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value -0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDDQ+0.5 (≤ 4.6 V max.) -0.5 to VDD+0.5 (≤ 4.6 V max.) +/- 20 +/- 20 1.5 -55 to 125 -55 to 125 Unit V V V V V mA mA W oC oC Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Symbol VDD VDDQ VIH VIL TA Min. 3.135 2.375 1.7 -0.3 0 Typ. 3.3 2.5 ----25 Max. 3.6 VDD VDD+0.3 0.8 70 Unit V V V V °C Notes 1 2 2 3 TA °C 3 Ambient Temperature (Industrial Range Versions) -40 25 85 Note: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V ≤ VDDQ ≤ 2.375V (i.e. 2.5V I/O) and 3.6V ≤ VDDQ ≤ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2V > Vi < VDD+2V with a pulse width not to exceed 20% tKC. Rev: 2.05 6/2000 15/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Undershoot Measurement and Timing VIH VDD+-2.0V VSS 50% VSS-2.0V 20% tKC VIL 50% VDD Overshoot Measurement and Timing 20% tKC Capacitance (TA=25oC, f=1MHZ, VDD=3.3V) Parameter Control Input Capacitance Input Capacitance Output Capacitance Note: This parameter is sample tested. Symbol CI CIN COUT Test conditions VDD=3.3V VIN=0V VOUT=0V Typ. 3 4 6 Max. 4 5 7 Unit pF pF pF Package Thermal Characteristics Rating Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Layer Board single four Symbol RΘJA RΘJA TQFP Max 40 24 BGA Max 38 21 Unit °C/W °C/W Notes 1,2,4 1,2,4 RΘJC 9 5 Junction to Case (TOP) °C/W 3,4 Notes: Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87. 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1. 4. For x18 configuration, consult factory. Rev: 2.05 6/2000 16/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions 2.3V 0.2V 1V/ns 1.25V 1.25V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ. 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VT=1.25V * Distributed Test Jig Capacitance Output Load 2 2.5V 30pF* DQ 5pF* 225Ω 225Ω DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IINZZ IINM IOL VOH VOH VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = - 4mA, VDDQ=2.375V IOH = - 4mA, VDDQ=3.135V IOL = 4mA Min -1uA -1uA -1uA -300uA -1uA -1uA 1.7V 2.4V Max 1uA 1uA 300uA 1uA 1uA 1uA 0.4V Rev: 2.05 6/2000 17/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Operating Currents -180 Parameter Test Conditions Operating Current Standby Current Deselect Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open -166 0 to 70°C -40 to 85°C -150 0 to 70°C -40 to 85°C -100 0 to 70°C -40 to 85°C Symbol IDD Pipeline 0 to 70°C -40 to 85°C 330mA 340mA 310mA 320mA 275mA 285mA 190mA 200mA IDD 190mA 200mA 190mA 200mA 190mA 200mA 140mA 150mA Flow-Thru ISB Pipeline ISB Flow-Thru IDD Pipeline IDD Flow-Thru 30mA 30mA 40mA 40mA 30mA 30mA 40mA 40mA 30mA 30mA 40mA 40mA 30mA 30mA 80mA 65mA 40mA 40mA 90mA 75mA ZZ ≥ VDD - 0.2V Device Deselected; All other inputs ≥ VIH or ≤ VIL 120mA 130mA 110mA 120mA 105mA 115mA 80mA 90mA 80mA 90mA 80mA 90mA Rev: 2.05 6/2000 18/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 AC Electrical Characteristics Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time FlowThru Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ 1 -180 Min 5.5 --1.5 1.5 10.0 --3.0 3.0 1.3 1.5 1.5 --0 --1.5 0.5 5 1 20 Max --3.2 ------8.0 --------3.2 3.2 --3.2 ----------- -166 Min 6.0 --1.5 1.5 10.0 --3.0 3.0 1.3 1.5 1.5 --0 --1.5 0.5 5 1 20 Max --3.5 ------8.5 --------3.5 3.5 --3.5 ----------- -150 Min 6.7 --1.5 1.5 10.0 --3.0 3.0 1.5 1.7 1.5 --0 --1.5 0.5 5 1 20 Max --3.8 ------10.0 --------3.8 3.8 --3.8 ----------10 --- -100 Min Max --4.5 ------12.0 --------5 5 --5 ----------- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5 1.5 15.0 --3.0 3.0 2 2.2 1.5 --0 --2.0 0.5 5 1 20 tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 2.05 6/2000 19/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Write Cycle Timing Single Write Burst Write Write Deselected CK tS tH tKH tKL tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH ADV must be inactive for ADSP Write WR2 WR3 A0-An GW WR1 tS tH tS tH BW tS tH BA - BD tS tH WR1 WR1 WR2 WR3 WR3 E1 masks ADSP E1 tS tH Deselected with E2 E2 tS tH E2 and E3 only sampled with ADSP or ADSC E3 G tS tH Write specified byte for 2a and all bytes for 2b, 2c& 2d D2a D2b D2c D2d D3a DQA - DQD Hi-Z D1a Rev: 2.05 6/2000 20/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Flow Through Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0-An GW RD1 tS RD2 RD3 tH tS tH BW BA - BD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE tOHZ G tOLZ tKQX Q1a tLZ tKQ tHZ Q2a Q2b Q2c Q2d Q3a tKQX DQA-DQD Hi-Z Rev: 2.05 6/2000 21/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Flow Through Read-Write Cycle Timing Single Read Single Write Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC ADV tS tH tS tH A0-An GW RD1 WR1 RD2 tS tH tS tH BW tS tH BA - BD WR1 tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 tOHZ E3 tOE G tKQ tS Q1a tH Q2a Q2b Q2c Q2d Q2a DQA - DQD Hi-Z D1a Burst wrap around to its initial state Rev: 2.05 6/2000 22/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Pipelined SCD Read Cycle Timing Single Read Burst Read tKH tKL tKC tS tH ADSC initiated read ADSP is blocked by E1 inactive CK tS tH ADSP ADSC tS tH Suspend Burst ADV tS tH A0-A17 GW RD1 tS RD2 RD3 tH tS tH BW BWA - BWD tS tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP or ADSC Deselected with E2 E2 tS tH E3 tOE G DQA - DQD Hi-Z tOLZ Q1a tLZ tOHZ tKQX Q2a Q2b Q2c Q2d tKQX Q3a tHZ tKQ Rev: 2.05 6/2000 23/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Pipelined SCD Read - Write Cycle Timing Single Read tKL Single Write Burst Read CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0-An GW RD1 WR1 RD2 tS tH tS tH BW tS tH BWA - BWD tS tH WR1 E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH Deselected with E3 E3 tOE tOHZ G tKQ tS tH Q1a D1a Q2a Q2b Q2c Q2d DQA - DQD Hi-Z Rev: 2.05 6/2000 24/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Sleep Mode Timing Diagram CK tS tH tKC tKH tKL ADSP ADSC tZZS ~ ~~~~ ~ ~~~~ ~ tZZH tZZR ZZ Snooze Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 2.05 6/2000 25/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 GS 84018/32/36 Output Driver Characteristics 60 Pull Down Drivers 40 20 VDDQ I Out 0 I Out (mA) VOut VSS -20 -40 Pull Up Drivers -60 -80 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD LD 3.3V PD LD 3.1V PD LD 3.1V PU LD 3.3V PU LD 3.6V PU LD Rev: 2.05 6/2000 26/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 TQFP Package Drawing Symbol A1 A2 b c D D1 E E1 e L L1 Y θ Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 0.45 Nom. 0.10 1.40 0.30 22.0 20.0 16.0 14.0 0.65 0.60 1.00 Max 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 L L1 θ c P in 1 D D1 e b 0.75 0.10 0° 7° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion A1 Y A2 E1 E Rev: 2.05 6/2000 27/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Package Dimensions - 119 Pin BGA Pin 1 Corner A 7654321 G P B S D A B C D E F G H J K L M N P R T U N Top View R Bottom View Package Dimensions - 119 Pin BGA T Symbol A B C D E F G K N P R S T Unit: mm Description Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Cut-out Package Width Foot Length Width of package between balls Length of package between balls Variance of Ball Height Min. Nom. Max 13.8 21.8 0.60 0.50 0.75 0.60 1.46 1.27 0.80 0.90 12.00 19.50 7.62 20.32 0.15 1.00 14.0 22.0 14.2 22.2 2.40 0.90 0.70 1.70 F Side View Rev: 2.05 6/2000 C E K 28/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMS Org 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 Part Number1 GS84018T-180 GS84018T-166 GS84018T-150 GS84018T-100 GS84032T-180 GS84032T-166 GS84032T-150 GS84032T-100 GS84036T-180 GS84036T-166 GS84036T-150 GS84036T-100 GS84018T-180I GS84018T-166I GS84018T-150I GS84018T-100I GS84032T-180I GS84032T-166I GS84032T-150I GS84032T-100I GS84036T-180I GS84036T-166I GS84036T-150I GS84036T-100I GS84018B-180 GS84018B-166 GS84018B-150 GS84018B-100 GS84032B-180 Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP BGA BGA BGA BGA BGA Speed2 (Mhz/ TA3 ns) 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 C C C C C C C C C C C C I I I I I I I I I I I I C C C C C Status Not Available Not Available Not Available Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T. 2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline / Flow through mode selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings. Rev: 2.05 6/2000 29/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Org 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 Part Number1 GS84032B-166 GS84032B-150 GS84032B-100 GS84036B-180 GS84036B-166 GS84036B-150 GS84036B-100 GS84018B-180I GS84018B-166I GS84018B-150I GS84018B-100I GS84032B-180I GS84032B-166I GS84032B-150I GS84032B-100I GS84036B-180I GS84036B-166I GS84036B-150I GS84036B-100I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA Speed2 (Mhz/ TA3 ns) 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 C C C C C C C I I I I I I I I I I I I Status Not Available Not Available Not Available Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS84032T-7.5T. 2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline / Flow through mode selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings. Rev: 2.05 6/2000 30/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com GS84018/32/36T/B-180/166/150/100 Revision History Rev. Code: Old; New GS84018/32/36 Rev 1.02c 5/1999; GS84018/32/36 2.00 8/1999D Types of Changes Format or Content Format/Typos Content Page /Revisions;Reason • Document/Continued changing to new format. • Added Fine Pitch BGA Package. • • Took “E” out of 840HE...in Core and Interface Voltages. • Pin outs/New small caps format. • Timing Diagrams/New format. • Block Diagrams/New small caps format. • Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3. • Pin Description/Rearranged Address Inputs to match order on TQFP Pinout. • TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1. Format/Typos GS84018/32/362.00 8/ 1999;GS84018/32/362.01 9/1999E Content • GS84018/32/362.01 9/ 1999E;GS84018/32/362.02 GS84018/32/362.0210-11/ 1999;GS84018/32/362.032/2000G GS84018/32/362.032/2000G; GS84018_r2_04 84018_r2_04; 84018_r2_05 • Took out Fine Pitch BGA Package. Package change in progress. Format Content Content • New GSI Logo • Took “Pin” out of heading for consistency. • Updated ADSC in timing diagrams on pages 22 and 24 • Pin description table updated • Updated BGA pin description table to meet JEDEC standard Rev: 2.05 6/2000 31/31 © 1999, Giga Semiconductor, Inc. . Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com