GS840FH32AT-8

GS840FH18/32/36AT-8/8.5/10/12 TQFP Commercial Temp Industrial Temp Features • Flow Through mode operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock Control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP • Pb-Free 100-lead TQFP package available 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs 8 ns–12 ns 3.3 V VDD 3.3 V and 2.5 V I/O counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Designing For Compatibility The JEDEC standard for Burst RAMs calls for a FT mode pin option (Pin 14 on TQFP). Board sites for flow through Burst RAMs should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI’s pipeline/flow through-configurable Burst RAMs or any vendor’s flow through or configurable Burst SRAM. Bumps designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, (e.g., GS840FH18/32/36A), to achieve flow through functionality. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS840FH18/32/36A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit. Functional Description Applications The GS840FH18/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS840FH18/32/36A is available in a JEDEC-standard 100-lead TQFP package. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address Parameter Synopsis -8 -8.5 -10 -12 Flow tKQ 8 ns 8.5 ns 10 ns 12 ns Through tCycle 9 ns 10 ns 12 ns 15 ns 2-1-1-1 IDD 210 mA 190 mA 165 mA 135 mA Rev: 1.07 10/2004 1/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 GS840FH18 100-Pin TQFP Pinout VDDQ VSS NC NC DQ B DQB VSS VDDQ DQ B DQB NC VDD NC VSS DQ B DQB VDDQ VSS DQ B DQB DQPB NC VSS VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Rev: 1.07 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 2/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 GS84FH32 100-Pin TQFP Pinout NC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC NC VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC Rev: 1.07 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 3/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 GS840FH36 100-Pin TQFP Pinout DQPC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC NC VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA Rev: 1.07 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 4/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 TQFP Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD BW BA , BB BC , BD CK GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ LBO VDD VSS VDDQ NC Type I I I/O I I I I I I I I I I I I I I I — Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect Rev: 1.07 10/2004 5/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 GS840FH18/32/36A Block Diagram Register A0–An D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E3 E2 Register D Q Register D Q 0 G Power Down Control ZZ 1 DQx0–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.07 10/2004 6/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Mode Pin Functions Mode Name Burst Order Control Power Down Control Pin Name LBO ZZ State L H or NC L or NC H Function Linear Burst Interleaved Burst Active Standby, IDD = ISB Note: There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 00 01 10 01 10 11 10 11 00 11 00 01 1st address 2nd address 3rd address A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 01 00 11 10 11 00 11 10 01 4th address 11 00 01 10 Note: The burst counter wraps to initial state on the 5th clock. 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Byte Write Truth Table Function Read Read Write byte A Write byte B Write byte C Write byte D Write all bytes GW H H H H H H H BW H L L L L L L BA X H L H H H L BB X H H L H H L BC X H H H L H L BD X H H H H L L Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.07 10/2004 7/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X E2 X F F T T T X X X X X X X ADSP ADSC X L H L H H H X H X H X H L X L X L L H H H H H H H ADV X X X X X X L L L L H H H W3 X X X X F T F F T T F F T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.07 10/2004 8/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.07 10/2004 9/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.07 10/2004 10/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to VDD –0.5 to 6 –0.5 to VDDQ+0.5 (≤ 4.6 V max.) –0.5 to VDD+0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V V mA mA W oC o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Parameter Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Symbol VDD VDDQ VIH VIL TA Min. 3.135 2.375 1.7 –0.3 0 Typ. 3.3 2.5 — — 25 Max. 3.6 VDD VDD+0.3 0.8 70 Unit V V V V °C Notes 1 2 2 3 TA –40 25 85 °C 3 Ambient Temperature (Industrial Range Versions) Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V ≤ VDDQ ≤ 2.375 V (i.e., 2.5 V I/O) and 3.6 V ≤ VDDQ ≤ 3.135 V (i.e., 3.3 V I/O) and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC. Rev: 1.07 10/2004 11/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Undershoot Measurement and Timing VIH VDD +– 2.0 V VSS 50% VSS – 2.0 V 20% tKC VIL 50% VDD Overshoot Measurement and Timing 20% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 3.3 V) Parameter Control Input Capacitance Input Capacitance Output Capacitance Note: This parameter is sample tested. Symbol CI CIN COUT Test conditions VDD = 3.3 V VIN = 0 V VOUT = 0 V Typ. 3 4 6 Max. 4 5 7 Unit pF pF pF Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87. 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1. Rev: 1.07 10/2004 12/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions 2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Output load Fig. 1& 2 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ, and tOHZ. 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VT = 1.25 V * Distributed Test Jig Capacitance Output Load 2 2.5 V 30pF* DQ 5pF* 225Ω 225Ω DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IINZZ IINM IOL VOH VOH VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –mA, VDDQ = 2.375 V IOH = –mA, VDDQ = 3.135 V IOL = mA Min –1 uA –1 uA –1 uA –300 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 300 uA 1 uA 1 uA 1 uA — — 0.4 V Rev: 1.07 10/2004 13/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Operating Currents -8 Parameter Test Conditions All other inputs ≥VIH or ≤ VIL Output open ZZ ≥ VDD – 0.2 V Device Deselected; All other inputs ≥ VIH or ≤ VIL Symbol 0 to 70°C 210 -8.5 -40 to 85°C 220 -10 0 to 70°C 165 -12 -40 to 85°C 175 0 to 70°C 190 -40 to 85°C 200 0 to 70°C 135 -40 to 85°C 145 Unit Operating Current Standby Current Deselect Current IDD Flow Through ISB Flow Through IDD Flow Through mA mA mA 20 30 20 30 20 30 20 30 40 50 40 50 35 45 35 45 AC Electrical Characteristics Parameter Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ 1 -8 Min 9.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 Max — 8.0 — — — — 3.2 3.2 — 3.2 — — — — — Min 10.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 -8.5 Max — 8.5 — — — — 3.5 3.5 — 3.5 — — — — — Min 10.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 -10 Max — 10 — — — — 3.8 3.8 — 3.8 — — — — — Min 15.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 -12 Max — 12 — — — — 5 5 — 5 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.07 10/2004 14/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Flow Through Mode Timing Begin Read A Cont tKL tKH Cont tKC Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect CK ADSP tS tH ADSC tS tH ADV tS tH A0–An A B C Fixed High tS tH ADSC initiated read tS tH GW tS tH BW tS tH Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tH tS tOE DQa–DQd Q(A) Deselected with E1 E2 and E3 only sampled with ADSC tOHZ D(B) tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) tHZ tKQX Rev: 1.07 10/2004 15/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Sleep Mode Timing Diagram tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL Rev: 1.07 10/2004 16/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 GS840FH18/32/36A Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VDDQ I Out I Out (mA) 0.0 VOut VSS -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD HD 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 3.6V PU HD Rev: 1.07 10/2004 17/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 TQFP Package Drawing (Package T) L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c Pin 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — L1 0.10 1.40 0.30 — 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 e b D D1 0.45 — 0.75 — A1 Y 0.10 0° — A2 E1 E 7° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.07 10/2004 18/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Ordering Information for GSI Synchronous Burst RAMS Speed2 (MHz/ns) 8 8.5 10 12 8 8.5 10 12 8 8.5 10 12 8 8.5 10 12 8 8.5 10 12 8 8.5 10 12 8 8.5 10 12 8 Org 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 Part Number1 GS840FH18AT-8 GS840FH18AT-8.5 GS840FH18AT-10 GS840FH18AT-12 GS840FH32AT-8 GS840FH32AT-8.5 GS840FH32AT-10 GS840FH32AT-12 GS840FH36AT-8 GS840FH36AT-8.5 GS840FH36AT-10 GS840FH36AT-12 GS840FH18AT-8I GS840FH18AT-8.5I GS840FH18AT-10I GS840FH18AT-12I GS840FH32AT-8I GS840FH32AT-8.5I GS840FH32AT-10I GS840FH32AT-12I GS840FH36AT-8I GS840FH36AT-8.5I GS840FH36AT-10I GS840FH36AT-12I GS840FH18AGT-8 GS840FH18AGT-8.5 GS840FH18AGT-10 GS840FH18AGT-12 GS840FH32AGT-8 Type Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP TA 3 Status C C C C C C C C C C C C I I I I I I I I I I I I C C C C C 128K x 32 GS840FH32AGT-8.5 Flow Through Pb-free TQFP 8.5 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 10/2004 19/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 Org 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 Part Number1 GS840FH32AGT-10 GS840FH32AGT-12 GS840FH36AGT-8 GS840FH36AGT-8.5 GS840FH36AGT-10 GS840FH36AGT-12 GS840FH18AGT-8I GS840FH18AGT-8.5I GS840FH18AGT-10I GS840FH18AGT-12I GS840FH32AGT-8I GS840FH32AGT-8.5I GS840FH32AGT-10I GS840FH32AGT-12I GS840FH36AGT-8I GS840FH36AGT-8.5I GS840FH36AGT-10I Type Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Flow Through Package Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Speed2 (MHz/ns) 10 12 8 8.5 10 12 8 8.5 10 12 8 8.5 10 12 8 8.5 10 TA 3 Status C C C C C C I I I I I I I I I I I 128K x 36 GS840FH36AGT-12I Flow Through Pb-free TQFP 12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840FH32AT-7.5T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.07 10/2004 20/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840FH18/32/36AT-8/8.5/10/12 4Mb Burst Datasheet Revision History Rev. Code: Old; New 840FH18A_r1_02 Types of Changes Page /Revisions;Reason Format or Content Content • Updated pin description table • Updated table on page 1 • Updated Operating Currents table on page 14 • Updated AC Electrical Characteristics table on page 14 • Updated Ordering Information table on page 21 • Updated entire document to comply with Technical Publications standards • Reduced IDD by 20 mA in table on page 1 and Operating Currents table • Removed 7.5 ns references from entire datasheet • Updated format • Matched current numbers to NBT parts • Removed Preliminary banner • Added Pb-free information to TQFP 840FH18A_r1_02; 840FH18A_r1_03 Content/Format 840FH18A_r1_03; 840FH18A_r1_04 840FH18A_r1_04; 840FH18A_r1_05 840FH18A_r1_05; 840FH18A_r1_06 840FH18A_r1_06; 840FH18A_r1_07 Content Content Content Content Rev: 1.07 10/2004 21/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.