GS840H36AGT-180I

GS840H18/32/36AT/B-180/166/150/100 TQFP, BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC standard 100-lead TQFP or 119-Bump BGA package • Pb-Free 100-lead TQFP package available 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs 180 MHz–100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS840H18/32/36A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS840H18/32/36A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Functional Description Applications The GS840H18/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS840H18/32/36A is available in a JEDEC standard 100-lead TQFP or 119-Bump BGA package. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 tCycle tKQ IDD tKQ tCycle IDD –180 5.5 ns 3.0 ns 335 mA 8 ns 9 ns 210 mA –166 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA –150 6.6 ns 3.8 ns 280 mA 10 ns 12 ns 165 mA –100 10 ns 4.5 ns 190 mA 12 ns 15 ns 135 mA Rev: 1.11 10/2004 1/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H18A 100-Pin TQFP Pinout (Package T) VDDQ VSS NC NC DQ B DQB VSS VDDQ DQ B DQB FT VDD NC VSS DQ B DQB VDDQ VSS DQ B DQB DQPB NC VSS VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Rev: 1.11 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 2/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H32A 100-Pin TQFP Pinout (Package T) NC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC FT VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC Rev: 1.11 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 3/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H36A 100-Pin TQFP Pinout (Package T) DQPC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC FT VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA Rev: 1.11 10/2004 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 4/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 TQFP Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD BW BA, BB BC , BD CK GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC Type I I I/O I I I I I I I I I I I I I I I I - Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pins Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/’s; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect Rev: 1.11 10/2004 5/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H18A Pad Out—119-Bump BGA—Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A E2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A NC 3 A A A VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A NC 4 ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD NC NC 5 A A A VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A NC 6 A E3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Rev: 1.11 10/2004 6/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H32A Pad Out—119-Bump BGA—Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A E2 A NC DQC DQC DQC DQC VDD DQD DQD DQD DQD NC A NC NC 3 A A A VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A NC 4 ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD A NC 5 A A A VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A NC 6 A E3 A NC DQB DQB DQB DQB VDD DQA DQA DQA DQA NC A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ Rev: 1.11 10/2004 7/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H36A Pad Out—119-Bump BGA—Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC2 DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A E2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC NC 3 A A A VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A NC 4 ADSP ADSC VDD NC E1 G ADV GW VDD CK NC BW A1 A0 VDD A NC 5 A A A VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A NC 6 A E3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB2 DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ Rev: 1.11 10/2004 8/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 BGA Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD BA, BB, BC, BD CK BW GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ NC Type I I I/O I I I I I I I I I I I I I I I - Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/O’s; active low Clock Input Signal; active high Byte Write—Writes all enabled bytes; active low Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect Rev: 1.11 10/2004 9/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H18/32/36A Block Diagram Register A0–An D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E3 E2 Register D Q Register D FT G Power Down Control Q ZZ 1 DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.11 10/2004 10/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Pin Name LBO FT ZZ State L H or NC L H or NC L or NC H Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Note: There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 00 01 10 01 10 11 10 11 00 11 00 01 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 00 01 10 01 00 11 10 11 00 11 10 01 4th address 11 00 01 10 Note: The burst counter wraps to initial state on the 5th clock. 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.11 10/2004 11/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Byte Write Truth Table Function Read Read Write byte A Write byte B Write byte C Write byte D Write all bytes GW H H H H H H H BW H L L L L L L BA X H L H H H L BB X H H L H H L BC X H H H L H L BD X H H H H L L Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.11 10/2004 12/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X E2 X F F T T T X X X X X X X ADSP ADSC X L H L H H H X H X H X H L X L X L L H H H H H H H ADV X X X X X X L L L L H H H W3 X X X X F T F F T T F F T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.11 10/2004 13/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.11 10/2004 14/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.11 10/2004 15/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V mA mA W o o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 VDDQ3 VDDQ2 Min. 3.0 2.3 3.0 2.3 Typ. 3.3 2.5 3.3 2.5 Max. 3.6 2.7 3.6 2.7 Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.11 10/2004 16/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 2.0 –0.3 2.0 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 0.6*VDD –0.3 0.6*VDD –0.3 Typ. — — — — Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.11 10/2004 17/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Undershoot Measurement and Timing VIH VDD + 2.0 V VSS 50% VSS – 2.0 V 50% tKC VIL 50% VDD Overshoot Measurement and Timing 50% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* Rev: 1.11 10/2004 18/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT, SCD, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA –1 uA –1 uA –100 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V Operating Currents -180 Parameter Test Conditions Symbol IDD Pipeline IDD Flow Through ISB Pipeline ISB Flow Through IDD Pipeline IDD Flow Through 0 to 70°C 335 210 20 20 55 40 -166 –40 to 85°C 345 220 30 30 65 50 -150 –40 to 85°C 320 200 30 30 60 50 -100 –40 to 85°C 290 175 30 30 60 45 0 to 70°C 310 190 20 20 50 40 0 to 70°C 280 165 20 20 50 35 0 to 70°C 190 135 20 20 40 35 –40 to 85°C 200 145 30 30 50 45 Unit Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open ZZ ≥ VDD – 0.2 V mA mA mA mA mA mA Standby Current Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Rev: 1.11 10/2004 19/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 AC Electrical Characteristics Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ 1 -180 Min 5.5 — 1.5 1.5 9.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 Max — 3.0 — — — 8.0 — — — — 3.2 3.2 — 3.2 — — — — — Min 6.0 — 1.5 1.5 10.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 -166 Max — 3.5 — — — 8.5 — — — — 3.5 3.5 — 3.5 — — — — — Min 6.7 — 1.5 1.5 12.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 20 -150 Max — 3.8 — — — 10.0 — — — — 3.8 3.8 — 3.8 — — — — — Min 10 — 1.5 1.5 15.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 2.0 0.5 5 1 20 -100 Max — 4.5 — — — 12.0 — — — — 5 5 — 5 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ tS tH tZZS2 tZZH2 tZZR 1 tOHZ1 Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.11 10/2004 20/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Pipeline Mode Timing Begin Read A Cont Cont Deselect Write B Single Write tKL tKH tKC Read C Read C+1 Read C+2 Read C+3 Cont Burst Read Deselect Single Read CK ADSP tS tH ADSC tS ADV tS tH A0–An A B C ADSC initiated read tH tS GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa–DQd tOHZ Q(A) D(B) E2 and E3 only sampled with ADSP and ADSC E1 masks ADSP Deselected with E1 tH tKQ tH tLZ Q(C) Q(C+1) Q(C+2) tKQX tHZ Q(C+3) Rev: 1.11 10/2004 21/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Flow Through Mode Timing Begin Read A Cont tKL tKH Cont tKC Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect CK ADSP tS tH ADSC tS tH ADV tS tH A0–An A B C Fixed High tS tH ADSC initiated read tS tH GW tS tH BW tS tH Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tH tS tOE DQa–DQd Q(A) Deselected with E1 E2 and E3 only sampled with ADSC tOHZ D(B) tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) tHZ tKQX Rev: 1.11 10/2004 22/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Sleep Mode Timing Diagram tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.11 10/2004 23/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 GS840H18/32/36A Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VDDQ I Out I Out (mA) 0.0 VOut VSS -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD HD 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 3.6V PU HD Rev: 1.11 10/2004 24/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 TQFP Package Drawing (Package T) L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c Pin 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — L1 0.10 1.40 0.30 — 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 e b D D1 0.45 — 0.75 — A1 Y 0.10 0° — A2 E1 E 7° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.11 10/2004 25/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Package Dimensions—119-Bump FPBGA (Package B, Variation 1) Pin #1 Corner BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) 1 2 3 45 6 7 A B C D E F G H J K L M N P R T U Ø1.00(3x) REF 7 6 5 43 2 1 A B C D E F G H J K L M N P R T U 22±0.20 19.50 0.70 REF 12.00 B 1.27 7.62 A 0.20(4x) 14±0.20 0.90±0.10 0.15 C 0.56±0.05 Rev: 1.11 10/2004 0.50~0.70 2.06.±0.13 C SEATING PLANE 0.15 C 26/30 20.32 1.27 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs Org 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 Part Number1 GS840H18AT-180 GS840H18AT-166 GS840H18AT-150 GS840H18AT-100 GS840H32AT-180 GS840H32AT-166 GS840H32AT-150 GS840H32AT-100 GS840H36AT-180 GS840H36AT-166 GS840H36AT-150 GS840H36AT-100 GS840H18AT-180I GS840H18AT-166I GS840H18AT-150I GS840H18AT-100I GS840H32AT-180I GS840H32AT-166I GS840H32AT-150I GS840H32AT-100I GS840H36AT-180I GS840H36AT-166I GS840H36AT-150I GS840H36AT-100I GS840H18AGT-180 GS840H18AGT-166 GS840H18AGT-150 GS840H18AGT-100 GS840H32AGT-180 Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Speed2 T 3 (MHz/ns) A 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 C C C C C C C C C C C C I I C C I I C C I I C C C C C C C Status 128K x 32 GS840H32AGT-166 Pipeline/Flow Through Pb-free TQFP 166/8.5 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 10/2004 27/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs (Continued) Org 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 128K x 36 Part Number1 GS840H32AGT-150 GS840H32AGT-100 GS840H36AGT-180 GS840H36AGT-166 GS840H36AGT-150 GS840H36AGT-100 GS840H18AGT-180I GS840H18AGT-166I GS840H18AGT-150I GS840H18AGT-100I GS840H32AGT-180I GS840H32AGT-166I GS840H32AGT-150I GS840H32AGT-100I GS840H36AGT-180I GS840H36AGT-166I GS840H36AGT-150I GS840H36AGT-100I GS840H18AB-180 GS840H18AB-166 GS840H18AB-150 GS840H18AB-100 GS840H32AB-180 GS840H32AB-166 GS840H32AB-150 GS840H32AB-100 GS840H36AB-180 GS840H36AB-166 GS840H36AB-150 GS840H36AB-100 Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP Pb-free TQFP 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) Speed2 T 3 (MHz/ns) A 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 C C C C C C I I C C I I C C I I C C C C C C C C C C C C C C Status 256K x 18 GS840H18AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 10/2004 28/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs (Continued) Org 256K x 18 256K x 18 256K x 18 128K x 32 128K x 32 128K x 32 128K x 32 128K x 36 128K x 36 128K x 36 Part Number1 GS840H18AB-166I GS840H18AB-150I GS840H18AB-100I GS840H32AB-180I GS840H32AB-166I GS840H32AB-150I GS840H32AB-100I GS840H36AB-180I GS840H36AB-166I GS840H36AB-150I Type Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Pipeline/Flow Through Package 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) 119 BGA (var. 1) Speed2 T 3 (MHz/ns) A 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 I C C I I C C I I C Status 128K x 36 GS840H36AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 10/2004 29/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840H18/32/36AT/B-180/166/150/100 4Mb Burst Datasheet Revision History Rev. Code: Old; New GS84018/32/36 Rev 1.02c 5/ 1999; GS84018/32/36 8/1999D Types of Changes Page /Revisions;Reason Format or Content Format/Typos Content • Document/Continued changing to new format. • • Took “E” out of 840HE...in Core and Interface Voltages. • Pin outs/New small caps format. • Timing Diagrams/New format. • Block Diagrams/New small caps format. • Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3. • Pin Description/Rearranged Address Inputs to match order on TQFP Pinout. • TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1. • • New GSI Logo • Took “Pin” out of heading for consistency. • Corrected all part order numbers • Updated pin description table • Updated BGA pin description table to meet JEDEC standard • Updated table on page 1 • Updated Operating Currents table on page 18 • Updated AC Electrical Characteristics table on page 19 • Added 150 MHz and 100 MHz • Updated format to comply with Technical Publications standards • Reduced IDD by 20 mA in table on page 1 and Operating Currents table • Removed 200 MHz references from entire datasheet • Updated format • Matched current numbers to NBT parts • Removed Preliminary banner • Added Pb-free TQFP information • Added variation number to 119 BGA information Format/Typos GS84018/32/36 8/ 1999;GS84018/32/36 9/ 1999E Content GS84018/32/36 9/ 1999E;GS84018/32/36 GS84018/32/3610-11/ 1999;GS84018/32/362/ 2000G GS84018/32/362/2000G; 840H18A_r1_04 840H18A_r1_04; 840H18A_r1_05 840H18A_r1_05; 840H18A_r1_06 Format Content Content Content 840H18A_r1_06; 840H18A_r1_07 Content/Format 840H18A_r1_07; 840E18_r1_08 840H18A_r1_08; 840H18_r1_09 840H18A_r1_09; 840H18A_r1_10 840H18A_r1_10; 840H18A_r1_11 Content Content Content Content Rev: 1.11 10/2004 30/30 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.