GS842Z18AB-166I

GS842Z18/36AB-180/166/150/100 119-Bump BGA Commercial Temp Industrial Temp Features • 256K x 18 and 128K x 36 configurations • User configurable Pipeline and Flow Through mode • NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization • Fully pin compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • Pin-compatible with 2M, 8M, and 16M devices • 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleave Burst mode • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • Clock Control, registered address, data, and control • ZZ Pin for automatic power-down • JEDEC-standard 119-bump BGA package 4Mb Pipelined and Flow Through Synchronous NBT SRAMs 180 MHz–100 MHz 3.3 V VDD 2.5 V and 3.3 V VDDQ Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS842Z18/36AT may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS842Z18/36AT is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump BGA package. Functional Description The GS842Z18/36AB is a 4Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 tCycle tKQ IDD tKQ tCycle IDD –180 5.5 ns 3.2 ns 335 mA 8 ns 9.1 ns 210 mA –166 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA –150 6.6 ns 3.8 ns 280 mA 10 ns 12 ns 165 mA –100 10 ns 4.5 ns 190 mA 12 ns 15 ns 135 mA Rev: 1.03 11/2004 1/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 GS842Z18A Pad Out—119-Bump BGA—Top View (Packge B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A E2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A TDI 4 NC ADV VDD ZQ E1 G NC W VDD CK NC CKE A1 A0 VDD NC TCK 5 A A A VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A TDO 6 A E3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Rev: 1.03 11/2004 2/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 GS842Z36A Pad Out— 119-Bump BGA—Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A E2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC TMS 3 A A A VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A TDI 4 NC ADV VDD ZQ E1 G NC W VDD CK NC CKE A1 A0 VDD A TCK 5 A8 A A VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A TDO 6 A E3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ Rev: 1.03 11/2004 3/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 GS842Z18/36A Pin Description Symbol A0 , A1 An DQA DQB DQC DQD BA , BB , BC , BD CK CKE W E1 G ADV ZZ FT LBO ZQ NC TMS TDI TDO TCK VDD VSS VDDQ CK Type I I I/O I I I I I I I I I I I I — I I O I I I I I Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQA I/Os; active low ( x36 Version) Clock Input Signal; active high Clock Input Buffer Enable; active low Write Enable. Writes all enabled bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active high Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) No Connect Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply Clock Input Signal; active high Rev: 1.03 11/2004 4/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Functional Details Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipelined Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function Read Write Byte “a” Write Byte “b” Write Byte “c” Write Byte “d” Write all Bytes Write Abort/NOP W H L L L L L L BA X L H H H L H BB X H L H H L H BC X H H L H L H BD X H H H L L H Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins. Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 1.03 11/2004 5/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Synchronous Truth Table Operation Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ R B R B W B B D D D D D External Next External Next External Next Next None None None None None None Current L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X L-H L L L L L L L L L L L L X H L H L H L H H L L L L H X X H X H X L X X X X X L X X X X X X X L L H X X X H X X X L X L X L X X H X X L X X X H X H X H X X X X L H X X X L X L X L X X X H X L X X X L L H H X X X X X X X X X X L L L L L L L L L L L L H L DQ Q Q High-Z High-Z D D Notes 1,10 2 1,2,10 3 1,3,10 High-Z 1,2,3,10 High-Z High-Z High-Z High-Z High-Z High-Z 4 1 1 Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 1.03 11/2004 6/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Pipelined and Flow Through Read-Write Control State Diagram D B R Deselect W D D W R R New Read B New Write W B R W R W B Burst Read D Burst Write D B Key Input Command Code Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. ƒ Transition Current State (n) Next State (n+1) n n+1 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. n+2 n+3 Clock (CK) Command ƒ Current State ƒ Next State ƒ ƒ Current State and Next State Definition for Pipelined and Flow Through Read/Write Control State Diagram Rev: 1.03 11/2004 7/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Pipeline Mode Data I/O State Diagram Intermediate BW High Z (Data In) D R Intermediate W Intermediate Intermediate RB Data Out (Q Valid) D Intermediate W R High Z B D Intermediate Key Input Command Code Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. ƒ Transition Current State (n) Transition Next State (n+2) Intermediate State (N+1) 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. n n+1 n+2 n+3 Clock (CK) Command ƒ Current State ƒ Intermediate State ƒ Next State ƒ Current State and Next State Definition for Pipeline Mode Data I/O State Diagram Rev: 1.03 11/2004 8/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Flow Through Mode Data I/O State Diagram BW High Z (Data In) D R W RB Data Out (Q Valid) D W R High Z B D Key Input Command Code Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. ƒ Transition Current State (n) n Next State (n+1) n+1 n+2 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. n+3 Clock (CK) Command ƒ Current State ƒ Next State ƒ ƒ Current State and Next State Definition for: Pipelined and Flow Through Read Write Control State Diagram Rev: 1.03 11/2004 9/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, interleaved burst sequence is selected. See the tables below for details. FLXDrive™ The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control FLXDrive Output Impedance Control Pin Name LBO FT ZZ ZQ State L H L H or NC L or NC H L H or NC Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB High Drive (Low Impedance) Low Drive (High Impedance) Note: There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ and PE pins, so those this input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Rev: 1.03 11/2004 10/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 8 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull-down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep Mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC CK tZZR tZZS ZZ tZZH tKL Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Bump R5. Not all vendors offer this option, however, most mark Bump R5 as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Rev: 1.03 11/2004 11/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V mA mA W o o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 VDDQ3 VDDQ2 Min. 3.0 2.3 3.0 2.3 Typ. 3.3 2.5 3.3 2.5 Max. 3.6 2.7 3.6 2.7 Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03 11/2004 12/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 2.0 –0.3 2.0 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 0.6*VDD –0.3 0.6*VDD –0.3 Typ. — — — — Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03 11/2004 13/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Undershoot Measurement and Timing VIH VDD + 2.0 V VSS 50% VSS – 2.0 V 50% tKC VIL 50% VDD Overshoot Measurement and Timing 50% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* Rev: 1.03 11/2004 14/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA –1 uA –1 uA –100 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V Rev: 1.03 11/2004 15/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Operating Currents –40 to 85°C 345 220 30 30 65 50 0 to 70°C 310 190 20 20 50 40 –40 to 85°C 320 200 30 30 60 50 0 to 70°C 280 165 20 20 50 35 –40 to 85°C 290 175 30 30 60 45 0 to 70°C 190 135 20 20 40 35 –40 to 85°C 200 145 30 30 50 45 Parameter Test Conditions Device Selected; All other inputs ≥VIH or ≤ VIL Output open ZZ ≥ VDD – 0.2 V Symbol IDD Pipeline IDD Flow-Thru ISB Pipeline ISB Flow-Thru IDD Pipeline IDD Flow-Thru 0 to 70°C 335 210 20 20 55 40 Unit mA mA mA mA mA mA Operating Current Standby Current Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Rev: 1.03 11/2004 16/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 AC Electrical Characteristics Parameter Clock Cycle Time Flow Through Symbol tKC tKQ tKQX tLZ 1 Min 9.1 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 Max — 8.0 — — — — 3.2 3.2 — 3.2 — — — — Min 10.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 Max — 8.5 — — — — 3.5 3.5 — 3.5 — — — — Min 12.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 1.5 0.5 5 1 -150 Max — 10.0 — — — — 3.8 3.8 — 3.8 — — — — Min 15.0 — 3.0 3.0 1.3 1.5 1.5 — 0 — 2.0 0.5 5 1 -100 Max — 12.0 — — — — 5 5 — 5 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 ZZ recovery tZZR 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03 11/2004 17/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Pipeline Mode Timing Write A Read B Suspend tKH tKL Read C tKC Write D writeno-op Read E Deselect CK tH tS A A tH tS B C D E CKE tH tS E* tH tS ADV tH tS W tH tS tS tH Bn tH tS tLZ tKQ Q(B) Q(C) D(D) Q(E) tHZ tKQX DQ D(A) Rev: 1.03 11/2004 18/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Flow Through Mode Timing Write A Write B Write B+1 tKL tKH CK Read C tKC Cont Read D Write E Read F Write G tH tS CKE tH tS E tH tS ADV tH tS W tH tS Bn tH tS A0–An A B C D E F G tKQ tH tS DQ D(A) D(B) tKQ tLZ D(B+1) Q(C) tKQX tHZ Q(D) tLZ D(E) Q(F) tKQX D(G) tOLZ tOE tOHZ G *Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1 JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.03 11/2004 19/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.03 11/2004 20/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 JTAG TAP Block Diagram · · · 108 · · · · · · · · 1 Boundary Scan Register 0 Bypass Register 210 0 Instruction Register TDI ID Code Register 31 30 29 TDO · ··· 210 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents TBD for this part. ID Register Contents Die Revision Code Bit # GSI Technology JEDEC Vendor ID Code Presence Register 0 Not Used I/O Configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Rev: 1.03 11/2004 21/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Rev: 1.03 11/2004 22/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.03 11/2004 23/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU Code 000 001 010 011 100 101 110 Description Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 1 1 1 1 1 BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ VILJ IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 0.6 * VDD –0.3 –300 –1 –1 1.7 — VDDQ – 100 mV Max. VDD +0.3 0.3 * VDD 1 100 1 — 0.4 — Unit Notes V V uA uA uA V V V 1 1 2 3 4 5, 6 5, 7 5, 8 — 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be –1 V > Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA Rev: 1.03 11/2004 24/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Test Port Input High Voltage Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ VILJ IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 0.6 * VDD –0.3 –300 –1 –1 1.7 — VDDQ – 100 mV Max. VDD2 +0.3 0.3 * VDD 1 100 1 — 0.4 — Unit Notes V V uA uA uA V V V 1 1 2 3 4 5, 6 5, 7 5, 8 — 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be – V > Vi < VDDn + V not to exceed .6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions VDD – 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ JTAG Port AC Test Load 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 1.03 11/2004 25/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 JTAG Port Timing Diagram tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 — 20 20 10 10 Max — 20 — — — — Unit ns ns ns ns ns ns Rev: 1.03 11/2004 26/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Output Driver Characteristics TBD Rev: 1.03 11/2004 27/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Package Dimensions—119-Bump FPBGA (Package B, Variation 1) Pin #1 Corner BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) 1 2 3 45 6 7 A B C D E F G H J K L M N P R T U Ø1.00(3x) REF 7 6 5 43 2 1 A B C D E F G H J K L M N P R T U 22±0.20 19.50 0.70 REF 12.00 B 1.27 7.62 A 0.20(4x) 14±0.20 0.90±0.10 0.15 C 0.56±0.05 0.50~0.70 2.06.±0.13 C SEATING PLANE 0.15 C 20.32 1.27 BPR 1999.05.18 Rev: 1.03 11/2004 28/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 Ordering Information—GSI NBT Synchronous SRAMs Org 256K x 18 256K x 18 256K x 18 256K x 18 128K x 36 128K x 36 128K x 36 128K x 36 256K x 18 256K x 18 256K x 18 256K x 18 128K x 36 128K x 36 128K x 36 Part Number1 GS842Z18AB-180 GS842Z18AB-166 GS842Z18AB-150 GS842Z18AB-100 GS842Z36AB-180 GS842Z36AB-166 GS842Z36AB-150 GS842Z36AB-100 GS842Z18AB-180I GS842Z18AB-166I GS842Z18AB-150I GS842Z18AB-100I GS842Z36AB-180I GS842Z36AB-166I GS842Z36AB-150I Type NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through Package BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) BGA (var. 1) Speed2 (MHz/ns) 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 100/12 180/8 166/8.5 150/10 TA3 C C C C C C C C I I I I I I I Status 128K x 36 GS842Z36AB-100I NBT Pipeline/Flow Through BGA (var. 1) 100/12 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS842Z36AB-100IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.03 11/2004 29/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS842Z18/36AB-180/166/150/100 4Mb Synchronous NBT Datasheet Revision History DS/DateRev. Code: Old; New 842Z18A_r1 Types of Changes Page /Revisions/Reason Format or Content • Creation of new datasheet • Updated power numbers in table on page 1 and Operating Currents table • Updated pinout for x18 • Updated Pin Description table • Removed ByteSafe references • Changed DP and QE to NC • Delete PE from entire document (changed to NC) • Removed 200 MHz speed bin • Removed pin locations from pin description table • Updated format • Updated timing diagrams • Added variation information to package mechanical 842Z18A_r1; 842Z18A_r1_01 Content 842Z18A_r1_01; 842Z18A_r1_02 842Z18A_r1_02; 842Z18A_r1_03 Content Format/Content Rev: 1.03 11/2004 30/30 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.