Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features
• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 1.8 V +10%/–10% core power supply and I/O supply • User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2Mb, 4Mb, 9Mb, 18Mb, and 36Mb devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down • JEDEC-standard 119-, 165- or 209-bump BGA package
72Mb Pipelined and Flow Through Synchronous NBT SRAM
250 MHz–133MHz 1.8 V VDD 1.8 V I/O
Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. The GS8644ZV18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS8644ZV18/36/72 is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump, 165-bump or 209-bump BGA package.
Functional Description
The GS8644ZV18/36/72 is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.
Parameter Synopsis
tKQ(x18/x36) tKQ(x72) tCycle Curr (x18) Curr (x36) Curr (x72) tKQ tCycle Curr (x18) Curr (x36) Curr (x72) -250 -225 -200 2.3 2.5 2.7 2.6 2.7 2.8 4.0 4.4 5.0 385 450 540 6.5 6.5 265 290 345 -166 2.9 2.9 6.0 -150 3.3 3.3 6.7 -133 Unit 3.5 ns 3.5 ns 7.5 ns
Pipeline 3-1-1-1
360 335 305 295 265 mA 415 385 345 325 295 mA 505 460 405 385 345 mA 6.5 6.5 6.5 6.5 8.0 8.0 8.5 8.5 8.5 8.5 ns ns
Flow Through 2-1-1-1
265 265 255 240 225 mA 290 290 280 265 245 mA 345 345 335 315 300 mA
Rev: 1.03 11/2004
1/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV72C Pad Out—209-Bump BGA—Top View (Package C)
1 A B C D E F G H J K L M N P R T U V W DQG DQG DQG DQG DQPG DQC DQC DQC DQC NC DQH DQH DQH DQH DQPD DQD DQD DQD DQD 2 DQG DQG DQG DQG DQPC DQC DQC DQC DQC NC DQH DQH DQH DQH DQPH DQD DQD DQD DQD 3 A BC BH VSS VDDQ VSS VDDQ VSS VDDQ CK VDDQ VSS VDDQ VSS VDDQ VSS NC A TMS 4 E2 BG BD NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 A NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 6 ADV W E1 G VDD ZQ MCH MCL MCH CKE FT MCL MCH ZZ VDD LBO A A1 A0 7 A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 E3 BB BE NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BF BA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC A TCK 10 DQB DQB DQB DQB DQPF DQF DQF DQF DQF NC DQA DQA DQA DQA DQPA DQE DQE DQE DQE 11 DQB DQB DQB DQB DQPB DQF DQF DQF DQF NC DQA DQA DQA DQA DQPE DQE DQE DQE DQE A B C D E F G H J K L M N P R T U V W
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.03 11/2004
2/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV72 209-Bump BGA Pin Description Symbol
A 0, A 1 A DQA DQB DQC DQD DQE DQF DQG DQH BA, BB BC,BD BE, BF, BG,BH NC CK E1 E3 E2 G ADV ZZ FT LBO MCH MCH MCL W ZQ CKE I I I
Type
I I
Description
Address field LSBs and Address Counter Preset Inputs. Address Inputs
I/O
Data Input and Output pins
I I I — I I I I I I I I I I I
Byte Write Enable for DQA, DQB I/Os; active low Byte Write Enable for DQC, DQD I/Os; active low Byte Write Enable for DQE, DQF, DQG, DQH I/Os; active low No Connect Clock Input Signal; active high Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Must Connect High Must Connect High Must Connect Low Write Enable; active low FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive] Clock Enable; active low
Rev: 1.03 11/2004
3/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV72 209-Bump BGA Pin Description (Continued) Symbol
TMS TDI TDO TCK VDD VSS VDDQ
Type
I I O I I I I
Description
Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
Rev: 1.03 11/2004
4/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV36B Pad Out—119-Bump BGA—Top View (Package B)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A E2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A A TMS 3 A A A VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A TDI 4 A ADV VDD ZQ E1 G A W VDD CK NC CKE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A TDO 6 A E3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A A NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ A B C D E F G H J K L M N P R T U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.03 11/2004
5/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV18B Pad Out—119-Bump BGA—Top View (Package B)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC A VDDQ 2 A E2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A TDI 4 A ADV VDD ZQ E1 G A W VDD CK NC CKE A1 A0 VDD A TCK 5 A A A VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A TDO 6 A E3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ A B C D E F G H J K L M N P R T U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.03 11/2004
6/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV18/36 119-Bump BGA Pin Description Symbol
A 0, A 1 A DQA DQB DQC DQD BA , BB , BC , BD NC CK CKE W E1 E3 E2 G ADV ZZ FT LBO ZQ TMS TDI TDO TCK VDD VSS VDDQ
Type
I I I/O I — I I I I I I I I I I I I I I O I I I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low No Connect Clock Input Signal; active high Clock Enable; active low Write Enable; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable Sleep mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply
BPR1999.05.18
Rev: 1.03 11/2004
7/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
165 Bump BGA—x18 Common I/O—Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC FT DQB DQB DQB DQB DQPB NC LBO 2 A A NC DQB DQB DQB DQB MCH NC NC NC NC NC A A 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC ZQ DQA DQA DQA DQA NC A A 11 A NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC A A B C D E F G H J K L M N P R
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.03 11/2004
8/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
165 Bump BGA—x36 Common I/O—Top View (Package E)
1 A B C D E F G H J K L M N P R NC NC DQPC DQC DQC DQC DQC FT DQD DQD DQD DQD DQPD NC LBO 2 A A NC DQC DQC DQC DQC MCH DQD DQD DQD DQD NC A A 3 E1 E2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BC BD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BB BA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 E3 CK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0 7 CKE W VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV G VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQB DQB DQB DQB ZQ DQA DQA DQA DQA NC A A 11 NC NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC A A B C D E F G H J K L M N P R
11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch
Rev: 1.03 11/2004
9/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
GS8644ZV18/36E 165-Bump BGA Pin Description Symbol
A 0, A 1 A DQA DQB DQC DQD BA , BB , BC , BD NC CK CKE W E1 E3 E2 FT G ADV ZQ ZZ LBO TMS TDI TDO TCK MCH VDD VSS VDDQ
Type
I I I/O I — I I I I I I I I I I I I I I O I — I I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low No Connect Clock Input Signal; active high Clock Enable; active low Write Enable; active low Chip Enable; active low Chip Enable; active low Chip Enable; active high Flow Through / Pipeline Mode Control Output Enable; active low Burst address counter advance enable; active high FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Sleep mode control; active high Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High Core power supply I/O and Core Ground Output driver power supply
Rev: 1.03 11/2004
10/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Functional Details
Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. Function Read Write Byte “a” Write Byte “b” Write Byte “c” Write Byte “d” Write all Bytes Write Abort/NOP W H L L L L L L BA X L H H H L H BB X H L H H L H BC X H H L H L H BD X H H H L L H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.
Rev: 1.03 11/2004
11/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Synchronous Truth Table Operation
Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst Write Abort, Continue Burst Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle Deselect Cycle, Continue Sleep Mode Clock Edge Ignore, Stall
Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ
R B R B W B B D D D D D External Next External Next External Next Next None None None None None None Current L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X L-H L L L L L L L L L L L L X H L H L H L H H L L L L H X X H X H X L X X X X X L X X X X X X X L L H X X X H X X X L X L X L X X H X X L X X X H X H X H X X X X L H X X X L X L X L X X X H X L X X X L L H H X X X X X X X X X X L L L L L L L L L L L L H L
DQ
Q Q High-Z High-Z D D
Notes
1,10 2 1,2,10 3 1,3,10
High-Z 1,2,3,10 High-Z High-Z High-Z High-Z High-Z High-Z 4 1 1
Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles.
Rev: 1.03 11/2004
12/37
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Pipelined and Flow Through Read Write Control State Diagram
D
B
Deselect
R
W
D
D W R
R
New Read
B
New Write
W B
R
W
R
W
B
Burst Read
D
Burst Write
D
B
Key
Input Command Code
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change.
ƒ Transition
Current State (n) Next State (n+1)
n n+1
2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. n+2 n+3
Clock (CK)
Command
ƒ
Current State
ƒ
Next State
ƒ
ƒ
Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram
Rev: 1.03 11/2004
13/37
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Pipeline Mode Data I/O State Diagram
Intermediate
BW High Z (Data In) D
R
Intermediate W Intermediate Intermediate
RB Data Out (Q Valid) D
Intermediate
W
R
High Z B D
Intermediate
Key
Input Command Code
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change.
ƒ Transition
Current State (n)
Transition Next State (n+2)
Intermediate State (N+1)
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
Current State
ƒ
Intermediate State
ƒ
Next State
ƒ
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 1.03 11/2004
14/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Flow Through Mode Data I/O State Diagram
BW High Z (Data In) D
R W
RB Data Out (Q Valid) D
W
R
High Z B D
Key
Input Command Code
Notes
1. The Hold command (CKE Low) is not shown because it prevents any state change.
ƒ Transition
Current State (n) Next State (n+1)
n n+1
2. W, R, B, and D represent input command codes as indicated in the Truth Tables.
n+2
n+3
Clock (CK)
Command
ƒ
Current State
ƒ
Next State
ƒ
ƒ
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 1.03 11/2004
15/37
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. FLXDrive™ The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control FLXDrive Output Impedance Control
Pin Name
LBO FT ZZ ZQ
State
L H L H or NC L or NC H L H or NC
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB High Drive (Low Impedance) Low Drive (High Impedance)
Note: There are pull-up devices onthe ZQ and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.
Rev: 1.03 11/2004
16/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Burst Counter Sequences
Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tKH tKC CK tZZR tZZS ZZ tZZH tKL
Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal. Not all vendors offer this option, however most mark the pin VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Other vendors mark the pin as a No Connect (NC). GSI RAMs have an internal pull-up device on the FT pin so a floating FT pin will result in pipelined operation. If the part being replaced is a pipelined mode part, the GSI RAM is fully compatible with these sockets. In the unlikely event the part being replaced is a Flow Through device, the pin will need to be pulled low for correct operation.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS
Note:
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
–0.5 to 3.6 –0.5 to 3.6 –0.5 to VDDQ +0.5 (≤ 3.6 V max.) –0.5 to VDD +0.5 (≤ 3.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125
Unit
V V V V mA mA W
o
C
oC
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Power Supply Voltage Ranges Parameter
1.8 V Supply Voltage 1.8 V VDDQ I/O Supply Voltage
Symbol
VDD1 VDDQ1
Min.
1.6 1.6
Typ.
1.8 1.8
Max.
2.0 2.0
Unit
V V
Notes
Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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VDDQ Range Logic Levels Parameter
VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage
Symbol
VIH VIL VIHQ VILQ
Min.
0.6*VDD –0.3 0.6*VDD –0.3
Typ.
— — — —
Max.
VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD
Unit
V V V V
Notes
1 1 1,3 1,3
Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Undershoot Measurement and Timing
VIH
Overshoot Measurement and Timing
20% tKC VDD + 2.0 V
VSS 50% VSS – 2.0 V 20% tKC
50% VDD
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
8 12
Max.
10 14
Unit
pF pF
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table.
Output Load 1 DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF*
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current FT and ZQ Input Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL IIN1 IIN2 IOL VOH1 VOL1
Test Conditions
VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –4 mA, VDDQ = 1.6 V IOL = 4 mA, VDD = 1.6 V
Min
–1 uA –1 uA –1 uA –100 uA –1 uA –1 uA VDDQ – 0.4 V —
Max
1 uA 1 uA 100 uA 1 uA 1 uA 1 uA — 0.4 V
Rev: 1.03 11/2004
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Operating Currents
-250 Mode Symbol 0 to 70°C Unit 480 60 315 30 400 50 270 20 360 25 250 15 120 120 200 170 200 170 230 190 220 200 160 120 160 120 180 160 160 120 160 120 160 160 210 190 275 15 250 15 275 15 250 15 275 15 240 15 120 120 170 160 395 25 335 25 370 25 315 20 350 20 285 20 320 20 260 15 160 160 200 190 295 20 270 20 295 20 270 20 295 20 260 20 285 20 245 20 275 20 225 15 120 120 170 150 435 50 370 45 405 45 345 40 380 40 310 35 345 35 295 30 330 30 270 20 310 20 250 15 160 160 200 180 340 30 315 30 340 30 315 30 340 30 305 30 330 30 285 30 310 30 280 20 270 25 230 15 250 15 210 15 120 120 160 140 515 60 445 60 480 60 410 50 445 50 365 40 400 40 345 40 380 40 315 30 350 30 305 20 305 25 255 15 285 15 235 15 160 160 190 170
mA mA mA mA mA mA mA mA mA mA
-225 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C
-200
-166
-150
-133
Rev: 1.03 11/2004 –40 to 85°C Pipeline (x72) Flow Through Pipeline (x36) Flow Through IDDQ IDD IDDQ IDD IDDQ ISB ISB IDD IDD Pipeline (x18) Flow Through Pipeline — Flow Through Pipeline — Flow Through IDD IDD IDDQ IDD IDDQ IDD IDDQ
Parameter
Test Conditions
Operating Current
Device Selected; All other inputs ≥VIH or ≤ VIL Output open
21/37
Standby Current
ZZ ≥ VDD – 0.2 V
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Deselect Current
Device Deselected; All other inputs ≥ VIH or ≤ VIL
Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario.
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© 2003, GSI Technology
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AC Electrical Characteristics
Parameter Clock Cycle Time Clock to Output Valid (x18/x36) Clock to Output Valid (x72) Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z (x18/x36) Clock to Output in High-Z (x72) G to Output Valid (x18/x36) G to Output Valid (x72) G to output in Low-Z G to output in High-Z (x18/x36) G to output in High-Z (x72) ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQ tKQX tLZ1 tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tHZ1 tOE tOE tOLZ1 tOHZ1 tOHZ1 tZZS2 tZZH tZZR
2
-250 Min 4.0 — — 1.0 1.0 1.3 0.2 6.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.0 Max — 2.3 2.6 — — — — — 6.5 — — — — — — 2.3
-225 Min 4.4 — — 1.0 1.0 1.3 0.3 6.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.0 Max — 2.5 2.7 — — — — — 6.5 — — — — — — 2.5
-200 Min 5.0 — — 1.0 1.0 1.4 0.4 6.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.0 Max — 2.7 2.8 — — — — — 6.5 — — — — — — 2.7
-166 Min 6.0 — — 1.0 1.0 1.5 0.5 7.0 — 3.0 3.0 1.5 0.5 1.3 1.5 1.0 Max — 2.9 2.9 — — — — — 7.0 — — — — — — 2.9
-150 Min 6.7 — — 1.0 1.0 1.5 0.5 7.5 — 3.0 3.0 1.5 0.5 1.5 1.7 1.0 Max — 3.3 3.3 — — — — — 7.5 — — — — — — 3.0
-133 Min 7.5 — — 1.0 1.0 1.5 0.5 8.5 — 3.0 3.0 1.5 0.5 1.7 2 1.0 Max — 3.5 3.5 — — — — — 8.5 — — — — — — 3.0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Pipeline
Flow Through
1.0 — — 0 — — 5 1 20
2.6 2.3 2.6 — 2.3 2.6 — — —
1.0 — — 0 — — 5 1 20
2.7 2.5 2.7 — 2.5 2.7 — — —
1.0 — — 0 — — 5 1 20
2.8 2.7 2.8 — 2.7 2.8 — — —
1.0 — — 0 — — 5 1 20
2.9 2.9 2.9 — 2.9 2.9 — — —
1.0 — — 0 — — 5 1 20
3.0 3.3 3.3 — 3.0 3.0 — — —
1.0 — — 0 — — 5 1 20
3.0 3.5 3.5 — 3.0 3.0 — — —
ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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Pipeline Mode Timing (NBT)
Write A Read B Suspend tKH tKL Read C tKC Write D writeno-op Read E Deselect
CK
tH tS
A
A tH tS
B
C
D
E
CKE
tH tS
E*
tH tS
ADV
tH tS
W
tH tS tS tH
Bn
tH tS tLZ tKQ Q(B) Q(C) D(D) Q(E) tHZ tKQX
DQ
D(A)
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Flow Through Mode Timing (NBT)
Write A Write B Write B+1 tKL tKH
CK
Read C tKC
Cont
Read D
Write E
Read F
Write G
tH tS
CKE
tH tS
E
tH tS
ADV
tH tS
W
tH tS
Bn
tH tS
A0–An A B C D E F G
tKQ tH tS
DQ D(A) D(B)
tKQ tLZ
D(B+1) Q(C)
tKQX tHZ
Q(D)
tLZ
D(E) Q(F)
tKQX
D(G)
tOLZ tOE tOHZ
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
JTAG Port Operation
Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ.
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Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions Pin
TCK TMS
Pin Name
Test Clock Test Mode Select
I/O
In In
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.
TDI
Test Data In
In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
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JTAG TAP Block Diagram (2-die module)
· · ·
108
·
·
·
·
·
·
· ·
1
· · ·
108
·
·
·
·
·
·
· ·
1
Boundary Scan Register
Boundary Scan Register
0
Bypass Register
210
0
0
Bypass Register
210
0
Instruction Register TDI ID Code Register
31 30 29
TDO
TDI
Instruction Register TDO ID Code Register
·
· ··
210
31 30 29
·
· ··
210
· TCK ·
TMS
Control Signals Test Access Port (TAP) Controller
Control Signals Test Access Port (TAP) Controller
Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Tap Controller Instruction Set
Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
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JTAG Tap Controller State Diagram
1
Test Logic Reset
0 1 1 1
0
Run Test Idle
Select DR
0 1
Select IR
0 1
Capture DR
0
Capture IR
0
Shift DR
1 1
0 1
Shift IR
1
0
Exit1 DR
0
Exit1 IR
0
Pause DR
1
0
Pause IR
1
0
Exit2 DR
1
0
Exit2 IR
1
0
Update DR
1 0
Update IR
1 0
Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins.
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EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
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JTAG Port AC Test Conditions
Parameter
Input high level Input low level Input slew rate Input reference level Output reference level
Conditions
VDD – 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ
JTAG Port AC Test Load
50Ω VDDQ/2
* Distributed Test Jig Capacitance
30pF*
Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted.
JTAG TAP Instruction Set Summary Instruction
EXTEST IDCODE SAMPLE-Z RFU SAMPLE/ PRELOAD GSI RFU BYPASS
Code
000 001 010 011 100 101 110 111
Description
Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO.
Notes
1 1, 2 1 1 1 1 1 1
Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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JTAG Port Recommended Operating Conditions and DC Characteristics Parameter
1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low
Symbol
VIHJ VILJ IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
0.6 * VDD –0.3 –300 –1 –1 1.7 — VDDQ – 100 mV —
Max.
VDD +0.3 0.3 * VDD 1 100 1 — 0.4 — 100 mV
Unit Notes
V V uA uA uA V V V V 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9
Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA
JTAG Port Timing Diagram
tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input
tTKH
tTKL
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JTAG Port AC Electrical Characteristics
Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 — 20 20 10 10 Max — 20 — — — — Unit ns ns ns ns ns ns
Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com.
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209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C A1 A aaa D D1
Side View
e
Bottom View
E1 ∅b e
Symbol A A1 ∅b c D Rev 1.0
Min — 0.40 0.50 0.31 21.9
Typ — 0.50 0.60 0.36 22.0
Max 1.70 0.60 0.70 0.38 22.1
Units mm mm mm mm mm
Symbol D1 E E1 e aaa
Min — 13.9 — — —
Typ 18.0 (BSC) 14.0 10.0 (BSC) 1.00 (BSC) 0.15
E
Max — 14.1 — — —
Units mm mm mm mm mm
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© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Package Dimensions—165-Bump FPBGA (Package E; Variation 1)
A1
TOP VIEW
BOTTOM Ø0.10M C Ø0.25M C A B Ø0.44~0.64(165x)
VIEW
A1
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H I J K L M N P R
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
1.0 10.0 1.0
17±0.05
14.0
A
0.53 REF 0.35 C
1.0
1.0
0.20 C
B 0.20(4x)
15±0.05
0.36 REF
Rev: 1.03 11/2004
0.36~0.46 1.40 MAX.
C
SEATING PLANE
33/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
A1 1
A B C D E F G H J K L M N P R T U
TOP VIEW
BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x)
2
3
4
5
6
7
7 6 5 43 2 1
A B C D E F G H J K L M N P R T U
22±0.10
B 0.70±0.05 0.15 C 1.27 7.62 0.15 C A 0.20(4x) 14±0.10
0.56±0.05
Rev: 1.03 11/2004
0.50~0.70 1.86.±0.13
C
SEATING PLANE
34/37
20.32
1.27
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Ordering Information for GSI Synchronous Burst RAMs Org
4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 1M x 72 1M x 72 1M x 72 1M x 72 1M x 72
Part Number1
GS8644ZV18B-250 GS8644ZV18B-225 GS8644ZV18B-200 GS8644ZV18B-166 GS8644ZV18B-150 GS8644ZV18B-133 GS8644ZV18E-250 GS8644ZV18E-225 GS8644ZV18E-200 GS8644ZV18E-166 GS8644ZV18E-150 GS8644ZV18E-133 GS8644ZV36B-250 GS8644ZV36B-225 GS8644ZV36B-200 GS8644ZV36B-166 GS8644ZV36B-150 GS8644ZV36B-133 GS8644ZV36E-250 GS8644ZV36E-225 GS8644ZV36E-200 GS8644ZV36E-166 GS8644ZV36E-150 GS8644ZV36E-133 GS8644ZV72C-250 GS8644ZV72C-225 GS8644ZV72C-200 GS8644ZV72C-166 GS8644ZV72C-150
Type
NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
Package
119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA
Speed2 (MHz/ns)
250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5
TA3
C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
1M x 72 GS8644ZV72C-133 NBT Pipeline/Flow Through 209 BGA 133/8.5 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644ZV18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03 11/2004
35/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
Ordering Information for GSI Synchronous Burst RAMs (Continued) Org
4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 4M x 18 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 2M x 36 1M x 72 1M x 72 1M x 72 1M x 72 1M x 72
Part Number1
GS8644ZV18B-250I GS8644ZV18B-225I GS8644ZV18B-200I GS8644ZV18B-166I GS8644ZV18B-150I GS8644ZV18B-133I GS8644ZV18E-250I GS8644ZV18E-225I GS8644ZV18E-200I GS8644ZV18E-166I GS8644ZV18E-150I GS8644ZV18E-133I GS8644ZV36B-250I GS8644ZV36B-225I GS8644ZV36B-200I GS8644ZV36B-166I GS8644ZV36B-150I GS8644ZV36B-133I GS8644ZV36E-250I GS8644ZV36E-225I GS8644ZV36E-200I GS8644ZV36E-166I GS8644ZV36E-150I GS8644ZV36E-133I GS8644ZV72C-250I GS8644ZV72C-225I GS8644ZV72C-200I GS8644ZV72C-166I GS8644ZV72C-150I
Type
NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through NBT Pipeline/Flow Through
Package
119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 119 BGA (var. 2) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 165 BGA (var. 1) 209 BGA 209 BGA 209 BGA 209 BGA 209 BGA
Speed2 (MHz/ns)
250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5 133/8.5 250/6.5 225/6.5 200/6.5 166/8 150/8.5
TA3
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I
1M x 72 GS8644ZV72C-133I NBT Pipeline/Flow Through 209 BGA 133/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8644ZV18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.03 11/2004
36/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Product Preview GS8644ZV18(B/E)/GS8644ZV36(B/E)/GS8644ZV72(C)
72Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
New 8644ZVxx_r1 8644ZVxx_r1; 8644ZVxx_r1_01 Content
Types of Changes Page;Revisions;Reason Format or Content
• Creation of new datasheet • Updated Operating Currents table • Updated FT AC Characteristics for tKQ • Updated FT tKQ and PL tS/tH and FT current numbers for 250 and 225 MHz (match 200 MHz) • Updated basic format • Updated Synchronous Truth Table • Added thermal characteristics to mechanical drawings • Updated JTAG section for module • Updated format • Added variation information to package mechanicals
8644ZVxx_r1_01; 8644ZVxx_r1_02
Content
8644ZVxx_r1_02; 8644ZVxx_r1_03
Format/Content
Rev: 1.03 11/2004
37/37
© 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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