GS88037BT-250V

GS88037BT-xxxV 100-Pin TQFP Commercial Temp Industrial Temp Features • Single Cycle Deselect (SCD) operation • 1.8 V or 2.5 V +10%/–10% core power supply • 1.8 V or 2.5 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package • RoHS-compliant 100-lead TQFP package available 256K x 36 9Mb Sync Burst SRAM 250 MHz–200 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. SCD Pipelined Reads The GS88037BT-xxxV is a SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS88037BT-xxxV operates on a 1.8 V or 2.5 V power supply. All input are 2.5 V and 1.8 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 2.5 V and 1.8 V compatible. Functional Description Applications The GS88037BT-xxxV is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Parameter Synopsis Pipeline 3-1-1-1 tKQ tCycle Curr (x36) -250 2.5 4.0 330 -200 2.5 5.0 270 Unit ns ns mA Rev: 1.03 6/2006 1/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV GS88037BT-xxxV 100-Pin TQFP Pinout DQPC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC VDDQ/DNU VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA Rev: 1.03 6/2006 LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 2/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV TQFP Pin Description Symbol A 0, A 1 A DQA DQB DQC DQD NC BW BA , BB BC , BD CK GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ LBO VDD VSS VDDQ VDDQ/DNU Type I I Description Address field LSBs and Address Counter preset Inputs Address Inputs I/O Data Input and Output pins — I I I I I I I I I I I I I I I — No Connect Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Byte Write Enable for DQC, DQD Data I/Os; active low Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply VDDQ or VDD (must be tied high) or Do Not Use (must be left floating) Rev: 1.03 6/2006 3/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV GS88037BT-xxxV Block Diagram A0–An Register D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E2 E3 Register D Q Register D Q 1 G Power Down Control ZZ SCD=1 DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.03 6/2006 4/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Mode Pin Functions Mode Name Burst Order Control Power Down Control Pin Name LBO ZZ State L H L or NC H Function Linear Burst Interleaved Burst Active Standby, IDD = ISB Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.03 6/2006 5/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes GW H H H H H H H BW H L L L L L L BA X H L H H H L BB X H H L H H L BC X H H H L H L BD X H H H H L L Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.03 6/2006 6/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X H E2 X F F T T T X X X X X X X X ADSP ADSC X L H L H H H X H X H X H X L X L X L L H H H H H H H H ADV X X X X X X L L L L H H H H W3 X X X X F T F F T T F F T T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.03 6/2006 7/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.03 6/2006 8/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03 6/2006 9/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage on VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to VDD –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V mA mA W o o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version) Parameter 1.8 V Supply Voltage 2.5 V Supply Voltage 1.8 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD1 VDD2 VDDQ1 VDDQ2 Min. 1.7 2.3 1.7 2.3 Typ. 1.8 2.5 1.8 2.5 Max. 2.0 2.7 VDD VDD Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03 6/2006 10/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV VDDQ2 & VDDQ1 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage Symbol VIH VIL Min. 0.6*VDD –0.3 Typ. — — Max. VDD + 0.3 0.3*VDD Unit V V Notes 1 1 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing VIH Overshoot Measurement and Timing 20% tKC VDD + 2.0 V VSS 50% VSS – 2.0 V 20% tKC 50% VDD VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF Rev: 1.03 6/2006 11/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 VDDQ/2 * Distributed Test Jig Capacitance Figure 1 Output Load 1 DQ 50Ω 30pF* Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) FT, ZZ Input Current Output Leakage Current Symbol IIL IIN IOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ 0 V Output Disable, VOUT = 0 to VDD Min –1 uA –100 uA –1 uA Max 1 uA 100 uA 1 uA DC Output Characteristics (1.8 V/2.5 V Version) Parameter 1.8 V Output High Voltage 2.5 V Output High Voltage 1.8 V Output Low Voltage 2.5 V Output Low Voltage Symbol VOH1 VOH2 VOL1 VOL2 Test Conditions IOH = –4 mA, VDDQ = 1.6 V IOH = –8 mA, VDDQ = 2.375 V IOL = 4 mA IOL = 8 mA Min VDDQ – 0.4 V 1.7 V — — Max — — 0.4 V 0.4 V Rev: 1.03 6/2006 12/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Operating Currents -250 Parameter Test Conditions Device Selected; All other inputs ≥VIH or ≤ VIL Output open ZZ ≥ VDD – 0.2 V Device Deselected; All other inputs ≥ VIH or ≤ VIL Mode Symbol 0 to 70°C 290 40 -200 –40 to 85°C 250 30 Unit –40 0 to 85°C to 70°C 300 40 240 30 Operating Current Standby Current Deselect Current (x36) Pipeline IDD IDDQ ISB IDD mA — Pipeline 40 50 40 50 mA — Pipeline 85 90 75 80 mA Notes: 1. IDD and IDDQ apply to any combination of VDD1, VDD2, VDDQ1, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Rev: 1.03 6/2006 13/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time G to Output Valid G to output in High-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to output in Low-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ1 tS tH tOE tOHZ1 tKH tKL tHZ1 tOLZ1 tZZS2 tZZH2 tZZR -250 Min 4.0 — 1.0 1.0 1.2 0.2 — — 1.3 1.7 1.0 0 5 1 20 Max — 2.5 — — — — 2.3 2.3 — — 2.3 — — — — Min 5.0 — 1.0 1.0 1.4 0.4 — — 1.3 1.7 1.0 0 5 1 20 -200 Max — 2.5 — — — — 2.5 2.5 — — 2.5 — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03 6/2006 14/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Pipeline Mode Timing (+1) Begin Read A Cont Cont Deselect Write B tKC tKH tKL Read C Read C+1 Read C+2 Read C+3 Cont Deselect CK ADSP tS tH ADSC tS ADV tS tH A0–An A B C ADSC initiated read tH tS GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa–DQd tOHZ Q(A) D(B) E2 and E3 only sampled with ADSC Deselected with E1 tH tH tKQ tLZ Q(C) Q(C+1) Q(C+2) tKQX tHZ Q(C+3) Rev: 1.03 6/2006 15/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.03 6/2006 16/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV TQFP Package Drawing (Package T) L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c Pin 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — 0.45 — 0.10 1.40 0.30 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 0.75 — 0.10 L1 e b D D1 A1 Y A2 E1 E 0° — 7° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.03 6/2006 17/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV Ordering Information for GSI Synchronous Burst RAMs Org 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 Part Number1 GS88037BT-250V GS88037BT-200V GS88037BT-250IV GS88037BT-200IV GS88037BGT-250V GS88037BGT-200V GS88037BGT-250IV GS88037BGT-200IV Type Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Voltage Option 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V 1.8 V or 2.5 V Package TQFP TQFP TQFP TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP RoHS-compliant TQFP Speed (MHz) 250 200 250 200 250 200 250 200 TA2 C C I I C C I I Status3 MP MP MP MP PQ PQ PQ PQ Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88037BT-200IT. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 3. MP = Mass Production. PQ = Pre-Qualification. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03 6/2006 18/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88037BT-xxxV 9Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 880V37B_r1 880V37B_r1; 880V37B_r1_01 880V37B_r1_01; 880V37B_r1_02 880V37B_r1_02; 88037B_V_r1_03 Content/Format Content/Format Content/Format Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet • Added 360 MHz • Removed all speed bins below 300 MHz • Updated format • Added Pb-free information for TQFP • Updated entire document to reflect new part nomenclature Rev: 1.03 6/2006 19/19 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.