GS880E32AT-200I

GS880E18/32/36AT-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package 512K x 18, 256K x 32, 256K x 36 9Mb Synchronous Burst SRAMs 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register. DCD Pipelined Reads The GS880E18/32/36AT is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS880E18/32/36AT operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Functional Description Applications The GS880E18/32/36AT is a 9,437,184-bit (8,388,608-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or Parameter Synopsis -250 Pipeline 3-1-1-1 tKQ tCycle Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) 2.5 4.0 280 330 5.5 5.5 175 200 -225 2.7 4.4 255 300 6.0 6.0 165 190 -200 3.0 5.0 230 270 6.5 6.5 160 180 -166 3.4 6.0 200 230 7.0 7.0 150 170 -150 3.8 6.7 185 215 7.5 7.5 145 165 -133 4.0 7.5 165 190 8.5 8.5 135 150 Unit ns ns mA mA ns ns mA mA Flow Through 2-1-1-1 Rev: 1.03 11/2004 1/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E18A 100-Pin TQFP Pinout (Package T) VDDQ VSS NC NC DQ B DQB VSS VDDQ DQ B DQB FT VDD NC VSS DQ B DQB VDDQ VSS DQ B DQB DQPB NC VSS VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 512K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Rev: 1.03 11/2004 LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 2/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E32A 100-Pin TQFP Pinout (Package T) NC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC FT VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA7 DQA NC Rev: 1.03 11/2004 LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 3/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E36A 100-Pin TQFP Pinout (Package T) DQPC DQC DQC VDDQ VSS DQC DQC DQ C DQC VSS VDDQ DQ C DQC FT VDD NC VSS DQ D DQD VDDQ VSS DQ D DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA Rev: 1.03 11/2004 LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 4/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 TQFP Pin Description Symbol A 0, A 1 An DQA DQB DQC DQD NC BW BA, BB, BC, BD CK GW E 1, E 3 E2 G ADV ADSP, ADSC ZZ FT LBO VDD VSS VDDQ Type I I I/O — I I I I I I I I I I I I I I I Description Address field LSBs and Address Counter preset Inputs Address Inputs Data Input and Output pin No Connect Byte Write—Writes all enabled bytes; active low Byte Write Enable for DQA, DQB Data I/Os; active low Clock Input Signal; active high Global Write Enable—Writes all bytes; active low Chip Enable; active low Chip Enable; active high Output Enable; active low Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply Rev: 1.03 11/2004 5/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 GS880E18/32/36A Block Diagram A0–An Register D Q A0 D0 A1 Q0 D1 Q1 Counter Load A0 A1 A LBO ADV CK ADSC ADSP GW BW BA Register Memory Array Q D Q D Register D BB Q 36 4 36 Register D BC Q Q Register D Register Q Register D D BD Q Register D Q E1 E2 E3 Register D Q Register D Q FT G Power Down Control ZZ DCD=1 DQx1–DQx9 Note: Only x36 version shown for simplicity. Rev: 1.03 11/2004 6/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Mode Pin Functions Mode Name Burst Order Control Power Down Control Pin Name LBO ZZ State L H L or NC H Function Linear Burst Interleaved Burst Active Standby, IDD = ISB Note: There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.03 11/2004 7/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Byte Write Truth Table Function Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes GW H H H H H H H BW H L L L L L L BA X H L H H H L BB X H H L H H L BC X H H H L H L BD X H H H H L L Notes 1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.03 11/2004 8/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Synchronous Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None External External External Next Next Next Next Current Current Current State Diagram Key5 X X X R R W CR CR CW CW E1 H L L L L L X H X H X H X E2 X F F T T T X X X X X X X ADSP ADSC X L H L H H H X H X H X H L X L X L L H H H H H H H ADV X X X X X X L L L L H H H W3 X X X X F T F F T T F F T DQ4 High-Z High-Z High-Z Q Q D Q Q D D Q Q D Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low 2. E = T (True) if E2 = 1; E = F (False) if E2 = 0 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.03 11/2004 9/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Simplified State Diagram X Deselect W W Simple Synchronous Operation R R X CW First Write R CR First Read X CR Simple Burst Synchronous Operation W R X Burst Write CR CW R Burst Read X CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low. Rev: 1.03 11/2004 10/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Simplified State Diagram with G X Deselect W W X W CW R R First Write R CR First Read X CR CW W X Burst Write R CR W CW R X Burst Read CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03 11/2004 11/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT PD TSTG TBIAS Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias Value –0.5 to 4.6 –0.5 to 4.6 –0.5 to VDDQ +0.5 (≤ 4.6 V max.) –0.5 to VDD +0.5 (≤ 4.6 V max.) +/–20 +/–20 1.5 –55 to 125 –55 to 125 Unit V V V V mA mA W o o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter 3.3 V Supply Voltage 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage 2.5 V VDDQ I/O Supply Voltage Symbol VDD3 VDD2 VDDQ3 VDDQ2 Min. 3.0 2.3 3.0 2.3 Typ. 3.3 2.5 3.3 2.5 Max. 3.6 2.7 3.6 2.7 Unit V V V V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03 11/2004 12/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 VDDQ3 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 2.0 –0.3 2.0 –0.3 Typ. — — — — Max. VDD + 0.3 0.8 VDDQ + 0.3 0.8 Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter VDD Input High Voltage VDD Input Low Voltage VDDQ I/O Input High Voltage VDDQ I/O Input Low Voltage Symbol VIH VIL VIHQ VILQ Min. 0.6*VDD –0.3 0.6*VDD –0.3 Typ. — — — — Max. VDD + 0.3 0.3*VDD VDDQ + 0.3 0.3*VDD Unit V V V V Notes 1 1 1,3 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol TA TA Min. 0 –40 Typ. 25 25 Max. 70 85 Unit °C °C Notes 2 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.03 11/2004 13/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Undershoot Measurement and Timing VIH VDD + 2.0 V VSS 50% VSS – 2.0 V 50% tKC VIL 50% VDD Overshoot Measurement and Timing 50% tKC Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Input Capacitance Input/Output Capacitance Note: These parameters are sample tested. Symbol CIN CI/O Test conditions VIN = 0 V VOUT = 0 V Typ. 4 6 Max. 5 7 Unit pF pF AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Conditions VDD – 0.2 V 0.2 V 1 V/ns VDD/2 VDDQ/2 Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω VDDQ/2 * Distributed Test Jig Capacitance 30pF* Rev: 1.03 11/2004 14/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Symbol IIL IIN1 IIN2 IOL VOH2 VOH3 VOL Test Conditions VIN = 0 to VDD VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Disable, VOUT = 0 to VDD IOH = –8 mA, VDDQ = 2.375 V IOH = –8 mA, VDDQ = 3.135 V IOL = 8 mA Min –1 uA –1 uA –1 uA –100 uA –1 uA –1 uA 1.7 V 2.4 V — Max 1 uA 1 uA 100 uA 1 uA 1 uA 1 uA — — 0.4 V Rev: 1.03 11/2004 15/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Operating Currents -250 Mode Symbol 0 to 70°C Unit 290 40 180 20 260 20 165 10 20 20 85 60 65 60 65 50 55 90 80 85 75 80 30 20 30 20 30 20 64 50 30 20 30 20 30 20 30 30 70 55 175 10 155 10 165 10 150 10 160 10 140 10 150 10 135 10 20 20 60 50 270 20 235 20 245 20 215 15 225 15 185 15 195 15 170 15 180 15 145 10 30 30 65 55 190 20 170 20 180 20 165 15 175 15 155 15 165 15 150 15 160 15 140 10 155 10 125 10 20 20 50 45 300 40 265 35 275 35 240 30 250 30 205 25 215 25 190 25 200 25 170 20 180 20 150 10 165 10 135 10 30 30 55 50 mA mA mA mA mA mA mA mA -225 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C -200 -166 -150 -133 Rev: 1.03 11/2004 –40 to 85°C (x32/ x36) Flow Through Pipeline (x18) Flow Through Pipeline — Flow Through ISB IDD IDD Pipeline — Flow Through ISB IDD IDDQ IDD IDDQ IDD IDDQ Pipeline IDD IDDQ Parameter Test Conditions Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open 16/24 Standby Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. GS880E18/32/36AT-250/225/200/166/150/133 © 2001, GSI Technology GS880E18/32/36AT-250/225/200/166/150/133 AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Flow Through Clock to Output Invalid Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ tS tH tKC tKQ tKQX tLZ1 tS tH tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tZZS2 tZZH2 tZZR 1 -250 Min 4.0 — 1.5 1.5 1.2 0.2 5.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 2.5 — — — — — 5.5 — — — — — — 2.3 2.3 — 2.3 — — — -225 Min 4.4 — 1.5 1.5 1.3 0.3 6.0 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 2.7 — — — — — 6.0 — — — — — — 2.5 2.5 — 2.5 — — — -200 Min 5.0 — 1.5 1.5 1.4 0.4 6.5 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 3.0 — — — — — 6.5 — — — — — — 3.0 3.2 — 3.0 — — — -166 Min 6.0 — 1.5 1.5 1.5 0.5 7.0 — 3.0 3.0 1.5 0.5 1.3 1.5 1.5 — 0 — 5 1 20 Max — 3.4 — — — — — 7.0 — — — — — — 3.0 3.5 — 3.0 — — — -150 Min 6.7 — 1.5 1.5 1.5 0.5 7.5 — 3.0 3.0 1.5 0.5 1.5 1.7 1.5 — 0 — 5 1 20 Max — 3.8 — — — — — 7.5 — — — — — — 3.0 3.8 — 3.0 — — — -133 Min 7.5 — 1.5 1.5 1.5 0.5 8.5 — 3.0 3.0 1.5 0.5 1.7 2 1.5 — 0 — 5 1 20 Max — 4.0 — — — — — 8.5 — — — — — — 3.0 4.0 — 3.0 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.03 11/2004 17/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Pipeline Mode Timing Begin Read A Cont Deselect Deselect Write B tKL tKH tKC Read C Read C+1 Read C+2 Read C+3 Cont Deselect Deselect CK ADSP tS tH ADSC tS ADV tS tH Ao–An A B C ADSC initiated read tH tS GW tS BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tS tOE DQa–DQd Hi-Z E2 and E3 only sampled with ADSC Deselected with E1 tH tKQ tH tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) tHZ tKQX tOHZ Q(A) D(B) Rev: 1.03 11/2004 18/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Flow Through Mode Timing Begin Read A Cont tKL tKH Deselect Write B tKC Read C Read C+1 Read C+2 Read C+3 Read C Deselect CK ADSP tS tH ADSC tH tS ADV tS tH Ao–An A B C Fixed High tS tH ADSC initiated read tS tH tS tH GW tS tH BW tH tS Ba–Bd tS tH E1 tS tH E2 tS tH E3 G tOE tKQ DQa–DQd Q(A) E1 masks ADSP Deselected with E1 E2 and E3 only sampled with ADSP and ADSC E1 masks ADSP tH tS tOHZ D(B) tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C) tKQX tHZ Rev: 1.03 11/2004 19/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. Sleep Mode Timing Diagram tKH tKC CK Setup Hold ADSP ADSC tZZR tZZS ZZ tZZH tKL Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention. Rev: 1.03 11/2004 20/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 TQFP Package Drawing (Package T) L Symbol A1 A2 b c D D1 E E1 e L L1 Y θ θ c Pin 1 Description Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle Min. Nom. Max 0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 — 0.45 — 0.10 1.40 0.30 — 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 — 0.75 — 0.10 L1 e b D D1 A1 Y A2 E1 E 0° — 7° Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.03 11/2004 21/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs Org 512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 256K x 32 256K x 32 256K x 32 256K x 32 256K x 32 256K x 32 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 256K x 32 256K x 32 256K x 32 256K x 32 Part Number1 GS880E18AT-250 GS880E18AT-225 GS880E18AT-200 GS880E18AT-166 GS880E18AT-150 GS880E18AT-133 GS880E32AT-250 GS880E32AT-225 GS880E32AT-200 GS880E32AT-166 GS880E32AT-150 GS880E32AT-133 GS880E36AT-250 GS880E36AT-225 GS880E36AT-200 GS880E36AT-166 GS880E36AT-150 GS880E36AT-133 GS880E18AT-250I GS880E18AT-225I GS880E18AT-200I GS880E18AT-166I GS880E18AT-150I GS880E18AT-133I GS880E32AT-250I GS880E32AT-225I GS880E32AT-200I GS880E32AT-166I Type DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP Speed2 (MHz/ns) 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 133/8.5 250/5.5 225/6 200/6.5 166/7 TA3 C C C C C C C C C C C C C C C C C C I I I I I I I I I I Status 256K x 32 GS880E32AT-150I DCD Pipeline/Flow Through TQFP 150/7.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03 11/2004 22/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 Ordering Information for GSI Synchronous Burst RAMs Org 256K x 32 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 Part Number1 GS880E32AT-133I GS880E36AT-250I GS880E36AT-225I GS880E36AT-200I GS880E36AT-166I GS880E36AT-150I Type DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through DCD Pipeline/Flow Through Package TQFP TQFP TQFP TQFP TQFP TQFP Speed2 (MHz/ns) 133/8.5 250/5.5 225/6 200/6.5 166/7 150/7.5 TA3 I I I I I I Status 256K x 36 GS880E36AT-133I DCD Pipeline/Flow Through TQFP 133/8.5 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880E18AT-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.03 11/2004 23/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS880E18/32/36AT-250/225/200/166/150/133 9Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 880E18A_r1 Types of Changes Format or Content Page;Revisions;Reason • Creation of new datasheet • Updated FT power numbers • Updated AC Characteristics table • Updated ZZ recovery time diagram • Changed 8Mb references to 9Mb • Updated AC Test Conditions table and removed Output Load 2 diagram • Removed Preliminary banner • Removed pin locations from pin description table • Updated format • Updated timing diagrams • Updated mechanical drawings 880E18A_r1; 880E18A_r1_01 Content 880E18A_r1_01; 880E18A_r1_02 880E18A_r1_02; 880E18A_r1_03 Content Format/Content Rev: 1.03 11/2004 24/24 © 2001, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.