IMAGE SENSOR
InGaAs linear image sensor
G9201 to G9204 series
Image sensor for DWDM wavelength monitor
G9201 to G9204 series InGaAs linear image sensors are specifically designed as detectors for monitoring WDM in optical communications. These linear image sensors consist of an InGaAs photodiode array with each pixel connected to a charge amplifier array comprised of CMOS transistors, a CDS circuit, an offset compensation circuit, a shift register and a timing generator. These sensors deliver high sensitivity and stable operation in the near infrared spectral range. The package is hermetically sealed for high reliability and the window has an anti-reflective coating for efficient light detection. Signal processing circuits on the CMOS chip allow selecting a feedback capacitance (Cf) of 10 pF or 0.5 pF by supplying an external voltage. The image sensor operates over a wide dynamic range when Cf=10 pF and delivers high gain when Cf=0.5 pF.
Features
Applications
l Wide dynamic range l Low noise and low dark current l Selectable gain l Anti-saturation circuit l CDS circuit *1 l Offset compensation circuit l Simple operation (by built-in timing generator) *2 l High resolution: 25 µm pitch (512 ch) l Low cross-talk l 256 ch: 1 video line
512 ch: 2 video lines
l DWDM wavelength monitor l Optical spectrum analyzer
Accessories (Optional)
l InGaAs multichannel detector head C8061-01 *3 l Multichannel detector head controller C7557 *3
s Selection guide
Type No. G 9 2 0 1-25 6 S G 9 2 0 2-51 2 S G 9 2 0 3-25 6 D * 4 G 9 2 0 3-25 6 S G 9 2 0 4-51 2 D * 4 G 9 2 0 4-51 2 S Cooling One-stage TE-cooled One-stage TE-cooled Non-cooled One-stage TE-cooled Non-cooled One-stage TE-cooled Number of pixels 256 512 256 512 Pixel pitch (µm) 50 25 50 25 Pixel size [µm (H) × µm (V)] 50 × 250 25 × 250 50 × 500 25 × 500 Spectral response range (µm) 0.9 to 1.67 (-10 °C) 0.9 to 1.67 (-10 °C) 0.9 to 1.7 (25 °C) 0.9 to 1.67 (-10 °C) 0.9 to 1.7 (25 °C) 0.9 to 1.67 (-10 °C) Defective pixel
0
*1: CDS (Correlated Double Sampling) circuit A major source of noise in charge amplifiers is the reset noise generated when the integration capacitance is reset. A CDS circuit greatly reduces this reset noise by holding the signal immediately after reset to find the noise differential. *2: Timing generator Different signal timings must be properly set in order to operate a shift register. In conventional image sensor operation, external PLDs (Programmable Logic Devices) are used to input the required timing signals. However, G9201 to G9204 series image sensors internally generate all timing signals on the CMOS chip just by supplying CLK and RESET pulses. This makes it simple to set the timings. *3: G9203-256D and G9204-512D are not available for C7557. *4: For G9203-256D and G9204-512D specifications, see the separate data sheets available from Hamamatsu.
s Spectral response
1.0 T=25 ˚C T= -10 ˚C
(Typ.)
PHOTO SENSITIVITY (A/W)
0.5
0 0.5
1.0
1.5
2.0
WAVELENGTH (µm)
KMIRB0011EA
1
InGaAs linear image sensor
s Absolute maximum ratings
Parameter Clock pulse voltage Operating temperature *5 Storage temperature *5 *5: Non condensation Symbol Vφ Topr Tstg
G9201 to G9204 series
Value 5.5 -40 to +70 -40 to +85 Unit V °C °C
s Electrical characteristics (Ta=25 °C, Vφ=5 V )
Parameter Supply voltage Supply current Ground Element bias Element bias current Clock frequency Clock pulse voltage Clock pulse rise/fall times Clock pulse width Reset pulse voltage Reset pulse rise/fall times Reset pulse width Video output voltage Data rate high low high low high low Symbol Vdd Vref 256 ch I (Vdd) 512 ch I (Vref) Vss INP I (INP) f Vφ tr φ tf φ tpw φ V (RES) tr (RES) tf (RES) tpw (RES) VH VL fV Min. 4.9 3.5 0.1 Vφ - 0.5 0 0 200 Vφ - 0.5 0 0 6000 0 Typ. 5.0 1.26 45 90 1 Max. 0 4.5 1 Max. Vφ 0 20 Vφ 0 20 4.5 1.26 f/8 Max. 5.1 50 100 4.6 4 Vφ + 0.5 0.4 100 Vφ + 0.5 0.4 100 Unit V mA mA V V mA MHz V V ns ns V V ns ns V Hz
s Electrical and optical characteristics General ratings (T=25 °C)
Parameter Peak sensitivity wavelength Saturation charge *6 RMS noise voltage (readout noise) Photo response non-uniformity *7 Symbol λp Qsat N PRNU Condition Vp=5 V Standard deviation Number of integration: 50 Integration time: 10 msec Min. Typ. 1.55 30 180 Max. 300 ±5 Unit µm pC µVrms % V
Saturation voltage Vsat 3.0 3.2 *6: Vφ=5 V, Cf=10 pF *7: 50 % of saturation, 10 ms integration time, after dark output subtraction, excluding first and last pixels.
Dark current characteristics (T=25 °C)
Parameter G9201 series G9202 series G9203 series G9204 series Symbol ID Min. Typ. 2 1 4 1 Max. 10 5 20 5 Unit pA
2
InGaAs linear image sensor
s Equivalent circuit
q 1 PIXEL (
G9201 to G9204 series
)
Cf=10 pF Cf=0.5 pF SHIFT REGISTER
CDS PHOTODIODE
OFFSET COMPENSATION
VIDEO
AD-TRIG TIMING GENERATOR
Vdd
INP Vss
CLK
RESET
Vref
EXTERNAL INPUT
KMIRC0010EB
s Timing chart
CLK (INPUT)
RESET (INPUT) INTEGRATION 2 CLOCKS TIME 8 CLOCKS 8 CLOCKS TRIGGER (OUTPUT) VIDEO (OUTPUT) 8 × N CLOCKS (READOUT TIME) 10 CLOCKS MIN.
1 ch
2 ch
(n-1) ch
n ch
s Basic circuit connection
CLK RESET Vref Vdd Cf SELECT INP Vss VIDEO AD-TRIG BUFFER BUFFER
KMIRC0016EB
KMIRC0012EA
3
InGaAs linear image sensor
s Dimensional outline (unit: mm)
63.5 ± 0.15 53.3 ± 0.15 38.1 ± 0.15 35.6 ± 0.15 28 15 27.2 ± 0.15
G9201 to G9204 series
25.4 ± 0.15
22.9 ± 0.15
10.2 ± 0.15
3.0 ± 0.15
12 INDEX MARK
14
20.3 ± 0.15
A
A
B
B
1.0 ± 0.2
6.4 ± 1
ONE-STAGE TE-COOLED 6.15 3.6
(28 ×) 2.54 (28 ×) 0.46
KMIRA0010EB
s Pin connection (top view)
256 PIXELS 512 PIXELS
TE +
Cf SELECT RESET TE AD-TRIG Vdd Vss INP CLK Vref VIDEO
RESET-EVEN TE + AD-TRIG-EVEN THERM THERM CASE CLK-EVEN
Cf SELECT RESET-ODD TE AD-TRIG-ODD Vdd Vss INP CLK-ODD
THERM THERM CASE
Vref VIDEO-EVEN VIDEO-ODD
KMIRC0013EA
Terminal name CLK RESET Vdd Vss INP Cf SELECT CASE THERM TE+, TEAD-TRIG VIDEO Vref
Input/Output Function and recommended connection Input Clock pulse for operating the CMOS shift register (CMOS logic compatible) Input Reset pulse for initializing the feedback capacitance in the charge amplifier (CMOS logic compatible) formed on the CMOS chip. The width of the reset pulse is integration time. Input
-
Supply voltage for operating the signal processing circuit on the CMOS chip. Ground for the signal processing circuit on the CMOS chip. Reset voltage for the charge amplifier array on the CMOS chip. Voltage that determines the feedback capacitance (Cf) on the CMOS chip. Cf=10 pF at 0 V, and Cf=0.5 pF at 5 V. This terminal is electrically connected to the package. Thermistor for monitoring temperature inside the package. No connection for room temperature operation type. Power supply terminal for the thermoelectric cooler that cools the photodiode array. Digital signal for AD conversion; positive polarity Analog video signal; positive polarity Reset voltage for the offset compensation circuit on the CMOS chip
Input Input
-
Output Output Input
Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2006 Hamamatsu Photonics K.K.
HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
4
Cat. No. KMIR1012E05 May 2006 DN
