S3921-256Q

IMAGE SENSOR NMOS linear image sensor S3921/S3924 series Voltage output type with current-integration readout circuit and impedance conversion circuit NMOS linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. The scanning circuit is made up of N-channel MOS transistors, operates at low power consumption and is easy to handle. Each photodiode has a large active area, high UV sensitivity yet very low noise, delivering a high S/N even at low light levels. NMOS linear image sensors also offer excellent output linearity and wide dynamic range. S3921/S3924 series have a current-integration readout circuit utilizing the video line and an impedance conversion circuit. The output is available in boxcar waveform allowing signal readout with a simple external circuit. The photodiodes of S3921 series have a height of 2.5 mm and are arrayed in a row at a spacing of 50 µm. The photodiodes of S3924 series also have a height of 2.5 mm but are arrayed at a spacing of 25 µm. The photodiodes are available in 3 different pixel quantities for each series, 128 (S3921-128Q), 256 (S3921-256Q, S3924-256Q) and 512 (S3921-512Q, S3924-512Q) and 1024 (S3924-1024Q). Quartz glass is the standard window material. Features Applications l Built-in current-integration readout circuit utilizing l Multichannel spectrophotometry video line capacitance and impedance conversion l Image readout system circuit (boxcar waveform output) l Wide active area Pixel pitch: 50 µm (S3921 series) 25 µm (S3924 series) Pixel height: 2.5 mm l High UV sensitivity with good stability l Low dark current and high saturation charge allow a long integration time and a wide dynamic range at room temperature l Excellent output linearity and sensitivity spatial uniformity l Low voltage, single power supply operation l Start pulse, clock pulse and video line reset pulse are CMOS logic compatible Figure 1 Equivalent circuit START CLOCK CLOCK st 1 2 DIGITAL SHIFT REGISTER (MOS SHIFT REGISTER) END OF SCAN SOURCE FOLLOWER CIRCUIT Vdd ACTIVE VIDEO Figure 2 Active area structure 2.5 mm b a OXIDATION SILICON ADDRESS SWITCH ACTIVE PHOTODIODE SATURATION CONTROL GATE SATURATION CONTROL DRAIN ADDRESS SWITCH DUMMY DIODE RESET SWITCH Vss DUMMY VIDEO 1.0 µm 1.0 µm 400 µm RESET RESET V N TYPE SILICON KMPDC0019EA P TYPE SILICON s Absolute maximum ratings S3921 SERIES: a=50 µm, b=45 µm S3924 SERIES: a=25 µm, b=20 µm KMPDA0067EA Parameter Supply voltage Input pulse (φ1, φ2, φst) voltage Power consumption * 1 Operating temperature * 2 Storage temperature *1: Vdd=5 V, Vr=2.5 V *2: No condensation Symbol Vdd Vφ P Topr Tstg Value 15 15 10 -40 to +65 -40 to +85 Unit V V mW °C °C NMOS linear image sensor s Shape specifications Parameter Number of pixels Package length Number of pin Window material *3 Weight *3: Fiber optic plate is available. S3921/S3924 series S3924S3924256Q 512Q 256 512 31.75 22 Quartz 3.0 S39241024Q 1024 40.6 3.5 Unit mm g S3921S3921128Q 256Q 128 256 31.75 22 Quartz 3.0 S3921512Q 512 40.6 3.5 s S pecifications (Ta=25 °C) Parameter Pixel pitch Pixel height Spectral response range (10 % of peak) Peak sensitivity wavelength Photodiode dark current *4 Photodiode capacitance *4 Saturation exposure *4, *5 Saturation charge *4 Saturation output voltage *4 Symbol λ λp ID Cph Esat Qsat Vsat Min. - PRNU Photo response non-uniformity *6 *4: Reset V=2.5 V, Vdd=5.0 V, Vφ=5.0 V *5: 2856 K, tungsten lamp *6: 50 % of saturation, excluding the start pixel and last pixel S3921 series Typ. 50 2.5 200 to 1000 600 0.2 20 220 50 1350 (-128Q) 1300 (-256Q) 1100 (-512Q) - Max. 0.6 ±3 Min. - S3924 series Typ. 25 2.5 200 to 1000 600 0.1 10 220 25 1050 (-256Q) 820 (-512Q) 570 (-1024Q) - Max. 0.3 ±3 Unit µm mm nm nm pA pF m lx · s pC mV mV mV % s Electrical characteristics (Ta=25 °C) Parameter Clock pulse (φ1, φ2) voltage Symbol Condition 50 % of saturation* 5 V bias 5 V bias 5 V bias Vdd=5 V Vr=2.5 V High Vφ1, Vφ2 (H) Low Vφ1, Vφ2 (L) Vφs (H) High Start pulse (φst) voltage *7 Vφs (L) Low Vrφ (H) High Reset pulse (Reset φ) Vrφ (L) voltage *7 Low Vdd Source follower circuit drain voltage *% Vr Reset voltage (Reset V) *8 Vscg Saturation control gate voltage 8 Vscd Saturation control drain voltage * tr φ 1, tr φ 2 Clock pulse (φ1, φ2) rise / fall time tf φ 1, tf φ 2 Clock pulse (φ1, φ2) pulse width tpw φ 1, tpw φ 2 Start pulse (φst) rise / fall time tr φ s, tf φ s Start pulse (φst) pulse width tpw φ s Reset pulse rise / fall time trr φ , tfr φ Start pulse (φst) and clock pulse t φ ov (φ2) overlap Clock pulse (φ2) and reset t φ ovr pulse (Reset φ) overlap Clock pulse (φ2) and reset td φ r-2 pulse (Reset φ) delay time Clock pulse (φ1, φ2) space *9 X1, X 2 Clock pulse (φ2, Reset φ) space *9 ts φ r-2 f Data rate *10 Video delay time Clock pulse (φ1, φ2) line capacitance Reset pulse (Reset φ) line capacitance Saturation control gate (Vscg) line capacitance Output impedance tvd Cφ Cr Cscg Zo Min. 4.5 0 4.5 0 4.5 0 4.5 2.0 200 200 200 660 50 S3921 series Typ. Max. 5 10 0.4 Vφ 10 0.4 Vφ 10 0.4 10 Vφ Vφ - 2.5 Vφ - 2.0 0 Vr 20 20 20 500 - Min. 4.5 0 4.5 0 4.5 0 4.5 2.0 200 200 200 660 50 S3924 series Typ. Max. 5 10 0.4 Vφ 10 0.4 Vφ 10 0.4 10 Vφ Vφ - 2.5 Vφ - 2.0 0 Vr 20 20 20 100 (-256 Q) 150 (-512 Q) 200 (-1024 Q) 27 (-256 Q) 50 (-512 Q) 100 (-1024 Q) 6 14 (-256 Q) 24 (-512 Q) 45 (-1024 Q) 200 500 - Unit V V V V V V V V V V ns ns ns ns ns ns ns ns ns ns kHz ns ns ns pF pF pF pF pF pF pF Ω trf - 20 0 0.1 100 (-128 Q) 150 (-256 Q) 200 (-512 Q) 21 (-128 Q) 36 (-256 Q) 67 (-512 Q) 6 12 (-128 Q) 20 (-256 Q) 35 (-512 Q) 200 trf - 20 0 0.1 - *7: Vφ is input pulse voltage (refer to figure 8) *8: Terminal pin 7 is used for both Reset V and saturation control drain voltage *9: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be input if the clock pulse rise or fall time is longer than 20 ns. (refer to figure 7) *10: Reset V=2.5 V, Vdd=5.0 V, Vφ=5.0 V NMOS linear image sensor Figure 3 Dimensional outlines (unit: mm) S3921-128Q, S3924-256Q 5.4 ± 0.2 S3921/S3924 series S3921-256Q, S3924-512Q 3.2 ± 0.3 6.4 ± 0.3 10.4 5.4 ± 0.2 5.0 ± 0.2 10.4 ACTIVE AREA 6.4 × 2.5 ACTIVE AREA 12.8 × 2.5 5.0 ± 0.2 31.75 PHOTOSENSITIVE SURFACE 1.3 ± 0.2* 31.75 PHOTOSENSITIVE SURFACE 1.3 ± 0.2* 3.0 0.51 2.54 25.4 10.16 0.25 0.51 2.54 25.4 * Optical distance from the outer surface of the quartz window to the chip surface 3.0 0.25 10.16 * Optical distance from the outer surface of the quartz window to the chip surface KMPDA0060EA KMPDA0061EA S3921-512Q, S3924-1024Q 5.4 ± 0.2 Figure 4 Pin connection ACTIVE AREA 25.6 × 2.5 12.8 ± 0.3 2 1 st 10.4 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 NC NC NC NC NC NC NC NC NC END OF SCAN Vdd Vss Vscg PHOTOSENSITIVE SURFACE 1.3 ± 0.2 * 40.6 5.0 ± 0.2 RESET RESET V (Vscd) Vss ACTIVE VIDEO DUMMY VIDEO Vsub 0.51 2.54 25.4 10.16 3.0 0.25 Vss, Vsub and NC should be grounded. KMPDC0025EA * Optical distance from the outer surface of the quartz window to the chip surface KMPDA0062EA NMOS linear image sensor Terminal φ1, φ2 φst Vss Vscg Reset φ Input or output Input (CMOS logic compatible) Input (CMOS logic compatible) Input Input (CMOS logic compatible) Input S3921/S3924 series Description Pulses for operating the MOS shift register. The video data rate is equal to the clock pulse frequency since the video output signal is obtained synchronously with the rise of φ2 pulse. Pulse for starting the MOS shift register operation. The time interval between start pulses is equal to the signal accumulation time. Connected to the anode of each photodiode. This should be grounded. Used for restricting blooming. This should be grounded. With Reset φ at high level, the video line is reset at the Reset V voltage. The Reset V terminal connects to each photodiode cathode via the video line when the address turns on. A positive voltage should be applied to the Reset V terminal to use each photodiode at a reverse bias. Setting the Reset V voltage to 2.5 V is recommended when the amplitude of φ1, φ2 and Reset φ is 5 V. Terminal pin 7 is used for both Reset V and Vscd. Used for restricting blooming. This should be biased at a voltage equal to “Reset V”. Low-impedance video output signal after internal current-voltage conversion. Negative-going output including DC offset. This has the same structure as the active video, but is not connected to photodiodes, so only DC offset is output. Leave this terminal open when not used. Connected to the silicon substrate. This should be grounded. Supply voltage to the internal impedance conversion circuit. A voltage equal to the amplitude of each clock should be applied to this terminal. This should be pulled up at 5 V by using a 10 kΩ resistor. This is a negative going pulse that appears synchronously with the φ2 timing right after the last photodiode is addressed. Should be grounded. Reset V Vscd Active video Dummy video Vsub Vdd End of scan NC Input Output Output Input Output (CMOS logic compatible) - Figure 5 Spectral response (typical example) Figure 6 Output voltage vs. exposure 0.3 (Ta=25 ˚C) 101 (Typ. Reset V=2.5 V, Vdd=5.0 V, V =5 V, light source: 2856 K) 101 (Typ. Reset V=2.5 V, Vdd=5.0 V, V =5 V, light source: 2856 K) PHOTO SENSITIVITY (A/W) 10 0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) SATURATION VOLTAGE 10 0 0.2 SATURATION VOLTAGE 10-1 S3924-256Q 10-2 S3924-512Q S3924-1024Q 10 -3 10-1 S3921-128Q S3921-256Q S3921-512Q 10 -3 10 -2 0.1 SATURATION EXPOSURE SATURATION EXPOSURE 0 200 400 600 800 1000 1200 10 -4 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 -4 10-5 10-4 10-3 10-2 10-1 100 WAVELENGTH (nm) KMPDB0149EA EXPOSURE (lx · s) KMPDB0118EA EXPOSURE (lx · s) KMPDB0119EA s Construction of image sensor The NMOS image sensor consists of a scanning circuit made up of MOS transistors, a photodiode array, and a switching transistor array that addresses each photodiode, all integrated onto a monolithic silicon chip. Figure 1 shows the circuit of a NMOS linear image sensor. The MOS scanning circuit operates at low power consumption and generates a scanning pulse train by using a start pulse and 2-phase clock pulses in order to turn on each address sequentially. Each address switch is comprised of an NMOS transistor using the photodiode as the source, the video line as the drain and the scanning pulse input section as the gate. The photodiode array operates in charge integration mode so that the output is proportional to the amount of light exposure (light intensity × integration time). Each cell consists of an active photodiode and a dummy diode, which are respectively connected to the active video line and the dummy video line via a switching transistor. Each of the active photodiodes is also connected to the saturation control drain via the saturation control gate, so that the photodiode blooming can be suppressed by grounding the saturation control gate. Applying a pulse signal to the saturation control gate triggers all reset. (See “Auxiliary functions”.) NMOS linear image sensor Figure 2 shows the schematic diagram of the photodiode active area. This active area has a PN junction consisting of an N-type diffusion layer formed on a P-type silicon substrate. A signal charge generated by light input accumulates as a capacitive charge in this PN junction. The N-type diffusion layer provides high UV sensitivity but low dark current. S3921/S3924 series s Driver circuit A start pulse φst and 2-phase clock pulses φ1, φ2 are needed to drive the shift register. These start and clock pulses are positive going pulses and CMOS logic compatible. The 2-phase clock pulses φ1, φ2 can be either completely separated or complementary. However, both pulses must not be “High” at the same time. A clock pulse space (X1 and X2 in Figure 7) of a “rise time/fall time - 20” ns or more should be input if the rise and fall times of φ1, φ2 are longer than 20 ns. The φ1 and φ2 clock pulses must be held at “High” at least 200 ns. Since the photodiode signal is obtained at the rise of each φ2 pulse, the clock pulse frequency will equal the video data rate. The amplitude of start pulse φst is the same as the φ1 and φ2 pulses. The shift register starts the scanning at the “High” level of φst, so the start pulse interval is equal to signal accumulation time. The φst pulse must be held “High” at least 200 ns and overlap with φ2 at least for 200 ns. To operate the shift register correctly, φ2 must change from the “High” level to the “Low” level only once during “High” level of φst. The timing chart for each pulse is shown in Figure 7. s End of scan The end of scan (EOS) signal appears in synchronization with the φ2 timing right after the last photodiode is addressed, and the EOS terminal should be pulled up at 5 V using a 10 kΩ resistor. Figure 7 Timing chart for driver circuit st 1 2 V s (H) V s (L) V V V V 1 (H) 1 (L) 2 (H) 2 (L) tpw s tpw 1 tpw 2 Figure 8 Reset V voltage margin 12 10 RESET V VOLTAGE (V) RESET Vr (H) Vr (L) tvd 8 ACTIVE VIDEO OUTPUT END OF SCAN 6 RE CO E MM ND R ED ES ET O VV MA LT AG E X. tr s st tf s 4 RESET V VOLTAGE RANGE tr 1 tf 1 2 MIN. 1 X1 2 t ov RESET ts r-2 X2 tf 2 0 4 5 6 7 8 9 10 t ovr td r-2 CLOCK PULSE AMPLITUDE (V) KMPDB0047EA tfr trr KMPDC0026EA s Signal readout circuit S3921/S3924 series include a current integration circuit utilizing the video line capacitance and an impedance conversion circuit. This allows signal readout with a simple external circuit. However, a positive bias must be applied to the video line because the photodiode anode of NMOS linear image sensors is at 0 V (Vss). This is done by adding an appropriate pulse to the reset φ terminal. The amplitude of the reset pulse should be equal to φ1, φ2 and φst. When the reset pulse is at the high level, the video line is set at the Reset V voltage. Figure 8 shows the Reset V voltage margin. A higher clock pulse amplitude allows higher Reset V voltage and saturation charge. Conversely, if the Reset V voltage is set at a low level with a higher clock pulse amplitude, the rise and fall times of video output waveform can be shortened. Setting the Reset V voltage to 2.5 V is recommended when the amplitude of φ1, φ2, φst and Reset φ is 5 V. To obtain a stable output, an overlap between the reset pulse (Reset φ) and φ2 must be settled. (Reset φ must rise while φ2 is at the high level.) Furthermore, Reset φ must fall while φ2 is at the low level. S3921/S3924 series provide output signals with negativegoing boxcar waveform which include a DC offset of approximately 1 V when Reset V is 2.5 V. If you want to remove the DC offset to obtain the positive-going output, the signal readout circuit and pulse timing shown in Figure 9 are recommended. In this circuit, Rs must be larger than 10 kΩ. Also, the gain is determined by the ratio of Rf to Rs, so choose the Rf value that suits your application. NMOS linear image sensor S3921/S3924 series Feature Low price Single power supply (+15 V) operation Boxcar waveform output BNC, length 1 m Hamamatsu provides the following driver circuits and related products (sold separately). Product name Driver circuit Pulse generator Cable +5 V +5 V + 10 kΩ st 1 2 Reset +2.5 V st 1 2 Reset Reset V (Vscd) Vscg Vss Vsub NC KMPDC0028EA Type No. C7885 C7885G C8225-02 A8226 Content Low cost driver circuit C7885 + C8225-02 C7885 series C7883 to C7885 series Figure 9 Readout circuit example and timing chart Vdd EOS OPEN Rs 10 kΩ EOS Rf st 1 DUMMY VIDEO ACTIVE VIDEO – + + 2 Reset +15 V KMPDC0027EA s Anti-blooming function If the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the saturation charge cannot accumulate in the photodiode. This excessive charge flows out into the video line degrading the signal purity. To avoid this problem and maintain the signal purity, applying the same voltage as the Reset V voltage to the saturation control drain and grounding the saturation control gate are effective. If the incident light intensity is extremely high, a positive bias should be applied to the saturation control gate. The larger the voltage applied to the saturation control gate, the higher the function for suppressing the excessive saturation charge will be. However, this voltage also lowers the amount of saturation charge, so an optimum bias voltage should be selected. s Auxiliary functions 1) All reset In normal operation, the accumulated charge in each photodiode is reset when the signal is read out. Besides this method that uses the readout line, S3921/S3924 series can reset the photodiode charge by applying a pulse to the saturation control gate. The amplitude of this pulse should be equal to the φ1, φ2, φst, Reset φ pulses and the pulse width should be longer than 5 µs. When the saturation control gate is set at the “High” level, all photodiodes are reset to the saturation control drain potential. Conversely, when the saturation control gate is set at the “Low” level (0 V), the signal charge accumulates in each photodiode without being reset. 2) Dummy video S3921/S3924 series have a dummy video line. Positive-polarity video signals with the DC offset remove can be obtained by differential amplification of the active video line and dummy video line outputs. When not needed, leave this unconnected. s Precautions for using NMOS linear image sensors 1) Electrostatic countermeasures NMOS linear image sensors are designed to resist static electrical charges. However, take sufficient cautions and countermeasures to prevent damage from static charges when handling the sensors. 2) Window If dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. Before using the image sensor, the window surface should be cleaned. Wipe off the window surface with a soft cloth, cleaning paper or cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. Do not rub the window with dry cloth or cotton swab as this may generate static electricity. Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218 Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Cat. No. KMPD1044E01 Oct. 2005 DN