2
Optically Isolated I C Bus Repeater
INTEGRATED CIRCUITS DIVISION
Features
•
•
•
•
•
•
•
•
•
•
•
Description
Bidirectionally Buffers Both I2C Signals
Glitch-Free Operation
Extends and Isolates I2C Interfaces
Standard- and Fast-mode I2C
Side B Fast-mode I2C Compliant VDDB > 4.5V
Very Low EM and RF Generation - No Internal Clock
SMBus Compatible VDDB = 3.3V
Operates on 2.7V to 5.5V, Enabling Level Translation
Slew-Limited Drivers Reduce EMI
Powerdown to Hi-Z Doesn't Load I2C
3750Vrms Galvanic Isolation
Flammability Rating UL 94 V-0
IXYS Integrated Circuits’ CPC5902 is a dual, optically
isolated, bidirectional logic-bus repeater. It galvanically
isolates two open-drain logic signals, and provides a
galvanic isolation of 3750Vrms. When the two sides’
supply voltages are configured with different voltages,
the CPC5902 also functions as a logic level translator
for levels as low as 2.7V or as high as 5.5V.
Unlike transformer or capacitive isolators, the optically
isolated repeaters pass DC signals, and do not need
to be clocked periodically to sustain the logic states.
Buffered signals will always return to their proper value
after a transient interruption on either side.
Applications
•
•
•
•
•
CPC5902
Ordering Information
Isolated Signal Monitoring and Control
Power-over-Ethernet
Power Supply High Side Interface
I2C Bus Length Extenders
I2C Logic Level Translation
Part
Description
CPC5902G
8-Pin DIP (50 / Tube)
CPC5902GS
8-Pin Surface Mount (50 / Tube)
CPC5902GSTR 8-Pin Surface Mount (1000 / Reel)
Approvals
• UL 1577 File E76270
• CSA Certified Component: Certificate 70157867
• EN/IEC 60950 Certified Component:
TUV Certificate available on our website
Figure 1. CPC5902 Functional Block Diagram
3750Vrms Optical Isolation
VDDA
IOA1
VDDB
1
A
VDDA
GNDA
VDDB
VDDB
B
D Q
CLR
VDDB
LED
2
A
LED
VDDB
8
7
IOB1
6
GNDB
B
A
VDDA
IOA2
3
A
VDDA
VDDA
4
VDDA
LED
VDDB
VDDB
B
B
D Q
CLR
VDDB
5
LED
IOB2
B
A
DS-CPC5902-R04
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1
CPC5902
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 IOA to IOB Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 IOB to IOA Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
3
3
4
4
5
6
6
2. Performance Data*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Calculating Minimum Pull-Up Resistor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
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12
12
12
12
13
R04
CPC5902
INTEGRATED CIRCUITS DIVISION
1 Specifications
1.1 Package Pinout
1.2 Pin Description
1
2
3
4
Pin#
Name
1
IOA1
GNDA
Bidirectional Input/Output 1 - Side A
IOA2
VDDA
Bidirectional Input/Output 2 - Side A
IOB2
GNDB
Bidirectional Input/Output 2 - Side B
IOB1
VDDB
Bidirectional Input/Output 1 - Side B
8
7
6
5
2
3
4
5
6
7
8
Description
Supply Return - Side A
Supply Voltage - Side A
Supply Return - Side B
Supply Voltage - Side B
1.3 Absolute Maximum Ratings
Electrical Absolute Maximum Ratings are at 25°C. Voltages with respect to local ground: GNDA or GNDB.
Parameter
Symbol
Min
Max
Units
Supply Voltage A
VDDA
-0.5
+6.5
V
Supply Voltage B
VDDB
-0.5
+6.5
V
Input Voltage
VIOx
-0.3
VDDx + 0.3
V
Power Dissipation 1
PTOT
-
800
mW
-
3750
-
4500
-
-40
+85
5
85
-50
+125
Isolation Voltage, Input to Output
60 Seconds
2 Seconds
Operating Temperature
Operating Relative Humidity
(Non-condensing)
Storage Temperature
1
TA
RH
TSTG
Vrms
°C
%
°C
Derate total power by 7.5mW/°C above 25°C.
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device.
Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not
implied.
1.4 ESD Rating
ESD Rating (Human Body Model)
4000V
1.5 Thermal Characteristics
Parameter
Thermal Impedance, Junction to Ambient
R04
Conditions
Symbol
Typical
Units
Free Air
RJA
114
°C/W
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3
CPC5902
INTEGRATED CIRCUITS DIVISION
1.6 General Conditions
Unless otherwise specified, minimum and maximum values are guaranteed by production testing requirements or by
design. Typical values are characteristic of the device at 25°C, and are the result of engineering evaluations. They are
provided for information purposes only, and are not part of the manufacturing testing requirements.
Specifications cover the operating temperature range TA = -40°C to +85°C.
1.7 Electrical Specifications
Parameter
Conditions
Symbol
Min
Typ
Max
Units
ISINK1=6mA, ISINK2=6mA
VDDA
2.7
-
5.5
V
-
7.5
-
-
7.85
-
-
8.1
10
-
0.01
10
Side A
Supply Voltage
Supply Current
VDDA=3.3V, ISINK=0
VDDA=3.3V, ISINK1=6mA, ISINK2=6mA
IDDA
VDDA=5.5V, ISINK=0, TA=25°C
Leakage Current
IOA1=IOA2=VDDA
Input Capacitance
ILEAKA
CIN
VDDA 2.7V to 5.5V
VILA
0.3VDDA
-
-
Rising Input High Threshold
VDDA 2.7V to 5.5V
VIHA
-
-
0.7VDDA
Hysteresis
VDDA=2.7V to 5.5V
HYSTA
-
0.15VDDA
-
-
0.21
0.35
-
0.42
0.7
VDDA=2.7V, ISINK=3mA
VDDA=2.7V, ISINK=6mA
Output Temperature Coefficient
VOLA
A
pF
3
Falling Input Low Threshold
Output Drive
mA
V
V
V
VDDA=2.7V to 5.5V, ISINK=6mA
TCA
-
+1.2
-
mV/°C
ISINK1=ISINK2=3mA
VDDB
2.7
-
5.5
V
-
12.1
-
-
12.25
-
-
12.7
16
-
0.01
10
Side B
Supply Voltage
Supply Current
VDDB=3.3V, ISINK=0
VDDB=3.3V, ISINK1=ISINK2=3mA
IDDB
VDDB=5.5V, ISINK=0, TA=25°C
Leakage Current
IOB1=IOB2=VDDB
Input Capacitance
Falling Input Low Threshold
CIN
VDDB = 2.7V
VDDB = 2.7V to 5.5V
Hysteresis
Output Drive
ILEAKB
VDDB=2.7V to 5.5V
0.54
0.6
VILB
0.2VDDB
- 60mV
0.2VDDB
0.2VDDB
+ 60mV
V
HYSTB
-
0.01VDDB
-
V
VDDB=2.7V, ISINK=3mA
0.63
0.72
0.81
VDDB=2.7V, ISINK=0.1mA
-
0.62
-
0.23VDDB
0.23VDDB
+ 190mV
-
-
0.3VDDB
VDDB = 2.7V to 5.5V, ISINK=3mA
VOLB
-
VDDB 4.5V, ISINK=6mA
Self-Drive Margin
Output Temperature Coefficient
4
A
pF
3
0.48
mA
V
VDD=2.7V, ISINK=0.1mA (Self_Out-In) VDIFFERENCE
VOLB - VILB
25
-
-
mV
VDDB=2.7V to 5.5V, ISINK=3mA
TCB
-
+0.4
-
mV/°C
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R04
CPC5902
INTEGRATED CIRCUITS DIVISION
1.8 Switching
Specifications
Parameter
I2C Clock Frequency
Conditions
ISINKA=6mA,
CLOADA=400pF
Symbol
Min
Typ
Max
Units
fMAX
500
-
-
kHz
tPHL_AB
-
60
135
ns
tPLH_AB
-
122
270
tPHL_BA
-
90
170
tPLH_BA
-
165
275
tPLH_BAB
-
290
480
ISINKB=3mA, CLOADB=200pF
ISINKB=6mA, CLOADB=400pF
(VDDB 4.5V)
Propagation Delay A to B 1
Falling
Rising
Propagation Delay B to A 2
Falling
Rising
VDDA=VDDB=3.3V,
RPUA=475,
RPUB=825,
CIOA=CIOB=20pF
Propagation Delay B to A to B 2
Rising
0.5VDDA to 0.5VDDB
0.2VDDB to 0.5VDDA
0.2VDDB to 0.5VDDB
ns
ns
1 Refer to “IOA to IOB Switching Waveforms” on page 6
2 Refer to “IOB to IOA Switching Waveforms” on page 6
R04
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5
CPC5902
INTEGRATED CIRCUITS DIVISION
1.9 IOA to IOB Switching Waveforms
4V
IOA In
VDDA=3.3V
tPHL_AB
3V
2V
0.5 • VDDA = 1.65V
1V
0V
0ns
4V
500ns
1000ns
IOB Out
VDDB=3.3V
3V
tPLH_AB
2V
0.5 • VDDB = 1.65V
1V
0V
0ns
500ns
1000ns
1.10 IOB to IOA Switching Waveforms
4V
IOB In
VDDB=3.3V
3V
tPLH_BAB
2V
tPHL_BA
0.5 • VDDB = 1.65V
1V
tPLH_BA
0V
0ns
4V
500ns
0.2 • VDDB = 0.66V
1000ns
IOA Out
VDDA=3.3V
3V
2V
0.5 • VDDA = 1.65V
1V
0V
0ns
6
500ns
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1000ns
R04
CPC5902
INTEGRATED CIRCUITS DIVISION
2 Performance Data*
1.8
1.6
VOLB _6mA
1.4
1.2
1.2
1.0
VOLB _3mA
0.8
VOLB _0.1mA
0.6
0.6
0.4
0.2
3.5
4.0
4.5
VDD (V)
5.0
5.5
2.5
6.0
Noise Margin - Side B
VIL_external = 0.3VDD
450
300
250
200
150
100
3.5
4.0
4.5
VDD (V)
5.0
5.5
100
0
2.5
Output Voltage (VOLA) - Side A
vs. Temperature
(ISINKA=6mA)
0.35
0.30
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
Output Voltage vs. Temperature
Side B
(VDDB=4.5V, ISINKB=6mA)
1.40
Supply Current (mA)
VOLB
1.20
1.15
0
20
40
60
Temperature (ºC)
80
40
60
Temperature (ºC)
80
100
12
11
10
9
IDDA
8
7
Propagation Delay (ns)
120
100
80
tPHL_AB
60
40
-60
-40
-20
0
20
40
60
Temperature (ºC)
80
100
0
20
40
60
Temperature (ºC)
80
100
Supply Current vs. Temperature
(VDDA=VDDB=5.5V)
13
12
IDDB
11
10
9
8
IDDA
6
190
tPLH_AB
-20
7
2.5
Propagation Delay A to B
(VCC=3.3V, CL=20pF)
(RPUA=475Ω, RPUB=825Ω)
140
0.80
14
IDDB
170
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
Propagation Delay B to A
(VCC=3.3V, CL=20pF)
(RPUA=475Ω, RPUB=825Ω)
340
tPLH_BA
150
130
110
tPHL_BA
90
70
-60
-50
6.0
Propagation Delay (ns)
20
VOLB
-40
5
0
6.0
0.85
100
6
1.10
5.5
0.70
-20
13
1.30
1.25
0.90
14
1.35
5.0
0.3VDDB
Supply Current vs. Supply Voltage
0.3VDDB
4.0
4.5
VDD (V)
0.75
0.25
-40
6.0
3.5
0.95
Supply Current (mA)
2.5
3.0
1.00
0.40
0
ISINKB=100μA
Output Voltage (VOLB) - Side B
vs. Temperature
(VDDB=3.3V, ISINKB=3mA)
1.05
VDDA=2.7V
VDDA=3.3V
VDDA=5.5V
0.45
50
ISINKB=3mA
150
6.0
0.50
Side A Output (V)
350
3.0
0.55
ISINKB=0.1mA
ISINKB=3mA
ISINKB=6mA
400
Side B Output (V)
200
50
Side B Output (V)
3.0
ISINKB=6mA
250
0.0
2.5
Margin (mV)
0.8
0.2
Self Drive Margin - Side B
(VOLB - VILB)
300
VILB
1.0
0.4
0.0
Propagation Delay (ns)
350
0.3 • VDD
1.4
VIL (V)
Output Level (V)
1.8
0.3 • VDD
1.6
Logic Low Input Levels - Side B
(VILB)
Margin (mV)
Logic Low Output Levels - Side B
(VOLB)
-40
-20
0
20
40
60
Temperature (ºC)
80
100
-30
-10
10
30
50
Temperature (ºC)
70
90
Propagation Delay Low to High
B to A to B
(VCC=3.3V, CL=20pF)
(RPUA=475Ω, RPUB=825Ω)
320
300
280
260
240
220
-60
-40
-20
0
20
40
60
Temperature (ºC)
80
100
*Unless otherwise noted, data presented in these graphs is typical of device operation at 25°C.
For guaranteed parameters not indicated in the written specifications, please contact our applications department.
R04
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7
CPC5902
INTEGRATED CIRCUITS DIVISION
3 Functional Description
3.1 Overview
The CPC5902 combines the features of multiple logic
optoisolators and an I2C bus repeater in a single 8-pin
package. It offers excellent isolation (3750Vrms) and
speed sufficient to support I2C Fast-mode at 400kbps.
It bidirectionally buffers the two I2C signals across the
isolation barrier, and supports I2C clock stretching. If
different supply voltage levels are used at each side,
then the part, in conjunction with its external pullup
resistors, will perform logic level translation for VDD
between 2.7V and 5.5V at either side.
The CPC5902, like available non-galvanically isolating
I2C bus repeaters, has a full drive side and a limited
drive side. It uses a voltage-limited output driver and a
lower VTHRESHOLD (VIL) at the Side B IO. The
voltage-limited Side B output driver can not output a
VOL level below an internally set voltage limit. This is
necessary to ensure that the CPC5902 cannot drive
its own IOB input to a level it accepts as a logic low,
which would cause I2C bus contention. The parts are
specified with a minimum VOL-VIL margin of 25mV at
minimum VDDB, and exhibit a proportionately larger
self-drive margin with larger VDDB.
The Side A drivers are Fast-mode, full strength (6mA)
over the full VDDA range, and the input thresholds are
specified to be Fast-mode compliant; thus Side A will
drive up to the full 400pF Fast-mode CLOAD and is
allowed to drive its own input to a logic low. Devices
meeting the I2C specification are easily able to drive
the IO nodes below the CPC5902’s lower VIL
(0.2VDDB) threshold at the Side B inputs, and will
correctly accept the CPC5902 Side B driven data,
thereby enabling Side B bidirectional communication
at up to 3mA of load current over the full VDDB range.
Over the entire VDDx range, Side A is fully I2C
Fast-mode compliant while Side B is I2C
Standard-mode compliant. It is important to note that
Side B can be operated at the Fast-mode date rate
when the capacitive loading on the bus is kept at
200pF or less, however when VDDB > 4.5V, Side B is
also Fast-mode compliant with up to 400pF capacitive
loading.
determined by tOPLH_AB. Side B deassertion occurs at
8
IO pullup resistors are required on both sides of the
barrier. At the Side B inputs, resistor values should be
chosen for Standard-mode 3mA pullup current (for
operation independent of VDDB). Pullups chosen for
Fast-mode drivers (up to 6mA) can be used at Side A
with no loss of noise margin.
Applying a pulse at a Side B input inherently involves
the use of some of the output driver circuits at that I/O.
In a manner similar to the I2C clock stretching feature,
once an asserted signal is determined to be valid, it is
stretched until its proper transmission through the
optics has been verified. This insures that there will be
no extra edges generated at either side due to optic
delays. If a Side B asserted-low pulse is long enough
to be accepted and passed to Side A, then the flip-flop
at Side B is set and remains set until the signal returns
through the optics from Side A.
In operation, a valid asserted pulse of less than 80ns
applied at Side B appears at Side A after a delay
largely determined by the low-pass filter delay (tFIL)
and the optics delay (tOPHL_BA). After this initial delay
the Side A driver is activated and a logic low is
asserted at time:
tSTARTA = tFIL + tOPHL_BA
That assertion is returned across the optics to Side B
after a delay largely determined by tOPHL_AB. Upon
arriving at Side B, the flip-flop is cleared, and the
deassertion is sent through the optics to Side A,
arriving at the Side A output after a delay largely
determined by tOPLH_BA at time:
tENDA = tFIL + tOPHL_BA + tOPHL_AB + tOPLH_BA
Thus a valid Side B pulse having a width less than
80ns is stretched at Side A to a typical width of 125ns.
The duration of the pulse width output onto the Side A
bus is given by:
tPWA_min = (tOPHL_AB + tOPLH_BA)
When Side A is deasserted, the output rises at a slew
rate determined by the RC load on IOA, and passes
the logic threshold after time tSLEWA. The deasserted
(logic HIGH) input propagates through the optics and
deasserts the Side B output after a delay largely
time tENDB given by:
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CPC5902
INTEGRATED CIRCUITS DIVISION
tENDB = tENDA + tSLEWA + tOPLH_AB
Thus at Side B input, an applied pulse of less than
80ns is stretched to:
tPWB_min = tFIL + tOPHL_BA + tOPHL_AB + tOPLH_BA + tSLEWA + tOPLH_AB
which is typically 330ns. More importantly, only one
pulse is seen at both ports, with no extra or missing
clock or data edges, assuring line integrity.
Pulses of width larger than approximately 80ns
applied to the Side B input do not utilize the flip-flop to
terminate the pulse, but do need to propagate to
Side A and then back to Side B when returning high
after being asserted low. The Side A pulse width is
given by the usual pulse width distortion relation:
tPWA_nom = tPULSE + tPLH_BA - tPHL_BA
which is typically tPULSE + 75ns. Note that tPLH_BA and
tPHL_BA are observed at the external pins, and are
provided in the table, “Electrical Specifications” on
page 4. The pulse at Side B is asserted by an
external driver pulling low, and lasts for time tPULSE. At
the end of the pulse, the rising edge passes through
the internal filter with delay tFIL, then applied to the
LED and received at Side A tOPLH_BA later. After time
tSLEWA the output at Side A crosses the logic high
threshold causing the Side A LED drive to deactivate,
which propagates the deasserted state back to Side B
with a delay of tOPLH_AB. Thus normal-width pulses of
width tPULSE applied at Side B (IOB) exhibit a
stretched pulse width of:
tPWB_nom = tPULSE + tFIL + tOPLH_BA + tSLEWA + tOPLH_AB
at IOB, which is also given by:
tPWB_nom = tPULSE + tPHL_BAB
and is typically tPULSE + 290ns.
Side A receivers have been designed to exhibit a
significant amount of hysteresis, which helps to
eliminate false clocking. They have not been internally
low-pass filtered beyond the filtering inherent within
the optical channel. When the I2C bus is terminated
for maximum bandwidth (6mA pullups and minimal
capacitance), the receivers typically will respond to
pulses greater than 12ns. If additional filtering is
desired, then externally increasing the load
capacitance of the I2C lines until the amount of time
the offending signal spends above/below VDD /2 is
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less than 10ns will reject the signal at the expense of
increasing rise and fall times.
Side B receivers do implement some hysteresis and
low-pass filtering in addition to the optics. An
asserted pulse typically needs to be held below
0.2VDD for 15ns before it is accepted at Side B input.
This may require a 30ns pulse applied by a typical
driver with just 20pF loading the I2C lines.
While any very short pulses stretched to the minimum
times above would seem to cause large amounts of
pulse width distortion, within 400kHz Fast-mode I2C
the shortest allowable signal or clock asserted low
time is 1.3s. Neither Standard-mode nor Fast-mode
variants include any legal signals that are less than
80ns (typ); thus the tPWA_nom and tPWB_nom equations
above always apply. The pulse width on valid longer
pulses receives less stretching and is proportionally
less noticeable. For example the Fast-mode minimum
clock low time of 1.3S when applied at Side B would
typically be seen as a 1.375S pulse at Side A and will
be stretched to a length of 1.59s for other devices on
the Side B bus.
Internal filtering and the flip-flop at Side B are used to
ensure that an equal number of pulse edges are seen
at both sides of the isolation barrier when Side B is
driven. When a signal at Side B is asserted low, the
flip-flop self-drives that Side B I/O pin until the optical
channel back from Side A proves that Side A has
successfully been asserted. While this is generally a
welcome error reduction feature and is especially
useful on the side with nonstandard levels, it does
need to be considered when assigning Side A and
Side B ports. If Side A is not powered up, then the
signal back from Side A will not appear until after
Side A has been powered, and the signal at Side B
will be stretched until that time. Side A uses filtered
hysteresis at its standard inputs, not pulse stretching,
to defeat sub-minimum-size pulses. Thus that side of
the isolation barrier, which will be the bus master at
power-up, should generally be assigned to Side A.
Note that the pinout of the package is rotationally
symmetrical. As a result, changing which side of the
isolation barrier utilizes Side A standard levels can be
accomplished by rotating the part 180° before it is
soldered onto the board.
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CPC5902
INTEGRATED CIRCUITS DIVISION
3.2 Calculating Minimum Pull-Up Resistor Values
The minimum value of the pull-up resistor, RPU, on the
2
I C bus is chosen based upon the expected VDD
supply voltage range and the weakest load current
sinking device on the bus. Note: Systems that do not
need maximum bandwidth and busses with lower
capacitive loading can use a higher value for the
pull-up resistor to reduce power consumption.
3.2.1 Side A Pull-Up Resistor: RPUA
The weakest I2C compliant device on the Side A bus,
with RPUA to VDDA, must be able to pull the Side A
inputs below 0.4V for outputs rated at 3mA or 0.6V for
outputs rated at 6mA when VDDA is at its maximum.
For example, if the weakest device is only guaranteed
to sink 3mA then the maximum allowed logic low
output voltage will be 0.4V. For designs with
VDDA_max = 3.6V, the minimum voltage across the
pull-up resistor is:
Minimum RPUA Voltage = 3.6 - 0.4 = 3.2V
For the I2C minimum current sink requirement of 3mA,
the minimum value of the pull-up resistor is easily
calculated as:
RPUA_min = 3.2V / 3mA = 1066.7
Chose a standard value resistor that will not violate
this minimum value over tolerance and temperature,
such as a 1.1k, 1% tolerance, 100ppm/C
temperature coefficient resistor.
If all the non-CPC5902 devices on the Side A bus are
Fast-mode compliant (400pF capacitive loading
capable) with the required 6mA current sink capability,
then the bus can be configured for Fast-mode.
Resistor selection for Fast-mode is similar to the
example given above but because the logic low output
level is greater (0.6V) then the voltage across the
pull-up resistor will be less. Calculation of the
compliant Fast-mode bus minimum pull-up resistor
value is given by:
RPUA_min = (3.6 - 0.6)V / 6mA = 500
The minimum E96 standard value 1% tolerance,
100ppm/C temperature coefficient resistor is 511.
3.2.2 Side B Pull-Up Resistor: RPUB
Calculating the pull-up resistor for Side B is similar to
the process used for Side A but with some additional
considerations.
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Before proceeding, it must be pointed out that Side B
of the CPC5902 is Fast-mode compliant with
VDDB 4.5V. This means the CPC5902 Side B
outputs are 6mA capable allowing bus operation of
400kb/s with up to 400pF of capacitive loading. For
VDDB supply levels below 4.5V the CPC5902 outputs
are only rated for 3mA but can be operated at
Fast-mode speeds of 400kb/s whenever the bus
capacitive loading CLOAD 200pF. Greater capacitive
loading of the Side B bus limits the CPC5902 to data
rates of 100kb/s.
First, it must be determined if the Side B bus will be
configured for 3mA or 6mA operation. This is done by
evaluating the external (non-CPC5602) devices on the
Side B bus and the operational capabilities of the
CPC5902. There are three possibilities:
1) One or more of the external devices is limited to
3mA of output current sink.
2) All of the external devices are rated at 6mA of
output current sink and the Side B minimum supply
voltage VDDB 4.5V.
3) All of the external devices are rated at 6mA of
output current sink and the Side B minimum supply
voltage VDDB 4.5V.
For conditions 1 and 2 above the bus must be
configured for 3mA. Condition 3 is the only situation
where the bus can be configured for 6mA, a
Fast-mode requirement when capacitive bus loading is
an issue.
Second, it is necessary to configure the Side B bus to
be compatible with the CPC5902’s lower logic low
input threshold:
VILB = 0.2 • VDDB - 60mV
As discussed earlier, this lower input threshold
requirement is to ensure the CPC5902 can drive a
logic low output that is recognized by the other I2C
devices on the bus, but will not accept it’s own logic
low output. This prevents latching of the CPC5902.
Additionally, this implies there can be no more than
one limited drive (Side B) CPC5902 interface on the
Side B bus, and that all other devices on the Side B
bus must have VIL = 0.3 • VDDB logic low input
thresholds. Because the CPC5902 Side A inputs are
compatible with this requirement, any number of
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CPC5902
INTEGRATED CIRCUITS DIVISION
CPC5902 Side A devices may be connected to the
Side B bus.
For all modes, the minimum required voltage drop
across the Side B pull-up resistor at VDDB_max by the
external non-CPC5902 I2C bus drivers is:
Minimum RPUB Voltage = VDDB_max - (0.2 • VDDB_max - 60mV)
= 0.8 • VDDB_max + 60mV
which gives the calculation for the minimum value of
the pull-up resistor as:
RPUB_min = (0.8 • VDDB_max + 60mV) / IOL
where IOL is the guaranteed logic low drive current of
the non-CPC5902 bus drivers.
For Standard-mode designs, with output drivers rated
at 3mA and a maximum supply voltage of 3.6V, the
minimum value of the pull-up resistor is:
RPUB_min = (0.8 • 3.6 + 60mV) / 3mA = 980
The minimal standard value 1% resistor with a
100ppm/C temperature coefficient that will not go
below the calculated minimum due to tolerance and
temperature is 1k.
In Fast-mode designs with 6mA capable output drivers
and a supply voltage maximum of 5.5V, the minimum
Fast-mode pull-up resistor value is calculated to be:
RPUB_min = (0.8 • 5.5 + 60mV) / 6mA = 743.3
For a Fast-mode design with high capacitive bus
loading a 768, 1%, 100ppm/C resistor would suffice.
When the bus does not have a heavy capacitive load
then a larger value pull-up resistor can be used
thereby reducing overall power consumption.
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CPC5902
INTEGRATED CIRCUITS DIVISION
4 Manufacturing Information
4.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of
the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of
our products to the maximum conditions set forth in the standard, and guarantee proper operation of our
devices when handled according to the limitations and information in that standard as well as to any
limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
CPC5902GS
Moisture Sensitivity Level (MSL) Classification
MSL 3
4.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
4.3 Soldering Profile
Provided in the table below is the IPC/JEDEC J-STD-020 Classification Temperature (TC) and the maximum dwell
time the body temperature of these surface mount devices may be (TC - 5)°C or greater. The Classification
Temperature sets the Maximum Body Temperature allowed for these devices during reflow soldering processes.
Device
Classification Temperature (TC)
Dwell Time (tp)
Max Reflow Cycles
CPC5902GS
250°C
30 seconds
3
The maximum wave soldering conditions of through-hole devices is provided in the following table. Dwell time is the
time it takes for the pins to pass through both waves.
Device
CPC5902G
Wave Temperature
260°C
Body Temperature
250°C
Dwell Time
10 seconds
Wave Cycles
1
4.4 Board Wash
IXYS Integrated Circuits recommends the use of no-clean flux formulations. Board washing to reduce or remove flux
residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to
the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake
cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of
the wash parameters used to clean the board, determination of the bake temperature and duration necessary to
remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying
methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must
not be exposed to halide flux or solvents that are Chlorine, Bromine, Fluorine, or Iodine-based.
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CPC5902
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4.5 Mechanical Dimensions
4.5.1 CPC5902G Package
9.652 ± 0.381
(0.380 ± 0.015)
2.540 ± 0.127
(0.100 ± 0.005)
8-0.800 DIA.
(8-0.031 DIA.)
2.540 ± 0.127
(0.100 ± 0.005)
9.144 ± 0.508
(0.360 ± 0.020)
6.350 ± 0.127
(0.250 ± 0.005)
Pin 1
PCB Hole Pattern
7.620 ± 0.254
(0.300 ± 0.010)
0.457 ± 0.076
(0.018 ± 0.003)
3.302 ± 0.051
(0.130 ± 0.002)
7.620 ± 0.127
(0.300 ± 0.005)
7.239 TYP.
(0.285)
4.064 TYP
(0.160)
0.254 ± 0.0127
(0.010 ± 0.0005)
7.620 ± 0.127
(0.300 ± 0.005)
Dimensions
mm
(inches)
0.813 ± 0.102
(0.032 ± 0.004)
4.5.2 CPC5902GS Package
9.652 ± 0.381
(0.380 ± 0.015)
2.540 ± 0.127
(0.100 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
Pin 1
3.302 ± 0.051
(0.130 ± 0.002)
0.635 ± 0.127
(0.025 ± 0.005)
9.525 ± 0.254
(0.375 ± 0.010)
0.457 ± 0.076
(0.018 ± 0.003)
PCB Land Pattern
2.54
(0.10)
8.90
(0.3503)
1.65
(0.0649)
7.620 ± 0.254
(0.300 ± 0.010)
0.254 ± 0.0127
(0.010 ± 0.0005)
0.65
(0.0255)
4.445 ± 0.127
(0.175 ± 0.005)
Dimensions
mm
(inches)
0.813 ± 0.102
(0.032 ± 0.004)
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CPC5902
INTEGRATED CIRCUITS DIVISION
4.5.3 CPC5902GSTR Tape & Reel Packaging
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
W=16.00
(0.63)
Bo=10.30
(0.406)
K0 =4.90
(0.193)
Ao=10.30
(0.406)
K1 =4.20
(0.165)
Embossed Carrier
Embossment
P1=12.00
(0.472)
User Direction of Feed
Dimensions
mm
(inches)
NOTES:
1. Dimensions carry tolerances of EIA Standard 481-2
2. Tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2
For additional information please visit our website at: www.ixysic.com
Disclaimer Notice - Littelfuse products are not designed for, and shall not be used for, any purpose (including, without limitation, automotive, military, aerospace,
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failure or lack of desired operation of the product may result in personal injury, death, or property damage) other than those expressly set forth in applicable Littelfuse
product documentation. Warranties granted by Littelfuse shall be deemed void for products used for any purpose not expressly set forth in applicable Littelfuse
documentation. Littelfuse shall not be liable for any claims or damages arising out of products used in applications not expressly intended by Littelfuse as set forth in
applicable Littelfuse documentation. The sale and use of Littelfuse products is subject to Littelfuse Terms and Conditions of Sale, unless otherwise agreed by
Littelfuse. Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and test each product
selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications.
Read complete Disclaimer Notice at www.littelfuse.com/disclaimer-electronics.
Specification: DS-CPC5902-R04
©Copyright 2019, IXYS Integrated Circuits
All rights reserved. Printed in USA.
9/25/2019
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