SP721AB

TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP721 The SP721 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection to sensitive input circuits. The SP721 has 2 protection SCR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Over-voltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) to V+ or V-. The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ (Pin 8) or a -VBE diode threshold below V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input. Standard ESD Human Body Model (HBM) Capability is: Features HBM STANDARD MODE IEC 61000-4-2 Air MIL-STD-3015.7 R C ESD (V) 330Ω 150pF >15kV Direct 330Ω 150pF >4kV Direct, Dual Pins 330Ω 150pF >8kV Direct, In-Circuit 1.5kΩ 100pF >15kV Refer to Figure 1 and Table 1 for further detail. Refer to Application Notes AN9304 and AN9612 for additional information. Ordering Information PART NO. TEMP. RANGE (oC) PACKAGE PKG. NO. Min. Order SP721AP -40 to 105 8 Ld PDIP E8.3 2000 SP721AB -40 to 105 8 Ld SOIC M8.15 1960 SP721ABT -40 to 105 8 Ld SOIC Tape and Reel M8.15 2500 • ESD Interface Capability for HBM Standards - MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15kV - IEC 61000-4-2, Direct Discharge, - Single Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2) - Two Inputs in Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 8kV (Level 4) - IEC 61000-4-2, Air Discharge . . . . . . . . . . . . . . . . . . 15kV (Level 4) • High Peak Current Capability - IEC 61000-4-5 (8/20µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3A - Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . ±2A - Single Pulse, 4µs Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . ±5A • Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to . . . . . . . . . . . . . . . . . . . . . . . . +30V - Differential Voltage Range to. . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Fast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2ns Rise Time • Low Input Leakages . . . . . . . . . . . . . . . . . . . . . . . . 1nA at 25oC Typical • Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3pF Typical • An Array of 6 SCR/Diode Pairs • Operating Temperature Range . . . . . . . . . . . . . . . . . . . . -40oC to 105oC Pinout Applications SP721 (PDIP, SOIC) TOP VIEW • Microprocessor/Logic Input Protection • Data Bus Protection IN 1 8 V+ IN 2 7 IN IN 3 6 IN V- 4 5 IN • Analog Device Input Protection • Voltage Clamp Functional Block Diagram V+ 8 3, 5-7 IN 1 V- 4 234 w w w. l i t t e l f u s e . c o m IN 2 IN TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP721 Absolute Maximum Ratings Thermal Information Continuous Supply Voltage, (V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . +35V Thermal Resistance (Typical, Note 1) Forward Peak Current, IIN to VCC , IIN to GND (Refer to Figure 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2A, 100µs ESD Ratings and Capability (Figure 1, Table 1) Load Dump and Reverse Battery (Note 2) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Storage Temperature Range . . . . . . . . . . . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature (Plastic Package) . . . .. . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . . .. . . . . . . . . . . .300oC (SOIC Lead Tips Only) θJA (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = -40oC to 105oC, VIN = 0.5VCC , Unless Otherwise Specified PARAMETER Operating Voltage Range, VSUPPLY = [(V+) - (V-)] SYMBOL TEST CONDITIONS VSUPPLY MIN TYP MAX UNITS - 2 to 30 - V - 2 2 - V V Forward Voltage Drop Input Leakage Current Quiescent Supply Current IIN = 1A (Peak Pulse) VFWDL VFWDH IIN -20 5 +20 nA IQUIESCENT - 50 200 nA Equivalent SCR ON Threshold Note 3 - 1.1 - V Equivalent SCR ON Resistance VFWD /IFWD; Note 3 - 1 - Ω Input Capacitance CIN - 3 - pF Input Switching Speed tON - 2 - ns 5 TVS DIODE ARRAYS IN to VIN to V+ NOTES: 2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- Pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here for thumb-rule information to determine peak current and dissipation under EOS conditions. ESD Capability TABLE 1. ESD TEST CONDITIONS ESD capability is dependent on the application and defined test standard.The evaluation results for various test standards and methods based on Figure 1 are shown in Table 1. For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit” method of ESD testing, the V+ and V- pins have a return path to ground and the SP721 ESD capability is typically greater than 15kV from 100pF through 1.5kΩ. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing, the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results were determined from AT&T ESD Test Lab measurements. STANDARD TYPE/MODE RD MIL-STD-3015.7 Modified HBM IEC 61000-4-2 EIAJ IC121 The HBM capability to the IEC 61000-4-2 standard is greater than 15kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess of 8kV (Level 4). For ESD testing of the SP721 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than 1kV from 200pF with no series resistance. CD ±VD 1.5kΩ 100pF 15kV Standard HBM 1.5kΩ 100pF HBM, Air Discharge 330Ω 150pF 15kV HBM, Direct Discharge 330Ω 150pF 4kV HBM, Direct Discharge, Two Parallel Input Pins 330Ω 150pF 8kV Machine Model 0kΩ 1kV R1 200pF 6kV RD CHARGE SWITCH DISCHARGE SWITCH CD H.V. SUPPLY ±VD IN DUT IEC 1000-4-2: R 1 50 to 100MΩ MIL-STD-3015.7: R 11 to 10MΩ FIGURE 1. ELECTROSTATIC DISCHARGE TEST w w w. l i t t e l f u s e . c o m 235 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP721 100 2.5 TA = 25oC SINGLE PULSE 2 FORWARD SCR CURRENT (A) FORWARD SCR CURRENT (mA) 80 TA = 25oC SINGLE PULSE 60 40 20 1.5 1 IFWD EQUIV. SAT. ON THRESHOLD ~ 1.1V 0.5 0 VFWD 0 600 800 1000 1200 0 FORWARD SCR VOLTAGE DROP (mV) FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP CURVE 1 2 FORWARD SCR VOLTAGE DROP (V) FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP CURVE +VCC +VCC INPUT DRIVERS OR SIGNAL SOURCES LINEAR OR DIGITAL IC INTERFACE IN 1 - 3 IN 5 - 7 TO +VCC V+ SP721 V- SP721 INPUT PROTECTION CIRCUIT (1 OF 6 SHOWN) FIGURE 4. TYPICAL APPLICATION OF THE SP721 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1VBE ABOVE V+ OR LESS THAN -1V BE BELOW V- 236 3 w w w. l i t t e l f u s e . c o m TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP721 Peak Transient Current Capability of the SP721 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP721’s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure 5. + VX - VARIABLETIME DURATION CURRENT PULSE GENERATOR R1 CURRENT SENSE (-) The test circuit of Figure 5 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP721 ‘IN’ input pin and the (+) current pulse input goes to the SP721 V- pin. The V+ to V- supply of the SP721 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 6 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. (+) 1 IN 2 IN V+ 8 IN 7 3 IN IN 6 4 IN 5 SP721 + C1 - VOLTAGE PROBE The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 25oC and 105oC and a 15V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of Figure 6. V- R1 ~ 10Ω TYPICAL VX ADJ. 10V/A TYPICAL C1 ~ 100µF Note that adjacent input pins of the SP721 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin. 7 CAUTION: SAFE OPERATING CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EACH CURVE. PEAK CURRENT (A) 6 TA = 25oC 5 V+ TO V- SUPPLY = 15V 4 TA = 105oC 3 2 1 0 0.001 0.01 0.1 1 10 100 1000 PULSE WIDTH TIME (ms) FIGURE 6. SP721 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVERSTRESS IN AMPERES vs PULSE WIDTH TIME IN MILLISECONDS w w w. l i t t e l f u s e . c o m 5 TVS DIODE ARRAYS FIGURE 5. TYPICAL SP721 PEAK CURRENT TEST CIRCUIT WITH A VARIABLE PULSE WIDTH INPUT 237 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP721 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE N INCHES E1 INDEX AREA 1 2 3 N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 0.355 - C D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 10.16 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - L 0.115 N 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 238 MILLIMETERS SYMBOL w w w. l i t t e l f u s e . c o m 8 0.430 - 0.150 2.93 8 10.92 7 3.81 4 9 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP721 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M INCHES B M SYMBOL E -B1 2 3 L SEATING PLANE -A- h x 45o A D µ e A1 B 0.25(0.010) M C 0.10(0.004) C A M MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e -C- B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS MIN µ 8 0o 8 7 8o - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. w w w. l i t t e l f u s e . c o m 5 TVS DIODE ARRAYS N 239