SP721APP

TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP721 Series SP721 Series 3pF 4kV Diode Array RoHS Pb GREEN Description The SP721 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection to sensitive input circuits. The SP721 has 2 protection SCR/Diode device structures per input. There are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. Overvoltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7) to V+ or V-. The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ (Pin 8) or a -VBE diode threshold below V- (Pin 4). From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input. Standard ESD Human Body Model (HBM) Capability is: Pinout SP721 (PDIP, SOIC) TOP VIEW IN 1 8 V+ IN 2 7 IN Features IN 3 6 IN • ESD Interface Capability for HBM Standards V- 4 5 IN - MIL STD 3015.7.................................................. 15kV - IEC 61000-4-2, Direct Discharge, - Single Input........................................... 4kV (Level 2) - Two Inputs in Parallel............................. 8kV (Level 4) - IEC 61000-4-2, Air Discharge................15kV (Level 4) Functional Block Diagram • High Peak Current Capability - IEC 61000-4-5 (8/20µs)........................................ ±3A - Single Pulse, 100µs Pulse Width......................... ±2A - Single Pulse, 4µs Pulse Width............................. ±5A • Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to......................... +30V - Differential Voltage Range to............................. ±15V • Fast Switching..............................................2ns Rise Time • Low Input Leakages.............................1nA at 25ºC Typical • Low Input Capacitance......................................3pF Typical • An Array of 6 SCR/Diode Pairs • Operating Temperature Range....................-40ºC to 105ºC Additional Information Resources © 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 05/12/17 Applications Samples • Microprocessor/Logic Input Protection • Analog Device Input Protection • Data Bus Protection • Voltage Clamp TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP721 Series Thermal Information Absolute Maximum Ratings Parameter Continuous Supply Voltage, (V+) - (V-) Forward Peak Current, IIN to VCC, IIN to GND (Refer to Figure 5) Rating +35 Units V ±2, 100µs A Parameter Thermal Resistance (Typical, Note 1) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Rating θJA ESD Ratings and Capability (Figure 1, Table 1) C/W PDIP Package 160 o SOIC Package 170 o Maximum Storage Temperature Range Maximum Junction Temperature (Plastic Package) Maximum Lead Temperature (Soldering 20-40s)(SOIC Lead Tips Only) Note: Units oC/W C/W -65 to 150 o 150 o C 260 o C C Load Dump and Reverse Battery (Note 2) 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Characteristics TA = -40oC to 105oC, VIN = 0.5VCC , Unless Otherwise Specified Parameter Operating Voltage Range, Symbol Test Conditions VSUPPLY Min Typ Max Units - 2 to 30 - V VSUPPLY = [(V+) - (V-)] Forward Voltage Drop IN to V- VFWDL - 2 - V IN to V+ VFWDH - 2 - V IIN -20 5 +20 nA IQUIESCENT - 50 200 nA Note 3 - 1.1 - V VFWD/IFWD; Note 3 - 1 - Ω Input Leakage Current Quiescent Supply Current IIN = 1A (Peak Pulse) Equivalent SCR ON Threshold Equivalent SCR ON Resistance Input Capacitance CIN - 3 - pF Input Switching Speed tON - 2 - ns Notes: 2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to het same supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger romf the V+ and V- Pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance”. These characteristics are given here for thumb-rule nformation to determine peak current and dissipation under EOS conditions. Typical Application of the SP721 (Application as an Input Clamp for Over-voltage, Greater than 1VBE Above V+ or less than -1VBE below V-) © 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 05/12/17 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP721 Series ESD Capability ESD capability is dependent on the application and defined test standard.The evaluation results for various test standards and methods based on Figure 1 are shown in Table 1. Figure 1: Electrostatic Discharge Test For the “Modified”MIL-STD-3015.7 condition that is defined as an “in-circuit” method of ESD testing, the V+ and V- pins have a return path to ground and the SP721 ESD capability is typically greater than 15kV from 100pF through 1.5kΩ.By strict definition of MIL-STD-3015.7 using “pin-to-pin”device testing, the ESD voltage capability is greater than 6kV.The MIL-STD-3015.7 results were determined from AT&T ESD Test Lab measurements. The HBM capability to the IEC 61000-4-2 standard is greater than 15kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level 2).Dual pin capability (2 adjacent pins in parallel) is well in excess of 8kV (Level 4). For ESD testing of the SP721 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than 1kV from 200pF with no series resistance. Table 1: ESD Test Conditions Standard MIL STD 3015.7 IEC 61000-4-2 EIAJ IC121 Figure 2: Low Current SCR Forward Voltage Drop Curve © 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 05/12/17 Type/Mode RD CD ±VD Modified HBM 1.5kΩ 100pF 15kV Standard HBM 1.5kΩ 100pF 6kV HBM, Air Discharge 330Ω 150pF 15kV HBM, Direct Discharge 330Ω 150pF 4kV HBM, Direct Discharge, Two Parallel Input Pins 330Ω 150pF 8kV 0kΩ 200pF 1kV Machine Model Figure 3: High Current SCR Forward Voltage Drop Curve TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP721 Series Peak Transient Current Capability of the SP721 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP721’s ability to withstand a wide range of peak current pulses vs time. The circuit used to generate current pulses is shown in Figure 4. Figure 4: T  ypical SP721 Peak Current Test Circuit with a Variable Pulse Width Input The test circuit of Figure 4 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP721 ‘IN’ input pin and the (+) current pulse input goes to the SP721 V- pin. The V+ to V- supply of the SP721 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 5 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. Note that adjacent input pins of the SP721 may be paralleled to improve current (and ESD) capability. The sustained peak current capability is increased to nearly twice that of a single pin. Figure 5: S  P721 Typical Single Peak Current Pulse Capability  howing the Measured Point of Overstress in Amperes vs S pulse width time in milliseconds 7 6 PEAK CURRENT (A) The maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. Peak current curves are shown for ambient temperatures of 25ºC and 105ºC and a 15V power supply condition. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of Figure 5. 5 TA = 25°C 4 CAUTION: SAFE OPERATING CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EACH CURVE. V+ TO V-SUPPLY = 15V TA = 105°C 3 2 1 0 0.001 0.01 0.1 1 10 100 1000 PULSE WIDTH TIME (ms) © 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 05/12/17 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP721 Series Soldering Parameters Reflow Condition Pre Heat Pb – Free assembly - Temperature Min (Ts(min)) 150°C - Temperature Max (Ts(max)) 200°C - Time (min to max) (ts) 60 – 180 secs Average ramp up rate (Liquidus) Temp (TL) to peak 5°C/second max TS(max) to TL - Ramp-up Rate 5°C/second max Reflow - Temperature (TL) (Liquidus) 217°C - Temperature (tL) 60 – 150 seconds Peak Temperature (TP) 260+0/-5 °C Time within 5°C of actual peak Temperature (tp) 20 – 40 seconds Ramp-down Rate 5°C/second max Time 25°C to peak Temperature (TP) 8 minutes Max. Do not exceed 260°C Package Dimensions — Dual-In-Line Plastic Packages (PDIP) Package PDIP Pins 8 Lead Dual-in-Line JEDEC MS-001 Millimeters Min Notes: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is t he maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 05/12/17 A A1 A2 B B1 C D D1 E E1 e eA eB L N Max 5.33 0.39 2.93 4.95 0.356 0.558 1.15 1.77 0.204 0.355 9.01 10.16 0.13 7.62 8.25 6.10 7.11 2.54 BSC 7.62 BSC 10.92 2.93 3.81 8 Inches Min Max 0.210 0.015 0.115 0.195 0.014 0.022 0.045 0.070 0.008 0.014 0.355 0.400 0.005 0.300 0.325 0.240 0.280 0.100 BSC 0.300 BSC 0.430 0.115 0.150 8 Notes 4 4 8, 10 5 5 6 5 6 7 4 9 TVS Diode Arrays (SPA® Diodes) General Purpose ESD Protection - SP721 Series Package Dimensions — Small Outline Plastic Packages (SOIC) N INDEX AREA H 0.25(0.010) M B M E 2 SOIC Pins 8 JEDEC -B1 Package 3 MS-012 Millimeters L SEATING PLANE -A- -Cμ e A1 B C 0.10(0.004) 0.25(0.010) M C A M B S Notes: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. NOTES: 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 1. Symbolsare definedin the “MOSeries SymbolList”in Section 2.2 of 3. Dimension “D” does Number not include Publication 95. mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed (0.006 inch) per side. 2. Dimensioning and tolerancing per0.15mm ANSI Y14.5M-1982. Max Min Max 1.35 1.75 0.0532 0.0688 A1 0.10 0.25 0.0040 0.0098 - B 0.33 0.51 0.013 0.020 9 C 0.19 0.25 0.0075 0.0098 - D 4.80 5.00 0.1890 0.1968 3 E 3.80 4.00 0.1497 0.1574 4 0.2284 0.2440 - h 0.25 0.50 0.0099 0.0196 5 L 0.40 1.27 0.016 0.050 6 8º 0º µ G = Green P = Lead Free TG= Tape and Reel - 6.20 N TVS Diode Arrays (SPA® Diodes) 0.050 BSC 5.80 5. The chamfer onper theside. body is optional. If it is not present, a visual index feature must be inch) located4.within the crosshatched Dimension “E”does notarea. includeinterleadflash or protrusions.Inter- SP 721 ** ** 1.27 BSC e - H 4. Dimension “E” does“D” notdoes include flashflash, or protrusions. Inter-lead flash and 3. Dimension notinterlead includemold protrusions or gate burrs. protrusions shall not protrusion exceed 0.25mm (0.010 inch) per Mold flash, and gate burrs shall notside. exceed 0.15mm(0.006 flash and protrusions shall not 0.25mm (0.010 inch) per 6. “L” is the lead length of terminal for soldering to aexceed substrate. 7. “N” is theside. number of terminal positions. 5. The chamferon the bodyis optional.If it is not present,a visualindex 8. Terminal numbers are shown for reference only. feature must be located withinthe crosshatchedarea. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating 6. “L” is the lengthof terminalfor solderingto a substrate. plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. “N”is the numberof terminalpositions. 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. Terminal numbersare shownfor reference only. 9. The lead width“B”, as measured0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). Part Numbering System 10. Controllingdimension:MILLIMETER. Convertedinch dimensions are not necessarilyexact. Notes Min A h x 45o A D Inches 8 0º 8 7 8º - Product Characteristics Lead Plating Matte Tin Lead Material Copper Alloy Lead Coplanarity 0.004 inches (0.102mm) Substitute Material Silicon Body Material Molded Epoxy Flammability UL 94 V-0 Package Series AB = 8 Ld SOIC AP = 8 Ld PDIP Ordering Information Part Number Temp. Range (ºC) Package Environmental Informaton Marking SP721APP -40 to 105 8 Ld PDIP Lead-free SP721AP(P) 1 SP721ABG -40 to 105 8 Ld SOIC SP721ABTG -40 to 105 8 Ld SOIC Tape and Reel Min. Order 2000 Green SP721A(B)G 2 1960 Green SP721A(B)G 2 2500 Notes: 1. SP721AP(P) means device marking either SP721AP or SP721APP. 2. SP721A(B)G means device marking either SP721AG or SP721ABG which are good for types SP721ABG and SP721ABTG. Disclaimer Notice - Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and test each product selected for their own applications. Littelfuse products are not designed for, and may not be used in, all applications. Read complete Disclaimer Notice at www.littelfuse.com/disclaimer-electronics. © 2017 Littelfuse, Inc. Specifications are subject to change without notice. Revised: 05/12/17