TVS Diode Arrays (SPA® Diodes) Datasheet
SP725 Series
5pF 8kV Diode Array
RoHS
Pb
GREEN
Description
The SP725 is an array of SCR/Diode bipolar structures for ESD and
overvoltage protection of sensitive input circuits. The SP725 has 2
protection SCR/Diode device structures per input. There are a total
of 4 available inputs that can be used to protect up to 4 external
signal or bus lines. Over-voltage protection is from the IN (Pins 1 4) to V+ or V-.
The SCR structures are designed for fast triggering at a threshold
of one +VBE diode threshold above V+ (Pin 5,6) or one –VBE diode
threshold below V- (Pin 7,8). From an IN input, a clamp to V+ is
activated if a transient pulse causes the input to be increased to a
voltage level greater than one VBE above V+. A similar clamp to Vis activated if a negative pulse, one VBE less than V-, is applied to
an IN input.
Refer to Fig 1 and Table 1 for further details. Refer to Application
Note AN9304 and AN9612 for further detail.
Additional Information
Features & Benefits
■ ESD Interface per HBM Standards
■ IEC 61000-4-2, Direct Discharge 8kV (Level 4)
■ IEC 61000-4-2, Air Discharge 15kV (Level 4)
■ MIL-STD-3015.7 25kV
Resources
Accessories
■ Peak Current Capability
Samples
■ IEC 61000-4-5 8/20 µs Peak Pulse Current ± 14 A
■ Single Transient Pulse, 100 µs Pulse Width ± 8 A
Pinout
■ Designed to Provide Over-Voltage Protection
■ Single-Ended Voltage Range to +30V
In
SP725
(SOIC)
8
1
V-
In
2
7
V-
In
3
6
V+
In
4
5
V+
■ Differential Voltage Range to ±15V
■ Fast Switching 2ns Risetime
■ Low Input Leakages 5 nA at 25 ºC Typical
■ Low Input Capacitance 5 pF Typical
■ An Array of 4 SCR/Diode Pairs
■ Operating Temperature Range -40 ºC to 105 ºC
Applications
Functional Block Diagram
V+
5, 6
IN
1
IN 2
■ Microprocessor/Logic Input
Protection
■ Analog Device Input
Protection
■ Data Bus Protection
■ Voltage Clamp
IN
3, 4
V7, 8
Life Support Note:
Not Intended for Use in Life Support or Life Saving Applications
The products shown herein are not designed for use in life sustaining or life saving
applications unless otherwise expressly indicated.
1
© 2022 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: GD. 09/07/22
TVS Diode Arrays (SPA® Diodes) Datasheet
SP725 Series
5pF 8kV Diode Array
Thermal Information
Absolute Maximum Ratings
Parameter
Rating
Continuous Supply Voltage, (V+) - (V-)
Forward Peak Current, IIN to VCC , IIN to GND
(Refer to Figure 5)
Peak Pulse Current, 8/20µs
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
Parameter
Units
+35
Thermal Resistance (Typical, Note 1)
V
± 8, 100 µs
A
± 14
A
Rating
SOIC Package
Storage Temperature Range
Maximum Junction Temperature
Maximum Lead Temperature
(Soldering 20-40s) (SOIC - Lead Tips Only)
Caution: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress only rating and operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied.
Units
C/W
θJA
o
170
o
C/W
C
-65 to 150
o
150
o
260
o
C
C
Electrical Characteristics TA = -40oC to 105oC, VIN = 0.5VCC , Unless Otherwise Specified
Parameter
Symbol
Operating Voltage Range,
VSUPPLY = [(V+) - (V-)]
Test Conditions
VSUPPLY
Min
Typ
Max
Units
-
2 to 30
-
V
V
Forward Voltage Drop
IIN = 2A (Peak Pulse)
IN to V-
VFWDL
-
2
-
IN to V+
VFWDH
-
2
-
V
IIN
-20
5
+20
nA
Input Leakage Current
Quiescent Supply Current
IQUIESCENT
Equivalent SCR ON Threshold
Equivalent SCR ON Resistance
Input Capacitance
CIN
Input Switching Speed
tON
-
50
200
nA
(Note 3)
-
1.1
-
V
VFWD/IFWD ; (Note 3)
-
0.5
-
Ω
5
-
pF
2
-
ns
-
Notes:
1. θJA is measured with the component mounted on an evaluation PC board in free air
2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery V+ and V- pins are connected to the same supply voltage source as the device or control line
under protection, a current limiting resistor should be connected in series between the external supply and the SP725 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically
0.01µF or larger from the V+ and V- pins to ground are recommended.
3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here for thumb-rule information to determine peak current and dissipation under EOS
conditions.
Typical Application of the SP725
(Application as an Input Clamp for Overvoltage, Greater than
1VBE Above V+ or less than -1VBE below V-)
+V CC
+V CC
INPUT
DRIVERS
OR
SIGNAL
SOURCES
LINEAR OR
DIGITAL IC
INTERFACE
IN 1 - 4
TO +V CC
V+
SP725
V-
SP725 INPUT PROTECTION CIRCUIT (1 OF 4 SHOWN)
2
© 2022 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: GD. 09/07/22
TVS Diode Arrays (SPA® Diodes) Datasheet
SP725 Series
5pF 8kV Diode Array
ESD Capability
Figure 1:
Electrostatic Discharge Test
ESD capability is dependent on the application and defined test
standard.The evaluation results for various test standards and
methods based on Figure 1 are shown in Table 1.
The SP725 has a Level 4 HBM capability when tested as a device
to the IEC 61000-4-2 standard. Level 4 specifies a required
capability greater than 8kV for direct discharge and greater than
15kV for air discharge.
For the “Modified” MIL-STD-3015.7 condition that is defined as an
“incircuit” method of ESD testing, the V+ and V- pins have a return
path to ground and the SP725 ESD capability is typically greater
than 25kV from 100pF through 1.5kΩ . By strict definition of MILSTD-3015.7 using “pinto-pin” device testing, the ESD voltage
capability is greater than 10kV.
For the SP725 EIAJ IC121 Machine Model (MM) standard, the
ESD capability is typically greater than 2kV from 200pF with no
series resistance.
R1
RD
CHARGE
SWITCH
DISCHARGE
SWITCH
CD
H.V.
SUPPLY
± VD
IN
DUT
IEC 61000-4-2: R 1
50 to 100M Ω
MIL-STD-3015.7: R 1
1 to 10M Ω
Table 1:
ESD Test Conditions
Standard
Type/Mode
HBM, Air Discharge
IEC 61000-4-2
(Level 4)
MIL-STD-3015.7
EIAJ IC121
Figure 2:
Low Current SCR Forward Voltage Drop Curve
200
CD
±VD
330 Ω
150pF
15kV
HBM, Direct Discharge 330 Ω
150pF
8kV
Modified HBM
1.5k Ω
100pF
25kV
Standard HBM
1.5k Ω
100pF
10kV
Machine Model
0k Ω
200pF
2kV
Figure 3:
High Current SCR Forward Voltage Drop Curve
5
TA = 25ºC
SINGLE PULSE
TA = 25°C
SINGLE PULSE
4
FORWARD SCR CURRENT (A)
160
FORWARD SCR CURRENT (mA)
RD
120
80
40
0
600
3
2
I FWD
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
1
V FWD
0
800
1000
1200
0
FORWARD SCR VOLT AGE DROP (mV)
1
2
3
FORWARD SCR VOLT AGE DROP (V)
3
© 2022 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: GD. 09/07/22
TVS Diode Arrays (SPA® Diodes) Datasheet
SP725 Series
5pF 8kV Diode Array
Peak Transient Current Capability for Long Duration Surges
Figure 4:
Typical SP725 Peak Current Test Circuit
with a Variable Pulse Width Input
The peak transient current capability rises sharply as the width of
the current pulse narrows. Destructive testing was done to fully
evaluate the SP725 ’s ability to withstand a wide range of peak
current pulses vs time. The circuit used to generate current pulses
is shown in Figure 4.
The test circuit of Figure 4 is shown with a positive pulse input.
For a negative pulse input, the (-) current pulse input goes to an
SP725 ‘IN’ input pin and the (+) current pulse input goes to the
SP725 V- pin. The V+ to V- supply of the SP725 must be allowed
to float. (i.e., It is not tied to the ground reference of the current
pulse generator.) Figure 5 shows the point of overstress as defined
by increased leakage in excess of the data sheet published limits.
The maximum peak input current capability is dependent on the
ambient temperature, improving as the temperature is reduced.
Peak current curves are shown for ambient temperatures of 25 º C
and 105 º C and a 15V power supply condition. The safe operating
range of the transient peak current should be limited to no more
than 75% of the measured overstress level for any given pulse
width as shown in the curves of Figure 5.
Note that adjacent input pins of the SP725 may be paralleled to
improve current (and ESD) capability. The sustained peak current
capability is increased to nearly twice that of a single pin.
+
-
VARIABLE TIME DURATION
CURRENT PULSE GENERATOR
R1
CURRENT
SENSE
VX
( -)
(+)
V- 8
1 IN
2 IN
3 IN
VSP72 5
4 IN
VOLTAGE
PROBE
7
+
V+ 6
-
V+ 5
C1
R 1 ~ 10 Ω TYPICAL
V X ADJ. 10V/A TYPICAL
C1 ~ 100 m F
Figure 5:
SP725 Typical Nonrepetitive Peak Current Pulse Capability
Showing the Measured Point of Overstress in Amperes vs pulse
width time in milliseconds
14
CAUTION: SAFE OPERATING CONDITIONS LIMIT
THE MAXIMUM PEAK CURRENT FOR A GIVEN
PULSE WIDTH TO BE NO GREATER THAN 75%
OF THE VALUES SHOWN ON EACH CURVE
PEAK CURRENT (A)
12
TA = 25ºC
10
V+ TO V-SUPPLY = 15V
8
6
TA = 105ºC
4
2
0
0.0001
0.01
0.1
1
10
100
1000
PULSE WIDTH TIME (ms)
4
© 2022 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: GD. 09/07/22
TVS Diode Arrays (SPA® Diodes) Datasheet
SP725 Series
5pF 8kV Diode Array
Soldering Parameters
Pb – Free assembly
Pre Heat
- Temperature Min (Ts(min))
150°C
- Temperature Max (Ts(max))
200°C
- Time (min to max) (ts)
60 – 180 secs
Average ramp up rate (Liquidus) Temp (TL) to
peak
5°C/second max
TS(max) to TL - Ramp-up Rate
5°C/second max
Reflow
tP
TP
- Temperature (TL) (Liquidus)
217°C
- Temperature (tL)
60 – 150 seconds
Peak Temperature (TP)
260+0/-5 °C
Time within 5°C of actual peak Temperature (tp)
20 – 40 seconds
Ramp-down Rate
5°C/second max
Time 25°C to peak Temperature (TP)
8 minutes Max.
Do not exceed
260°C
Temperature
Reflow Condition
Critical Zone
TL to TP
Ramp-up
TL
TS(max)
tL
Ramp-do
Ramp-down
Preheat
TS(min)
25
tS
time to peak temperature
Time
Package Dimensions — Small Outline Plastic Packages (SOIC)
Package
N
INDEX
AREA
H
0.25(0.010) M
B M
E
8
JEDEC
MS-012
Millimeters
-B1
2
3
h x 45o
A
D
-C-
µ
e
B
A1
C
0.10(0.004)
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs
shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not
exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the
crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed
a maximum value of 0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
Min
Max
1.35
1.75
0.0532
0.0688
A1
0.10
0.25
0.0040
0.0098
-
B
0.33
0.51
0.013
0.020
9
-
C
0.19
0.25
0.0075
0.0098
-
D
4.80
5.00
0.1890
0.1968
3
E
3.80
4.00
0.1497
0.1574
4
1.27 BSC
0.050 BSC
-
H
5.80
6.20
0.2284
0.2440
-
h
0.25
0.50
0.0099
0.0196
5
L
0.40
1.27
0.016
8
N
µ
5
Notes
Max
e
0.25(0.010) M C A M B S
Inches
Min
A
L
SEATING PLANE
-A-
SOIC
Pins
0o
0.050
8
8o
0o
6
7
8o
-
© 2022 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: GD. 09/07/22
TVS Diode Arrays (SPA® Diodes) Datasheet
SP725 Series
5pF 8kV Diode Array
Part Numbering System
Product Characteristics
SP 725 AB *
G=Green
TG=Tape and Reel
TVS Diode Arrays
(SPA® Diodes)
Series
Package Type
AB: 8 Leaded SOIC
Lead Plating
Matte Tin
Lead Material
Copper Alloy
Lead Coplanarity
0.004 inches (0.102mm)
Substitute Material
Silicon
Body Material
Molded Epoxy
Flammability
UL 94 V-0
Notes:
1. All dimensions are in millimeters.
2. Dimensions include solder plating.
3. Dimensions are exclusive of mold flash & metal burr.
4.Blo is facing up for mold and facing down for trim/form, i.e. reverse trim/form.
5. Package surface matte finish VDI 11-13.
Ordering Information
Part Number
Temp. Range (ºC)
Package
Marking
Min. Order Qty.
SP725ABG
-40 to 105
8 Ld SOIC
SP725AB(T)G 1
1960
SP725ABTG
-40 to 105
8 Ld SOIC Tape and Reel
SP725AB(T)G
2500
1
Notes:
1. SP725AB(T)G means device marking either SP725ABG or SP725ABTG.
Embossed Carrier Tape & Reel Specification - SOIC Package
User Feeding Direction
Symbol
Pin 1 Location
Millimetres
Inches
Min
Max
Min
Max
E
1.65
1.85
0.065
0.073
F
5.4
5.6
0.213
0.22
P2
1.95
2.05
0.077
0.081
D
1.5
1.6
0.059
0.063
1.50 Min
D1
P0
3.9
0.059 Min
4.1
40.0 ± 0.20
10P0
0.154
0.161
1.574 ± 0.008
W
11.9
12.1
0.468
0.476
P
7.9
8.1
0.311
0.319
A0
6.3
6.5
0.248
0.256
B0
5.1
5.3
0.2
0.209
K0
2
2.2
0.079
0.087
t
0.30 ± 0.05
0.012 ± 0.002
Disclaimer Notice - Information furnished is believed to be accurate and reliable. However, users should independently evaluate the suitability of and test each product selected for their own applications. Littelfuse products are
not designed for, and may not be used in, all applications. Read complete Disclaimer Notice at www.littelfuse.com/disclaimer-electronics.
6
© 2022 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: GD. 09/07/22
