HMD4M72D18G

HANBit HMD4M72D18G 32Mbyte(4Mx72) Fast Page Mode 4K Ref. 5V, DIMM 168 pin Part No. HMD4M72D18G GENERAL DESCRIPTION The HMD4M72D18G is a 4Mx72bits Dynamic RAM high density memory module. The HMD4M72D18G consists of eighteen CMOS 4Mx4bits DRAMs in SOJ/TSOPІІ 400mil packages mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The HMD4M72D18 is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets FEATURES w Part Identification HMD4M72D18G --- 4KCycles/64ms Ref, Gold Plate Lead -6 SPEED -5 PERFORMANCE RANGE tRAC 50ns 60ns tCAC 18ns 20ns tRC 90ns 110ns tHPC 35ns 40ns w High-density 32MByte design w New JEDEC standard proposal without buffer w CAS-before-RAS Refresh capability w RAS-only and Hidden refresh capability w Single +5± 0.5V power supply w Fast Page mode operation. w LVTTL compatible inputs and outputs w FR4-PCB design w Access times : 50, 60ns w Timing 50ns access 60ns access w Packages 168-pin DIMM D -5 -6 PIN NAMES Pin Name A0-A11 A0-A12 /W0,/W2 /OE0,/OE2 Function Address Input (4k ref) Address Input (8k ref) Read/Write Enable Output Enable Pin Name /RAS0, /RAS2 /CAS0 - /CAS7 SCL DU Function Row Address Strobe Column Address Strobe Serial Clock Don't use Pin Name Vss NC Vcc SDA Function Ground No Connection Power (+5V) Serial /Data I/O SA0 – SA2 Address in EEPROM CB0 - CB7 Check Bit DQ0-DQ63 Data In/Out Address URL:www.hbe.co.kr REV. 1.0 (August.2002) -1- HANBit Electronics Co.,Ltd. HANBit PIN ASSIGNMENT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 Vss NC NC Vcc /W0 /CAS0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol /CAS1 /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 NC Vcc Vcc NC Vss /OE2 /RAS2 /CAS2 /CAS3 /W2 Vcc NC NC CB2 CB3 Vss DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol DQ18 DQ19 Vcc DQ20 NC NC NC Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss NC NC NC SDA SCL Vcc PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Symbol Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 Vss NC NC Vcc NC /CAS4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 HMD4M72D18G Symbol /CAS5 /RAS1 NC Vss A1 A3 A5 A7 A9 A11 NC Vcc NC NC Vss NC /RAS3 /CAS6 /CAS7 NC Vcc NC NC CB6 CB7 Vss DQ48 DQ49 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol DQ50 DQ51 Vcc DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss NC NC SA0 SA1 SA2 Vcc URL:www.hbe.co.kr REV. 1.0 (August.2002) -2- HANBit Electronics Co.,Ltd. HANBit FUNCTIONAL BLOCK DIAGRAM CB0-7 DQ 0-63 /CAS /RAS0 HMD4M72D18G /OE0 /CAS /RAS /OE /W /CAS /RAS /OE /W DQ0-3 U1 A0 -A11 DQ4-7 /CAS4 /RAS2 /OE2 /CAS /RAS /OE /W /CAS /RAS /OE /W DQ32-35 U11 A0 -A11 DQ36-39 U2 A0 -A11 DQ8-11 /CAS5 U12 A0 -A11 DQ40-43 /CAS /CAS /RAS /OE /W /CAS /RAS /OE /W /CAS /RAS /OE /W U3 A0 -A11 DQ12-15 /CAS /RAS /OE /W /CAS /RAS /OE /W /CAS /RAS /OE /W U13 A0 -A11 DQ44-47 U4 A0 -A11 CB0-3 U14 A0 -A11 CB4-7 U5 A0 -A11 DQ16-19 /CAS6 U15 A0 -A11 DQ48-51 /CAS2 /CAS /RAS /OE /W /CAS /RAS /OE /W U6 A0 -A11 DQ20-23 /CAS /RAS /OE /W /CAS /RAS /OE /W U15 A0 -A11 DQ52-55 U7 A0 -A11 DQ24-27 /CAS7 U16 A0 -A11 DQ56-59 /CAS3 /CAS /RAS /OE /W /CAS /RAS /OE /W U8 A0 -A11 DQ28-31 /CAS /RAS /OE /W /CAS /RAS /OE /W U17 A0 -A11 DQ60-63 A0 -A11 /WE2 U9 A0 -A11 U18 /WE0 A(0:11) Vcc Vs 0.1uF or 0.22uF Capacitor for each DRAM To all DRAMs HANBit Electronics Co.,Ltd. URL:www.hbe.co.kr REV. 1.0 (August.2002) -3- HANBit HMD4M72D18G ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -0.5V to 4.6V -0.5V to 4.6V 18W -55oC to 150oC Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.. 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) HMD4M72D18EG (4K REF) SYMBOL SPEED MIN MAX ICC1 -5 -6 ICC2 ICC3 Don't care -5 -6 ICC4 -5 -6 ICC5 ICC6 Don't care -5 -6 Icc7 Iccs L L 1980 1800 18 1980 1800 1620 1440 9 1980 1800 4500 3600 UNITS mA mA MA mA mA mA mA MA mA mA µA µA ICC1 : Operating Current * (/RAS , /CAS , Address cycling @tRC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) URL:www.hbe.co.kr REV. 1.0 (August.2002) -4- HANBit Electronics Co.,Ltd. HANBit ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 4.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 3.3V VOH : Output High Voltage Level (IOH= -2mA ) VOL : Output Low Voltage Level (IOL = 2mA ) HMD4M72D18G * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE ( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1 MIN MAX 20 20 73 20 17 UNITS pF pF pF pF pF o DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W0,/W1,/OE0,/OE2) Input Capacitance (/RAS0,/RAS2) Input Capacitance (/CAS0-/CAS7) Input/Output Capacitance (DQ0-63) AC CHARACTERISTICS ( 0 C ≤ TA ≤ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 104 140 50 13 25 3 3 3 2 30 50 13 38 8 20 10K 37 10K 13 50 3 3 3 2 40 60 15 45 10 20 10K 45 10K 13 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 84 116 o STANDARD OPERATION Random read or write cycle time Read-modify-write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z /OE to output in Low-Z Output buffer turn-off delay from /CAS Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time URL:www.hbe.co.kr REV. 1.0 (August.2002) SYMBOL tRC tRWC tRAC tCAC tAA tCLZ tOLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD -5- HANBit Electronics Co.,Ltd. HANBit /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address hold referenced to /RAS Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS to /W delay time /RAS to /W delay time Column address to /W delay time /CAS precharge to /W delay time /CAS setup time (/CAS-before /RAS refresh) /CAS hold time(/CAS-before-/RAS refresh) /RAS to /CAS precharge time Access time from /CAS precharge Hyper page mode cycle time Hyper page mode read-modify write cycle time /CAS precharge time(Hyper page cycle) /RAS pulse width (Hyper page cycle) /RAS hold time from /CAS precharge /OE access time /OE to date delay Output buffer tune off delay time from /OE tCP tRASP tRHCP tOEA tOED tOEZ 13 3 13 8 50 30 13 15 3 200K 10 60 35 tCHR tRPC tCPA tHPC tHPRWC 20 47 10 5 28 25 56 10 5 tRAD tCRP tASR tRAH tASC tCAH tRRH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tRWD tAWD tCPWD tCSR 0 30 67 42 47 5 15 5 0 10 0 8 0 25 0 0 0 10 10 13 8 0 8 32 0 34 79 49 54 5 25 15 5 0 10 0 10 0 30 0 0 0 10 10 15 10 0 10 HMD4M72D18G 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32 ms ns ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns 15 ns URL:www.hbe.co.kr REV. 1.0 (August.2002) -6- HANBit Electronics Co.,Ltd. HANBit /OE command hold time Output data hold time Output buffer turn off delay from /RAS Output buffer turn off delay from /W /W to data delay /OE to /CAS hold time /CAS hold time to /OE /OE precharge time /W pulse width (Hyper page cycle) tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE 13 10 3 3 15 5 5 5 5 13 13 13 10 3 3 15 5 5 5 5 HMD4M72D18G ns ns 15 15 ns ns ns ns ns ns ns NOTES 1.An initial pause of 200µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.Input voltage levels are VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD ≥ tRCD(max) 6.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS ≥ tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle the data output will contain the data read from the selected address. If neither of the above conditions are satisfied, The condition of the data out is indeternimated. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA. 10. If /RAS goes to high before /CAS high going, the open circuit condition of the output is achieved by /CAS high going. If /Cas goes to high before /RAS high going, the open circuit condition of the output is achieved by /RAS high going. 11.tASC ≥ 6ns URL:www.hbe.co.kr REV. 1.0 (August.2002) -7- HANBit Electronics Co.,Ltd. HANBit TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE /RAS HMD4M72D18G /CAS A /W /OE DQ TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) /RAS /CAS A /W /OE DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) -8- HANBit Electronics Co.,Ltd. HANBit TIMING WAVEFORM OF WRITE CYCLE (/OE CONTROLLED WRITE) NOTE : Dout = OPEN HMD4M72D18G /RAS /CAS A /W /OE DQ READ MODIFY WRITE CYCLE /RAS /CAS A /W /OE DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) -9- HANBit Electronics Co.,Ltd. HANBit HYPER PAGE READ CYCLE HMD4M72D18G /RAS /CAS A /W /OE DQ HYPER PAGE WRITE CYCLE (EARLY WRITE) /RAS /CAS A /W /OE DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) - 10 - HANBit Electronics Co.,Ltd. HANBit HYPER PAGE READ MODIFY WRITE CYCLE /RAS HMD4M72D18G /CAS A /W /OE DQ HYPER PAGE READ AND WRITE MIXED CYCLE /RAS /CAS A /W /OE DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) - 11 - HANBit Electronics Co.,Ltd. HANBit /RAS ONLY REFRESH CYCLE NOTE: /W,/OE,Din = Don't care Dout = OPEN HMD4M72D18G /RAS /CAS A /CAS BEFORE /RAS REFRESH CYCLE NOTE: /OE, A = Don't care /RAS /CAS A DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) - 12 - HANBit Electronics Co.,Ltd. HANBit HIDDEN REFRESH CYCLE ( READ) HMD4M72D18G /RAS /CAS A /W /OE DQ HIDDEN REFRESH CYCLE ( WRITE ) NOTE: Dout = OPEN /RAS /CAS A /W /OE DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) - 13 - HANBit Electronics Co.,Ltd. HANBit /CAS BEFORE /RAS REFRESH COUNTER TEST CYCLE /RAS HMD4M72D18G /CAS A READ CYCLE /W /OE DQ WRITE CYCLE /W /OE DQ READ-MODIFY-WRITE /W /OE DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) - 14 - HANBit Electronics Co.,Ltd. HANBit /CAS BEFORE /RAS SELF REFRESH CYCLE NOTE : /OE, A = Don’ care t HMD4M72D18G /RAS /CAS DQ /W TEST MODE IN CYCLE NOTE: /OE, A = Don't care /RAS /CAS /W DQ URL:www.hbe.co.kr REV. 1.0 (August.2002) - 15 - HANBit Electronics Co.,Ltd. HANBit PACKAGING INFORMATION UNIT:mm HMD4M72D18G (FRONT VIEW) 3.69 mm MAX 0.25 mm MAX 2.54 mm MIN 1.27mm Gold : 1.00mm 1.27±0.1 mm ORDERING INFORMATION Part Number Density Org. Package Component Number 18EA 18EA Vcc MODE SPEED HMD4M72D18G-5 HMD4M72D18G-6 32MByte 32MByte x 72 x 72 168 Pin-DIMM 168 Pin-DIMM 5V 5V FP FP 50ns 60ns URL:www.hbe.co.kr REV. 1.0 (August.2002) - 16 - HANBit Electronics Co.,Ltd.