HMN88D-120I

HANBit HMN88D Non-Volatile SRAM MODULE 64Kbit (8K x 8-Bit),28Pin DIP, 5V Part No. HMN88D GENERAL DESCRIPTION The HMN88D Nonvolatile SRAM is a 65,536-bit static RAM organized as 8,192 bytes by 8 bits. The HMN88D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN88D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES w Access time : 85, 100, 120, 150 ns w High-density design : 64Kbit Design w Battery internally isolated until power is applied w Industry-standard 28-pin 8K x 8 pinout w Unlimited writes cycles w Data retention in the absence of VCC w 10-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss w Commercial temperature operation PIN ASSIGNMENT NC A12 A7 A6 A5 A4 A3 A2 A1 A0 D Q0 D Q1 D Q2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE NC A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 28-pin Encapsulated Package OPTIONS w Timing 85 ns 100 ns 120 ns 150 ns MARKING - 85 -100 -120 -150 URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 1 HANBit Electronics Co.,Ltd HANBit FUNCTIONAL DESCRIPTION HMN88D The HMN88D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A12) defines which of the 8,192 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN88D operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN88D acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN88D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (tW R) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge. The HMN88D provides full functional capability for VCC greater than 4.5 V and write protects by 4.37 V nominal. Powerdown/power-up control circuitry constantly monitors the VCC supply for a power-fail-detect threshold VPFD . W hen VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “ don’t care” and all outputs are high impedance. As VCC falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. BLOCK DIAGRAM /OE /WE 8K x 8 SRAM Block A0-A12 DQ0-DQ7 PIN DESCRIPTION A0-A12 : Address Input /CE : Chip Enable /CE VSS : Ground DQ0-DQ7 : Data In / Data Out Power /CE Power – Fail Control Lithium Cell VCC /WE : Write Enable /OE : Output Enable VCC: Power (+5V) NC : No Connection URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 2 HANBit Electronics Co.,Ltd HANBit TRUTH TABLE MODE Not selected Output disable Read W rite /OE X H L X /CE H L L L /WE X H H L I/O OPERATION High Z High Z DOUT DIN HMN88D POWER Standby Active Active Active ABSOLUTE MAXIMUM RATINGS PARAMETER DC voltage applied on VCC relative to VSS DC Voltage applied on any pin excluding VCC relative to VSS Operating temperature Storage temperature Temperature under bias Soldering temperature SYMBOL VCC VT TOPR TSTG TBIAS TSOLDER RATING -0.3V to 7.0V -0.3V to 7.0V 0 to 70°C -40°C to 70°C -10°C to 70°C 260°C For 10 second VT≤ VCC+0.3 CONDITIONS NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) PARAMETER Supply Voltage Ground Input high voltage Input low voltage SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.3 TYPICAL 5.0V 0 MAX 5.5V 0 VCC+0.3V 0.8V NOTE: Typical values indicate operation at TA = 25℃ URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 3 HANBit Electronics Co.,Ltd HANBit DC ELECTRICAL CHARACTERISTICS (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER Input Leakage Current Output Leakage Current Output high voltage Output low voltage Standby supply current Standby supply current CONDITIONS VIN=VSS to VCC /CE=VIH or /OE=VIH Or /WE=VIL IOH=-1.0mA IOL= 2.1mA /CE=VIH /CE≥ VCC-0.2V, 0V≤ VIN≤ 0.2V, or VIN≥ VCC-0.2V Operating supply current Power-fail-detect voltage Supply switch-over voltage Min.cycle,duty=100%, /CE=VIL, II/O=0㎃ ICC VPFD VSO 4.30 65 4.37 3 ISB1 2.5 SYMBOL ILI ILO VOH VOL ISB MIN 2.4 TYP. 4 HMN88D MAX ±1 ±1 0.4 2 100 UNIT mA mA V V ㎃ mA 15 4.50 - ㎃ V V CAPACITANCE (TA=25℃ , f=1MHz, VCC=5.0V) DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS Input voltage = 0V Output voltage = 0V SYMBOL CIN CI/O MAX 10 10 MIN UNIT pF pF CHARACTERISTICS (Test Conditions) PARAMETER Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) VALUE 0 to 3V 5 ns 1.5V (unless otherwise specified) See Figures 1and 2 1KΩ DOUT 1.9KΩ +5V DOUT 100㎊ +5V 1.9KΩ 5㎊ 1KΩ Figure 1. Output Load A Figure 2. Output Load B URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 4 HANBit Electronics Co.,Ltd HANBit READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER Read Cycle Time Address Access Time Chip enable access time Output enable to Output valid Chip enable to output in low Z Output enable to output in low Z Chip disable to output in high Z Output disable to output high Z Output hold from address change SYMBOL t RC tACC tACE t OE tCLZ tOLZ tCHZ tOHZ t OH Output load A Output load A Output load A Output load B Output load B Output load B Output load B Output load A CONDITIONS M IN 70 5 5 0 0 10 -70 M AX 70 70 35 25 25 M IN 85 5 0 0 0 10 -85 M AX 85 85 45 35 25 -120 M IN 120 5 0 0 0 10 M AX 120 120 60 45 35 - HMN88D -150 M IN 150 10 5 0 0 10 M AX 150 150 70 60 50 - UNIT ns ns ns ns ns ns ns ns ns WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax ) PARAMETER W rite Cycle Time Chip enable to end of write Address setup time Address valid to end of write W rite pulse width W rite recovery time (write cycle 1) W rite recovery time (write cycle 2) Data valid to end of write Data hold time (write cycle 1) Data hold time (write cycle 2) W rite enabled to output in high Z Output active from end of write SYMBOL tWC tCW tAS tAW tWP tWR1 tWR2 tDW tDH1 tDH2 tWZ tOW Note 4 Note 4 Note 5 Note 5 Note 1 Note 2 Note 1 Note 1 Note 3 Note 3 CONDITIONS M IN 70 65 0 65 55 5 15 30 0 10 0 5 -70 M AX 25 M IN 85 75 0 75 65 5 15 35 0 10 0 0 -85 M AX 30 -120 M IN 120 100 0 100 85 5 15 45 0 10 0 0 M AX 40 -150 M in 150 100 0 90 90 5 15 50 0 0 0 5 M ax 50 UNI T ns ns ns ns ns ns ns ns ns ns ns ns NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE going low and /WE going low. 3. Either tW R1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state. URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 5 HANBit Electronics Co.,Ltd HANBit POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V) PARAMETER VCC slew, 4.75 to 4.25V VCC slew, 4.75 to VSO VCC slew, VSO to VPFD (max) Chip enable recovery time Data-retention time in Absence of VCC Data-retention time in Absence of VCC W rite-protect time SYMBOL tPF tFS tPU Time during which SRAM tCER is write-protected after VCC passes VPFD on power-up. tDR tDR-N TA = 25℃ TA = 25℃ ; industrial temperature range (-N) only Delay after VCC slews down tW PT past VPFD before SRAM is Write-protected. 40 100 10 6 40 80 CONDITIONS MIN 300 10 0 TYP. - HMN88D MAX 120 UNIT ㎲ ㎲ ㎲ ms - years years 150 ㎲ TIMING WAVEFORM - READ CYCLE NO.1 (Address Access)* 1,2 tRC Address tACC tOH DOUT Previous Data Valid Data Valid - READ CYCLE NO.2 (/CE Access) /CE *1,3,4 tRC tACE tCLZ DOUT High-Z tCHZ High-Z URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 6 HANBit Electronics Co.,Ltd HANBit - READ CYCLE NO.3 (/OE Access) *1,5 HMN88D tRC Address tACC /OE tOE DOUT tOLZ High-Z tOHZ Data Valid High-Z NOTES: 1. /WE is held high for a read cycle. 2. Device is continuously selected: /CE = /OE =VIL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = VIL. 5. Device is continuously selected: /CE = VIL - WRITE CYCLE NO.1 (/WE-Controlled) *1,2,3 tWC Address tAW tCW /CE tAS /WE tDW DIN tWZ DOUT Data Undefined (1) Data-in Valid tOW High-Z tDH1 tWP tWR1 URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 7 HANBit Electronics Co.,Ltd HANBit - WRITE CYCLE NO.2 (/CE-Controlled) *1,2,3,4,5 HMN88D tWC Address tAS /CE t WP /WE tDW DIN tWZ DOUT Data Undefined (2) NOTE: 1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tW R2 must be met. 5. Either tDH1 or tDH2 must be met. tAW tCW tWR2 tDH2 Data-in Valid High-Z - POWER-DOWN/POWER-UP TIMING tPF VCC 4.75 VPFD VPFD 4.25 VSO tFS tWPT /CE tDR VSO tPU tCER URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 8 HANBit Electronics Co.,Ltd HANBit PACKAGE DIMENSION Dimension A B C D E F G H I J Min 1.470 0.710 0.365 0.012 0.008 0.590 0.017 0.090 0.075 0.120 Max 1.500 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150 HMN88D J A H G I B C D E F ORDERING INFORMATION H M N 8 8 D - 70 I Operating Temp. : Blank = Commercial (0 to 70 °C ) I = Industrial (-40 to 85°C) Speed options : 70 = 70 ns 85 = 85 ns 1 20 = 120 ns 1 50 = 150 ns Dip type package Device : 8K x 8 bit Nonvolatile T imekeeping SRAM HANBit Memory Module URL : www.hbe.co.kr Rev. 0.0 (April, 2002) 9 HANBit Electronics Co.,Ltd