HMS12832M4G-10

HANBit HMS12832M4G/Z4 SRAM MODULE 512KByte (128K x 32-Bit), 64PIN SIMM / ZIP Part No. HMS12832M4G, HMS12832Z4 GENERAL DESCRIPTION The HMS12832M4G/Z4 is a high-speed static random access memory (SRAM) module containing 131,072 words organized in a x32-bit configuration. The module consists of four 128K x 8 SRAMs mounted on a 64-pin, single-sided, FR4-printed circuit board. PD0 and PD1 identify the module’s density allowing interchangeable use of alternate density, industry- standard modules. Four chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes independently. Output enable(/OE) and write enable(/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible. Reading is FEATURES w Access times : 10, 12, 15 and 20ns w High-density 512KByte design w High-reliability, high-speed design w Single + 5V ±0.5V power supply w Easy memory expansion with /CE and /OE functions w All inputs and outputs are TTL-compatible w Industry-standard pinout w FR4-PCB design PIN 1 2 3 4 5 6 SYMBOL Vss NC NC DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 Vcc A0 A7 A1 A8 PIN 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SYMBOL A2 A9 DQ12 DQ4 DQ13 DQ5 DQ14 DQ6 DQ15 DQ7 Vss /WE A15 A14 /CE2 /CE1 PIN 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL /CE4 /CE3 NC A16 /OE Vss DQ24 DQ16 DQ25 DQ17 DQ26 DQ18 DQ27 DQ19 A3 A10 PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 SYMBOL A4 A11 A5 A12 Vcc A13 A6 DQ20 DQ28 DQ21 DQ29 DQ22 DQ30 DQ23 DQ31 Vss PIN ASSIGNMENT OPTIONS MARKING w Timing 8ns access 10ns access 12ns access 15ns access 20ns access w Packages 64-pin SIMM 64-pin ZIP M Z -8 -10 -12 -15 -20 7 8 9 10 11 12 13 14 15 16 SIMM TOP VIEW URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 1 HANBit Electronics Co.,Ltd. HANBit FUNCTIONAL BLOCK DIAGRAM 32 17 A0-16 /WE /OE /CE /CE1 A0-16 /WE /OE /CE /CE2 A0-16 /WE /OE /CE /CE3 A0-16 /WE /OE /WE /OE /CE /CE4 DQ24-31 DQ16-23 DQ 8-15 DQ 0-7 HMS12832M4G/Z4 DQ0 - DQ31 A0 - A16 U1 U2 U3 U4 PRESENCE-DETECT PD0 = Open PD1 = Open TRUTH TABLE MODE STANDBY NOT SELECTED READ WRITE /OE X H L X /CE H L L L /WE X H H L DQ HIGH-Z HIGH-Z Dout Din POWER STANDBY ACTIVE ACTIVE ACTIVE URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 2 HANBit Electronics Co.,Ltd. HANBit ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature Operating Temperature SYMBOL VIN,OUT VCC PD TSTG TA HMS12832M4G/Z4 RATING -0.5V to Vcc+0.5V -0.5V to +7.0V 4.0W oC to +150oC -65 0oC to +70oC w Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.5* TYP. 5.0V 0 MAX 5.5V 0 Vcc+0.5V** 0.8V VIL(Min.) = -2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA ** VIH(Min.) = Vcc+2.0V ac (Pulse Width ≤ 10ns) for I ≤ 20 mA DC AND OPERATING CHARACTERISTICS (1)(0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 10% ) PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=5.0V, Temp=25 oC TEST CONDITIONS VIN=Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0mA IOL = 8.0mA SYMBOL ILI IL0 VOH VOL MIN -8 -8 2.4 0.4 MAX 8 8 UNITS µA µA V V DC AND OPERATING CHARACTERISTICS (2) DESCRIPTION TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CE=VIH f=0MHZ, /CE≥VCC-0.2V, VIN≥ VCC-0.2V or VIN≤0.2V ISB ISB1 120 20 120 20 120 20 mA mA ICC 300 292 280 mA SYMBOL MAX -12 -15 -20 UNIT Power Supply Current:Operating Power Supply Current:Standby URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 3 HANBit Electronics Co.,Ltd. HANBit HMS12832M4G/Z4 CAPACITANCE (TA =25 oC , f= 1.0Mhz) DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN MAX 32 24 UNIT pF pF * NOTE : Capacitance is sampled and not 100% tested AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V, unless otherwise specified) Test conditions PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load VALUE 0V to 3V 3ns 1.5V See below Output Load (A) Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ VL=1.5V 50Ω DOUT Z0=50Ω 30pF DOUT 353Ω +3.3V 319Ω 5pF* READ CYCLE -12 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change Chip Select to Power Up Time Chip Select to Power Down Time SYMBOL MIN tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH tPU tPD 0 3 0 0 3 0 12 6 6 12 12 12 6 0 3 0 0 3 0 15 7 7 MAX MIN 15 15 15 7 0 3 0 0 3 0 20 9 9 MAX MIN 20 20 20 9 MAX ns ns ns ns ns ns ns ns ns ns ns -15 -20 UNIT URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 4 HANBit Electronics Co.,Ltd. HANBit HMS12832M4G/Z4 WRITE CYCLE PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z SYMBOL tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW -12 MIN 12 8 0 8 8 0 0 6 0 3 6 MAX MIN 15 10 0 9 9 0 0 7 0 3 7 -15 MAX MIN 20 12 0 10 10 0 0 8 0 3 9 -20 MAX UNIT ns ns ns ns ns ns ns ns ns ns URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 5 HANBit Electronics Co.,Ltd. HANBit TIMING DIAGRAMS HMS12832M4G/Z4 NOTES(READ CYCLE) 1. 2. 3. 4. 5. 6. 7. 8. WE is high for read cycle. All read cycle timing is referenced from the last valid address to the first transition address. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. Device is continuously selected with CS=VIL. Address valid prior to coincident with CS transition low. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 6 HANBit Electronics Co.,Ltd. HANBit HMS12832M4G/Z4 URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 7 HANBit Electronics Co.,Ltd. HANBit HMS12832M4G/Z4 NOTES(WRITE CYCLE) 1. 2. ll write cycle timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. 4. 5. 6. 7. 8. 9. tCW is measured from the later of CS going low to end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. Dout is the read data of the new address. not be applied. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should FUNCTIONAL DESCRIPTION /CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT l SB, l SB1 lCC lCC lCC Note: X means Don't Care URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 8 HANBit Electronics Co.,Ltd. HANBit HMS12832M4G/Z4 PACKAGING INFORMATION UNIT : mm SIMM Design 0.25 mm MAX 2.54 mm MIN 1.27 Gold : 1.04±0.10 mm Solder : 0.914±0.10 mm 1.27±0.08 mm (Solder & Gold Plating Lead) URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 9 HANBit Electronics Co.,Ltd. HANBit ZIP Design < FRONT SIDE> HMS12832M4G/Z4 1.27 ± 0.20 1.7±0.30 mm 2.54 mm URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 10 HANBit Electronics Co.,Ltd. HANBit HMS12832M4G/Z4 ORDERING INFORMATION Component Number 4EA 4EA 4EA 4EA 4EA 4EA 4EA 4EA Part Number Density Org. Package Vcc Access Time HMS12832M4G-10 HMS12832M4G-12 HMS12832M4G-15 HMS12832M4G-20 HMS12832Z4-10 HMS12832Z4-12 HMS12832Z4-15 HMS12832Z4-20 512KByte 512KByte 512KByte 512KByte 512KByte 512KByte 512KByte 512KByte 128KX 32bit 128KX 32bit 128KX 32bit 128KX 32bit 128KX 32bit 128KX 32bit 128KX 32bit 128KX 32bit 64 Pin-SIMM 64 Pin-SIMM 64 Pin-SIMM 64 Pin-SIMM 64 Pin-ZIP 64 Pin-ZIP 64 Pin-ZIP 64 Pin-ZIP 5V 5V 5V 5V 5V 5V 5V 5V 10ns 12ns 15ns 20ns 10ns 12ns 15ns 20ns URL: www.hbe.co.kr Rev. 1.0 (September / 2002) 11 HANBit Electronics Co.,Ltd.