CA1391E

CA1391, CA1394 May 1999 UCT OBSOLETE PROD REPLACEMENT NO RECOMMENDED ns 1-800-442-7747 Call Central Applicatio harris.com or email: centapp@ TV Horizontal Processors [ /Title (CA13 91, CA139 4) /Subject (TV Horizontal Processors) /Autho r () /Keywords (Harris Semiconductor, TV horizontal processor, horizontal oscillator, horizontal driver, phase detector, AFC circuit, AGC circuit, Features • CA1391E - Positive Horizontal Sawtooth Input • CA1394E - Negative Horizontal Sawtooth Input • Internal Shunt Regulator • Linear Balanced Phase Detector • Preset Hold Control Capability • Pull-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±300Hz (Typ) • Low Thermal Frequency Drift • Small Static Phase Error • Variable Output Duty Cycle • Adjustable DC Loop Gain Description The Harris CA1391E and CA1394E are monolithic integrated circuits designed for use in the low-level horizontal section of monochrome or color television receivers. Functions include a phase detector, an oscillator, a regulator, and a pre-driver. The CA1391E and CA1394E are electrically equivalent and pin compatible with industry types 1391 and 1394 in similar packages. Part Number Information PART NUMBER CA1391E CA1394E TEMP. RANGE (oC) 0 to 85 0 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP PKG. NO. E8.3 E8.3 Pinout CA1391, CA1394 (PDIP) TOP VIEW MARKSPACE RATIO OSC 7 TIMING 8 6 V+ PHASE 5 DETECT OUT Functional Diagram PHASE DETECTOR OUTPUT 5 OSCILLATOR TIMING 7 V+ 6 OUT GND SYNC IN HORIZ IN 1 2 3 4 PHASE DETECTOR OUT OSCILLATOR MARK-SPACE RATIO REGULATOR 8 4 HORIZONTAL SAWTOOTH INPUT PHASE DETECTOR PREDRIVER 1 OUTPUT 3 SYNC INPUT 2 GROUND CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 File Number 981.4 8-9 CA1391, CA1394 Absolute Maximum Ratings DC Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA DC Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Sync Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5VP-P Sawtooth Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5VP-P Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Supply Voltage (See Figure 1) TEST CONDITIONS TEMP. (oC) 25 MIN 8 TYP MAX 9 UNITS V S1, S5, S6 = 2; S2, S3, S4, S7, S8 = 1 Measure Terminal 6 to GND S1, S5, S6 = 2; S2, S3, S4, S7, S8 = 1 Counter to Terminal 1 S2, S3, S6, S8 = 1; S1, S4, S5, S7 = 2 Measure Terminal 1 to 25V S2, S3, S5, S6, S8 = 1; S1, S4, S7 = 2 Measure Terminal 1 to GND S2, S5, S6, S8 = 1; S1, S3, S4, S7 = 2 Measure Terminal 3 to GND S5, S8 = 1; S1, S2, S3, S4, S6, S7 = 2 Measure Terminal 5 to +4V S1, S5, S8 = 1; S2, S3, S4, S6, S7 = 2 Measure Terminal 5 to +4V S1, S5, S6, S8 = 1; S2, S3, S4, S7 = 2 Measure Terminal 5 to +4V Free Running Frequency -1% Output Leakage 25 14734 - 16734 Hz 25 - 10 - mV Output Saturation 25 - 60 - mV Phase Detector Bias 25 - 1.9 - V Phase Detector Leak 25 -2 - 2 mV Phase Detector Low 25 -0.55 (Note 2) +0.55 (Note 2) -100 0.3 - - - V Phase Detector High 25 - - V Phase Detector Balance VDET2 + VDET3 Sync Diode Static Phase Error Oscillator Pull In Range Oscillator Hold In Range NOTE: 2. Polarity reversed in the CA1391. S1, S2, S3, S4, S6, S7 = 1; S5, S8 = 2 See Figure 3 25 25 25 0.5 ±300 ±900 100 1.2 - mV V µs Hz Hz 8-10 CA1391, CA1394 Test Circuit +25V 620Ω 1W 1kΩ 1 14kΩ S3 430Ω 2 S5 1.5kΩ 1 S4 8 7 CA1391/CA1394 1 2 S8 2.65kΩ 1 2 5.6kΩ +6V 1 3 S1 2 1 4 S2 2 6 5 21 S6 1 150kΩ 1µF 6800pF 1 2 S7 150Ω 2 1.65kΩ 100Ω 2 150Ω +6V 200Ω FIGURE 1. DC TEST CIRCUIT Schematic Diagram PREDRIVER OSC. TIMING 7 OSCILLATOR R8 3.9K R1 2.6K Q6 R12 2.4K R16 1.1K R18 200 Q15 Z2 V+ 6 REGULATOR PHASE DETECTOR R31 560 R24 40K Q16 R29 1.5K R30 1.5K Q20 Q21 5 PHASE DET. OUT CA1394E 4 MARKSPACE RATIO 8 Q3 OUT 1 Q1 Q2 R15 2.4K Q4 R4 430 R3 7.5K Q5 R6 400 R5 5.1K R2 6.8K 2 GND R7 1.8K Q9 R10 470 Q10 Q7 Q8 R9 1.3K R14 6.8K Q11 R13 1.5K Z1 R1 3K Q19 Q14 Q12 R22 Q13 3.3K R20 820 R23 6.8K R25 7.5K R26 Q22 Q23 HORIZ INPUT 4 CA1391E R17 6.2K 7.5K Q18 Q17 R27 510 D1 R11 3.6K R19 240 D2 R28 910 3 SYNC INPUT NOTE: All resistances are in ohms. 8-11 CA1391, CA1394 Application Information Circuit Operation (See Schematic Diagram) The CA1391 and CA1394 contain the oscillator, phase detector, and predriver sections necessary for the television horizontal oscillator and AFC loop. The oscillator is an RC type with Terminal 7 used to control the timing. If it is assumed that Q7 is initially off, then an external capacitor connected from Terminal 7 to ground charges through an external resistance connected between Terminals 6 and 7. As soon as the voltage at Terminal 7 exceeds the potential set at the base of Q8 by resistors R11 and R12, Q7 turns on, and Q6 supplies base current to Q5 and Q10. Transistor Q5 discharges the capacitor through R4 until the base bias of Q7 falls below that of Q8 at which time, Q7 turns off, and the cycle repeats. The sawtooth generated at the base of Q4 appears across R3 and turns off Q3 whenever the sawtooth voltage rises to a value that exceeds the bias set at Terminal 8. By adjusting the potential at Terminal 8, the duty cycle at the pre-drive output (Terminal 1) may be changed. The phase detector is isolated from the remainder of the circuit by R31, Z2, Q15 and Q16. The phase detector consists of the comparator Q22 and Q23, and the gated current source Q18. Negative going sync pulses at Terminal 3 turn off Q17, and the current division between Q22 and Q23 is then determined by the phase relationship of the sync and the sawtooth waveform at Terminal 4, which is derived from the horizontal flyback pulse. If there is no phase difference between the sync and sawtooth, equal currents flow in the collectors of Q22 and Q23 during each half of the sync pulse period. The current in Q22 is turned around by current mirror Q20 and Q21 so that there is no net output current at Terminal 5 for balanced conditions. When a phase offset occurs, current flows either in or out of Terminal 5. In circuit applications, this terminal is connected to Terminal 7 through an external low pass filter, thereby controlling the oscillator. Shunt regulation for the circuit is obtained by using a VBE and zener multiplier. Resistors R13 and R14 multiply the VBE of Q11, and the ratio of R15 and R16 multiplies the voltage of the zener diode Z1. TA = 25oC FREE RUNNING FREQUENCY = 15734Hz VOLTAGE AT TERM. 8 (THROUGH 1kΩ) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 10 20 30 40 50 60 70 POSITIVE PULSE WIDTH AT TERMINAL 1 (µs) FIGURE 2. DUTY CYCLE AT THE PRE-DRIVE OUTPUT (TERMINAL 1) AS IT IS AFFECTED BY THE INPUT AT TERMINAL 8 V+ 24V 3kΩ 620Ω 6800pF +150V 4kΩ 10W 2.4kΩ 2 2.7kΩ 120kΩ 14kΩ 470µF 0.47µF 8.2kΩ 0.001µF 1.5kΩ 150kΩ 8 7 CA1394 1 2 3 470pF 4 6 5 0.01µF 22Ω 270Ω 7.5kΩ 0.0027µF SYNC 1.2kΩ 20VP-P 5µs 60VP-P 10µs 0.1µF 390kΩ 0.1µF 3.9kΩ FIGURE 3. TYPICAL CIRCUIT APPLICATION 8-12