CD22102

Semiconductor CD22101, CD22102 x 4 x 2 Crosspoint Switch with Control Memory CD22101 and CD22102 crosspoint switches consist of 4 x 4 x 2 arrays of crosspoints (transmission gates) with a 4-line to 16-line decoder and 16 latch circuits. Any one of the sixteen crosspoint pairs can be selected by applying the appropriate four-line address, corresponding crosspoints in each array are turned on and off simultaneously. Any number of crosspoints can be turned on simultaneously. In the CD22101, the selected crosspoint pair can be turned on or off by applying a logic ONE or ZERO, respectively, to the data input, and applying a ONE to the strobe input. When the device is “powered up”, the states of the 16 switches are indeterminate. Therefore, all switches must be turned off by putting the strobe high, data-in low, and then addressing all switches in succession. The selected pair of crosspoints in the CD22102 is turned on by applying a logic ONE to the KA (set) input while a logic ZERO is on the KB input, and turned off by applying a logic ONE to the KB (reset) input while a logic ZERO is on the KA input. In this respect, the control latches of the CD22102 are similar to SET/RESET flip-flops. They differ, however, in that the simultaneous application of ONEs to the KA and KB inputs turns off (resets) all crosspoints. All crosspoints in both devices must be turned off as VDD is applied. February 1999 Features [ /Title (CD22 101, CD221 02) /Subject (CMO S4x4 x2 Crosspoint Switch with Control Memory) / Author () /Keywords (Harris Semiconductor, Telecom, SLICs, SLACs , Telephone, Telephony, WLL, Wireless T CMOS 4 E PRODUC NT OBSOLET PLACEME DED RE MEN 42-7747 NO RECOM ons 1-800-4 al Applicati @harris.com Call Centr entapp or email: c Description • Low ON Resistance . . . . . . . . . . . . 75Ω (Typ) at VDD = 12V • “Built - In” Latched Inputs • Large Analog Signal Capability . . . . . . . . . . . . . . . ±VDD/2 • Switch Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . 10MHz • Matched Switch Characteristics ∆RON = 8Ω (Typ) at VDD = 12V • High Linearity - 0.25% Distortion (Typ) at f = 1kHz, VIN = 5VP-P, VDD - VSS = 10V, and RL = 1kΩ • Standard CMOS Noise Immunity Applications • Telephone Systems • PBX • Studio Audio Switching • Multisystem Bus Interconnect Ordering Information PART NUMBER CD22101E CD22101F CD22102E TEMP. RANGE (oC) -40 to 85 -55 to 125 -40 to 85 PACKAGE 24 Ld PDIP 24 Ld CERDIP 24 Ld PDIP PKG. NO. E24.6 F24.6 E24.6 Pinouts CD22101 (PDIP, SBDIP) TOP VIEW B1 C2 X2' 3 Y1' 4 Y2' 5 X4' 6 X3' 7 Y4' 8 Y3' 9 X1' 10 D 11 VSS 12 24 VDD 23 A 22 X2 21 Y1 20 Y2 19 X4 18 X3 17 Y4 16 Y3 15 X1 14 DATA 13 STROBE B1 C 2 Functional Diagram CD22102 (PDIP) TOP VIEW 24 VDD 22 X2 21 Y1 20 Y2 19 X4 18 X3 17 Y4 16 Y3 15 X1 14 KA 13 KB IN (OUT) 16 ADDRESS 23 A DECODER LATCH 16 CONTROL IN (OUT) 16 4X4 SWITCH OUT (IN) X2' 3 Y1' 4 Y2' 5 X4' 6 X3' 7 Y4' 8 Y3' 9 X1' 10 D 11 VSS 12 4X4 SWITCH OUT (IN) CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1999 File Number 2871.3 4-193 CD22101, CD22102 Absolute Maximum Ratings Supply Voltage (VDD) (Referenced to VSS Terminal) . . . .-0.5 to 20V Input Voltage (All Inputs) . . . . . . . . . . . . . . . . . . . -0.5 to VDD +0.5V Supply Voltage Range For TA = Full Package Temperature Range . . . . . . . . . . . . . . 3V to 18V Input Current (Any One Input) (Note 1) . . . . . . . . . . . . . . . . . . . ±10mA Power Dissipation For TA = -40oC to 60oC (Package Type E) . . . . . . . . . . . . 500mW For TA = 60oC to 85oC Package Type E) . . . . . . . . Derate Linearly 12mW/oC to 200mW For TA = -55oC to 100oC (Package Type D, F) . . . . . . . . . 500mW For TA = 100oC to 125oC (Package Type D, F) . . . . . Derate Linearly 12mW/oC to 200mW Device Dissipation per Output Transistor For TA = Full Package Temperature Range (All Types) . . . . . 100mW Thermal Information Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . -65oC ≤ TA ≤ 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range Package Type D, F. . . . . . . . . . . . . . . . . . . . . -55oC ≤ TA ≤ 125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . -40oC ≤ TA ≤ 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications Values at -55oC, 25oC, 125oC Apply to D, F, H Packages Values at -40oC, 25oC, 85oC Apply to E Package TEST CONDITIONS -55oC MAX -40oC MAX 85oC MAX 125oC MAX MIN 25oC TYP MAX UNITS µA µA µA µA Ω Ω Ω Ω Ω Ω Ω Ω nA PARAMETER SYMBOL FIGURE VDD(V) STATIC CROSSPOINTS Quiescent Device Current IDD (Max) 1 1 1 1 On Resistance RON (Max) Any Switch VIS = 0 to VDD 14 15 16 ∆ON Resistance ∆RON Between Any Two Switches 5 10 15 20 5 10 12 15 5 10 12 15 OFF Leakage Current STATIC CONTROLS Input Low Voltage VIL (Max) OFF Switch IL < 0.2µA 5 10 15 Input High Voltage VIH (Min) ON Switch See RON Characteristic 5 10 15 Input Current NOTES: 1. Maximum current through transmission gates (switches) = 25mA. 2. Determined by minimum feasible leakage measurement for automatic testing. IIN (Max) Any Control VIN = 0, 18V 2 18 ±0.1 ±0.1 1.5 3 4 3.5 7 11 ±1 ±1 3.5 7 11 ±10-5 1.5 3 4 ±0.1 V V V V V V µA IL (Max) All Switches OFF, VIS = 18V 4 18 5 10 20 100 475 135 100 70 5 10 20 100 500 145 110 75 ±1000 150 300 600 3000 725 205 155 110 150 300 600 3000 800 230 175 125 0.04 0.04 0.04 0.08 225 85 75 65 25 10 8 5 ±1 5 10 20 100 600 180 135 95 ±100 (Note 2) 4-194 CD22101, CD22102 Electrical Specifications TA = 25oC TEST CONDITIONS fIS (kHz) RL (kΩ) VIS (V) (Note 3) VDD (V) PARAMETER DYNAMIC CROSSPOINTS Propagation Delay Time, (Switch ON) Signal Input to Output SYMBOL FIGURE MIN TYP MAX UNITS tPHL, tPLH 5 - 10 5 10 15 5 10 15 - 30 15 10 60 30 20 ns ns ns CL = 50pF; tR , tF = 20ns Frequency Response (Any Switch ON) f3dB 19 1 1 5 10 40 MHz V OS Sine Wave Input, 20log ----------- = -3dB V IS THD 1 1 1 1 1 1 0.6 2.5 5 7.5 2 (Note 4) 5 10 15 10 1 0.25 0.15 -96 % % % dB Sine Wave Response (Distortion) Feedthrough (All Switches OFF) FDT 13 1.6 Sine Wave Input Frequency for Signal Crosstalk Attenuation of 40dB Attenuation of 95dB Capacitance: XN to Ground YN to Ground Feedthrough DYNAMIC CONTROLS Propagation Delay Time: High Impedance to High Level or Low Level Strobe to Output, CD22101 tPZH, tPZL 6 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 500 1000 ns CIOS CIS 25 60 0.6 pF pF pF Sine Wave Input FCT 12 0.6 1 (Note 4) 10 2.5 0.1 MHz kHz 10 15 - 230 170 515 220 170 500 215 160 480 225 155 460 340 1000 440 340 1000 430 320 960 450 300 ns ns ns ns ns ns ns ns ns ns ns Data-In to Output, CD22101 tPZH, tPZL 7 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 KA to Output, CD22102 tPZH, tPZL - RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Address to Output CD22101, CD22102 tPZH, tPZL 8 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 4-195 CD22101, CD22102 Electrical Specifications TA = 25oC (Continued) TEST CONDITIONS fIS (kHz) RL (kΩ) VIS (V) (Note 3) VDD (V) 5 10 15 KB to Output, CD22102 tPHZ, tPLZ RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Data-In to Output, CD22101 tPHZ, tPLZ RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 KA • KB to Output, CD22102 tPHZ, tPLZ RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Address to Output CD22101, CD22102 tPHZ, tPLZ 8 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Minimum Strobe Pulse Width, CD22101 tW 6 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Address to Strobe Setup or Hold Times, CD22101 tSU, tH 9 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Strobe to Data-In Hold Time, CD22101 tHHL, tHLH 10 RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Address to KA and KB Setup or Hold Times, CD22102 tSU, tH RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Minimum KA • KB Pulse Width, CD22102 tW RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 Minimum KA Pulse Width, CD22102 tW RL = 1kΩ, CL = 50pF, tR, tF = 20ns 5 10 15 PARAMETER Propagation Delay Time: High Level or Low Level to High Impedance Strobe to Output, CD22101 SYMBOL tPHZ, tPLZ FIGURE 6 MIN - TYP 450 200 135 450 200 130 450 165 110 280 130 90 425 190 130 260 120 80 -160 -70 -50 200 80 60 -160 -70 -50 375 160 110 425 175 120 MAX 900 400 270 900 400 260 900 330 220 560 260 180 850 380 260 500 240 160 0 0 0 400 160 120 0 0 0 750 320 220 850 350 240 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RL = 1kΩ, CL = 50pF, tR, tF = 20ns 4-196 CD22101, CD22102 Electrical Specifications TA = 25oC (Continued) TEST CONDITIONS fIS (kHz) RL (kΩ) VIS (V) (Note 3) VDD (V) 5 10 15 Control Crosstalk, Data-In, Address or Strobe to Output 11 100 10 5 PARAMETER Minimum KB Pulse Width, CD22102 SYMBOL tW FIGURE - MIN - TYP 200 90 70 75 MAX 400 180 140 - UNITS ns ns ns mVPEAK RL = 1kΩ, CL = 50pF, tR, tF = 20ns Square Wave Input = 5V, tR, tF = 20ns, RS = 1kΩ Input Capacitance NOTES: CIN Any Control Input 5 7.5 pF V DD 3. Peak-to-peak voltage symmetrical about ----------- , unless otherwise specified. 2 4. RMS. Functional Block Diagram CD22102 ONLY KB CD22101 ONLY STROBE (NOTE) 13 23 A (NOTE) DECODER 1 B (NOTE) ADDRESS 2 C (NOTE) 11 D (NOTE) 15 16 16 X1 22 X2 18 X3 19 X4 LATCHES DATA (NOTE) 14 16 8 9 10 11 4 5 6 7 KA 0 1 2 3 21 Y1 Y2 20 SIGNALS OUT (IN) Y3 16 Y4 17 12 13 14 15 SIGNALS IN (OUT) Y1’ 4 16 0’ 1’ 2’ 3’ Y2’ 5 VDD 4’ 5’ 6’ 7’ Y3’ 9 NOTE: INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK 8’ 9’ 10’ 11’ Y4’ 8 12’ 10 VSS 13’ 3 14’ 7 15’ 6 X4’ SIGNALS OUT (IN) X1’ X2’ X3’ SIGNALS IN (OUT) 4-197 CD22101, CD22102 Schematic Diagram (NOTE) STROBE 13 (NOTE) DATA IN 14 21 TO X1’ Y1’ 24 VDD A B C 23 A (NOTE) A TO 15 OTHER NANDS A D DQ 0 1 2 3 TG 4 5 6 7 TG DQ 8 9 10 11 TG 12 13 14 15 15 X1 10 X1’ 22 18 X2 3 X2’ X3 7 X3’ 19 X4 6 X4’ TG TG TG TG TG TG TG TG TG Y1 TG TG TG TG ( Y1’ ) 4 ø ø LATCH TO 15 OTHER LATCHS 20 Y2 ( Y2’ ) 5 16 Y3 1 B (NOTE) B B KA (SET) (NOTE) 14 KB (RESET) (NOTE) 13 A B C D CD22101 ( Y3’ ) 9 ø ø 17 Y4 ( Y4’ ) 8 2 C (NOTE) C C TO 15 OTHER NANDS D D D R 11 (NOTE) ( TO 15 OTHER LATCHES ) ( ) ( ) ( ) DETAIL OF TRANSMISSION GATES VDD IN VDD 12 VSS CD22102 VDD DETAIL OF LATCHES ø D p n Q NOTE: INPUTS PROTECTED BY COS/MOS PROTECTION NETWORK ø ø p n VSS Q OUT ø VSS DECODER TRUTH TABLE ADDRESS A 0 1 0 1 0 1 0 1 B 0 0 1 1 0 0 1 1 C 0 0 0 0 1 1 1 1 D 0 0 0 0 0 0 0 0 SELECT X1Y1 and X1’Y1’ X2Y1 and X2’Y1’ X3Y1 and X3’Y1’ X4Y1 and X4’Y1’ X1Y2 and X1’Y2’ X2Y2 and X2’Y2’ X3Y2 and X3’Y2’ X4Y2 and X4’Y2’ A 0 1 0 1 0 1 0 1 ADDRESS B 0 0 1 1 0 0 1 1 C 0 0 0 0 1 1 1 1 D 1 1 1 1 1 1 1 1 SELECT X1Y3 and X1’Y3’ X2Y3 and X2’Y3’ X3Y3 and X3’Y3’ X4Y3 and X4’Y3’ X1Y4 and X1’Y4’ X2Y4 and X2’Y4’ X3Y4 and X3’Y4’ X4Y4 and X4’Y4’ 4-198 CD22101, CD22102 CONTROL TRUTH TABLE FOR CD22101 ADDRESS FUNCTION Switch ON Switch OFF No Change 1 = High Level A 1 1 X B 1 1 X C 1 1 X D 1 1 X STROBE 1 1 0 DATA 1 0 X X = Don’t Care SELECT 15 (X4Y4) and 15’ (X4’Y4’) 15 (X4Y4) and 15’ (X4’Y4’) XXXX 0 = Low Level CONTROL TRUTH TABLE FOR CD22102 ADDRESS FUNCTION Switch ON Switch OFF All Switches OFF (Note 5) No Change 1 = High Level NOTE: 5. In the event that KA and KB are changed from levels 1, 1 to 0, 0 KB should not be allowed to go to 0 before KA, otherwise a switch which was off will inadvertently be turned on. A 1 1 X X B 1 1 X X C 1 1 X X D 1 1 X X KA 1 0 1 0 KB 0 1 1 0 X = Don’t Care SELECT 15 (X4Y4) and 15’ (X4’Y4’) 15 (X4Y4) and 15’ (X4’Y4’) All XXXX 0 = Low Level Metallization Mask Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). 4-199 CD22101, CD22102 Test Circuits and Waveforms VDD VDD VDD VDD 1 2 VSS 3 4 5 6 7 8 9 10 11 12 VSS MEASURE INPUTS SEQUENTIALLY TO BOTH VDD AND VSS CONNECT ALL UNUSED INPUTS TO EITHER VDD OR VSS 24 23 22 21 20 19 18 17 16 15 14 13 VSS VSS IDD II 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FIGURE 1. QUIESCENT CURRENT TEST CIRCUIT VDD 0.1µF 500µF ID FIGURE 2. INPUT CURRENT TEST CIRCUIT Q1 CD4029 CLK CLK Q2 Q3 Q4 2kΩ Q2 Q3 CL 1 2 3 4 5 CL 6 7 8 9 CL 10 11 12 24 S 23 22 21 20 19 18 17 16 15 14 13 CL CL 2kΩ Q1 POWER DISSIPATION PER PACKAGE (µW) CL 105 TA = 25oC VDD = 15V 10V 10V CL CL 104 103 5V 102 CL = 50pF CL = 15pF 10 102 103 104 105 106 107 SWITCHING FREQUENCY (Hz) Q4 2kΩ VSS 2kΩ CLOSE SWITCH S AFTER APPLYING VDD FIGURE 3. DYNAMIC POWER DISSIPATION TEST CIRCUIT FOR CD22101AND TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF SWITCHING FREQUENCY 4-200 CD22101, CD22102 Test Circuits and Waveforms VDD ON IL VIS SW 10kΩ VOS 50pF (Continued) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SW = ANY CROSSPOINT STROBE = DATA - IN = VDD VDD VIS 50% 0 tPLH VDD VOS 50% 0 tPHL 50% 50% VSS FIGURE 4. OFF SWITCH INPUT OR OUTPUT LEAKAGE CURRENT TEST CIRCUIT (16 OF 32 SWITCHES) FIGURE 5. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (SIGNAL INPUT TO SIGNAL OUTPUT, SWITCH ON) tW DATA-IN STROBE VDD VIS SW 1kΩ SW = ANY CROSSPOINT VOS 50pF VOS 0 tPHZ DATA-IN STROBE VDD 50% 0 tS VDD 0 tH 50% tW 50% tS 50% tH tPZH VDD 90% 10% FIGURE 6. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (STROBE TO SIGNAL OUTPUT, SWITCH TURN-ON OR TURN-OFF) 4-201 CD22101, CD22102 Test Circuits and Waveforms (Continued) DATA-IN VDD VDD VIS SW 1kΩ SW = ANY CROSSPOINT STROBE = VDD VOS VDD 50pF VOS 0 10% DATA-IN 0 tPZH VIS SW 50% VDD VDD DATA-IN 1kΩ VOS 50pF 0 tPZL VDD VOS 0 90% 50% FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (DATA-IN TO SIGNAL OUTPUT, SWITCH TURN-ON TO HIGH OR LOW LEVEL) VDD ADDRESS = 0 ADDRESS = 1 ADDRESS 0 tS VDD VIS SW VOS1 VIS VDD DATA-IN SW VOS2 0 tH VDD 50% 50% 50% tPHZ VDD VOS1 1kΩ 50pF 1kΩ 50pF VOS2 0 0 VDD SW = ANY CROSSPOINT STROBE = VDD 90% tPZH 10% FIGURE 8. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (ADDRESS TO SIGNAL OUTPUT, SWITCH TURN-ON OR TURN-OFF) 4-202 CD22101, CD22102 Test Circuits and Waveforms (Continued) STROBE 50% DATA tSU 50% ADDRESS tH DATA-IN tHLH STROBE 1µs 1µs tHHL 50% tHLH 50% 1µs OUTPUT OF SWITCH ADDRESSED Y2 IF SETUP AND HOLD TIMES PROVIDED ARE TOO SHORT, AN UNADDRESSED SWITCH MAY BE TURNED ON OR OFF SIMULTANEOUSLY WITH THE ADDRESSED SWITCH SET ALL SWITCHES TO OFF INITIALLY APPLY VDD TO ALL X INPUTS AND RETURN ALL Y OUTPUTS TO VSS THROUGH 1kΩ. ADDRESS X1Y2 (ABCD) WITH fIN = 10kHz FIGURE 9. ADDRESS TO STROBE SETUP AND HOLD TIMES FIGURE 10. STROBE TO DATA-IN HOLD TIME tH, FOR CD22101 CONTROLS VDD X (N) 1kΩ SW Y (N) 10kΩ VOS SW = ANY CROSSPOINT 75mV 0 CONTROL 0 5µs FIGURE 11. TEST CIRCUIT AND WAVEFORMS FOR CROSSTALK (CONTROL INPUT TO SIGNAL OUTPUT) -140 -120 dB TA = 25oC RS = 600Ω RL = 600Ω VIS = 1VRMS V OS 20 log --------V IS ON VIS 600Ω SW 600Ω 600Ω SW = ANY CROSSPOINT OFF SW VOS 600Ω = -100 -80 VDD = 5V -60 10V -40 -20 0 102 15V CROSSTALK 103 104 105 106 107 INPUT SIGNAL FREQUENCY (Hz) FIGURE 12. TEST CIRCUIT AND TYPICAL CROSSTALK AS A FUNCTION OF FREQUENCY BETWEEN SWITCH CIRCUITS IN THE SAME PACKAGE 4-203 CD22101, CD22102 Test Circuits and Waveforms (Continued) TA = 25oC RS = 600Ω RL = 600Ω 7.5V, -7.5V, 3VRMS 5V, -5V, 2VRMS -140 VIS 600Ω ANY OFF SWITCH VOS 600Ω = V OS 20 log --------V IS FEEDTHROUGH dB -120 -100 -80 -60 -40 -20 102 VDD = 2.5V, VSS = -2.5V VIS = 1VRMS V OS ISOLATION (dB) = 20 LOG --------V IS 103 104 105 106 107 INPUT SIGNAL FREQUENCY (Hz) FIGURE 13. TEST CIRCUIT AND TYPICAL FEEDTHROUGH AS A FUNCTION OF FREQUENCY (ANY OFF SWITCH) Typical Performance Curves VDD = 2.5V, VSS = -2.5V 350 SWITCH “ON” RESISTANCE (Ω) SWITCH “ON” RESISTANCE (Ω) 300 250 200 150 100 50 0 -2 -1 0 INPUT SIGNAL (V) 1 2 TA = 125oC 25oC -55oC 0 -4 -2 0 INPUT SIGNAL (V) 2 4 175 150 125 100 TA = 125oC 75 25oC 50 -55oC 25 VDD = 5V, VSS = -5V FIGURE 14. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT VDD = -VSS = 2.5V FIGURE 15. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT VDD = -VSS = 5V 4-204 Typical Performance Curves 100 VDD = 7.5V, VSS = -7.5V SWITCH “ON” RESISTANCE (Ω) (Continued) 400 TA = 25oC SWITCH “ON” RESISTANCE (Ω) TA = 125oC 350 300 250 200 150 100 ±5V 50 0 ±7.5V VDD = 2.5V, VSS = -2.5V 75 25oC 50 -55oC 25 0 -10 -8 -6 -4 -2 0 2 4 6 8 10 INPUT SIGNAL (V) -10 -5 0 INPUT SIGNAL (V) 5 10 FIGURE 16. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT VDD = -VSS = 7.5V FIGURE 17. TYPICAL ON RESISTANCE AS A FUNCTION OF INPUT SIGNAL VOLTAGE AT TA = 25oC TA = 25oC CL = 15pF VDATA-IN = 5V RL = 1MΩ 2 1.5 10kΩ 1 0.5 0 105 106 107 108 INPUT SIGNAL FREQUENCY (Hz) 1kΩ RF VOLTMETER BOONTON RADIO MODEL 91-CA OR EQUIV. fIS VIS SW RL CL VDD = 5V, VSS = -5V VDD = 10V TA = 25oC 10 OUTPUT VOLTAGE (V) OUTPUT SIGNAL (VOS) RMS (V) RL = 1MΩ, 100kΩ, 10kΩ 8 STROBE = VDD 6 4 2 500Ω VIS DATA-IN = VDD SW VOS RL VSS 0 2 4 6 8 10 1kΩ 2.5 VIS = 5VP-P = SINE WAVE 1.77VRMS CIOS = 0.4pF VOS (RMS) INPUT VOLTAGE (V) FIGURE 18. TYPICAL SWITCH ON TRANSFER CHARACTERISTICS (1 OF 16 SWITCHES) FIGURE 19. TYPICAL SWITCH ON FREQUENCY RESPONSE CHARACTERISTICS 4-205