CD4070B

Semiconductor CD4070B, CD4077B CMOS Quad Exclusive-OR and Exclusive-NOR Gate Description The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent Exclusive-NOR gates. The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively. June 1998 Features • High-Voltage Types (20V Rating) • CD4070B - Quad Exclusive-OR Gate • CD4077B - Quad Exclusive-NOR Gate • Medium Speed Operation - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF • 100% Tested for Quiescent Current at 20V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range - 100nA at 18V and 25oC • Noise Margin (Over Full Package Temperature Range) - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices Ordering Information PART NUMBER CD4070BE CD4077BE CD4070BF CD4077BF CD4070BM CD4077BM TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld PDIP 14 Ld PDIP 14 Ld CERDIP 14 Ld CERDIP 14 Ld SOIC 14 Ld SOIC PKG. NO. E14.3 E14.3 F14.3 F14.3 M14.15 M14.15 Applications • Logical Comparators • Adders/Subtractors • Parity Generators and Checkers Pinouts CD4070B (PDIP, CERDIP, SOIC) TOP VIEW CD4077B (PDIP, CERDIP, SOIC) TOP VIEW A1 B2 J=A⊕B 3 K=C⊕D 4 C5 D6 VSS 7 14 VDD 13 H 12 G 11 M = G ⊕ H 10 L = E ⊕ F 9F 8E A1 B2 J=A⊕B 3 K=C⊕D 4 C5 D6 VSS 7 14 VDD 13 H 12 G 11 M = G ⊕ H 10 L = E ⊕ F 9F 8E CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 910.1 1 CD4070B, CD4077B Functional Diagrams CD4070B 1 2 5 6 8 9 12 13 10 4 CD4077B 1 2 5 6 8 9 12 13 10 4 A J=A⊕B K=C⊕D M=G⊕ H L=E⊕F B C D E F G H 3 J J =A K K=C A B 3 J ⊕B ⊕D C D E F G H K L M=G L VSS = 7 VDD = 14 ⊕H =E⊕F L 11 M 11 M VDD VDD VDD VDD B† 2(5,9,12) p p n VSS VDD A† 1(6,8,13) p n VSS VDD VSS VSS VDD VSS n p p p n n J 3(4,10,11) A† 1(6,8,13) B† 2(5,9,12) p n VSS VDD p n n n n p n p J 3(4,10,11) p † INPUTS PROTECTED BY CMOS PROTECTION NETWORK † INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B (1 OF 4 IDENTICAL GATES) FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B (1 OF 4 IDENTICAL GATES) CD4070B TRUTH TABLE (1 OF 4 GATES) A 0 1 0 1 NOTE: 1 = High Level 0 = Low Level J=A⊕B B 0 0 1 1 J 0 1 1 0 CD4077B TRUTH TABLE (1 OF 4 GATES) A 0 1 0 1 NOTE: 1 = High Level 0 = Low Level J=A⊕B B 0 0 1 1 J 1 0 0 1 2 CD4070B, CD4077B Typical Performance Curves TA = 25oC (Continued) tPHL, tPLH, PROPAGATION DELAY TIME (ns) tTHL, tTLH, TRANSITION TIME (ns) TA = 25oC 300 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 50 0 0 20 40 60 80 100 110 CL, LOAD CAPACITANCE (pF) 200 SUPPLY VOLTAGE (VDD) = 5V 10V 15V 100 10V 15V 0 0 20 40 60 80 100 CL, LOAD CAPACITANCE (pF) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE tPHL, tPLH, PROPAGATION DELAY TIME (ns) FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE 105 PD, POWER DISSIPATION (µW) 104 103 102 10 1 10-1 10-1 TA = 25oC LOAD CAPACITANCE CL = 50pF 300 TA = 25oC 200 SU P GE TA OL YV PL (V D D )= 15 V 10V CL = 50pF 10V CL = 15pF 5V 100 0 0 5 10 15 20 VDD, SUPPLY VOLTAGE (V) 1 102 103 10 fI, INPUT FREQUENCY (kHz) 104 FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF SUPPLY VOLTAGE FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 5 CD4070B, CD4077B Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E A A1 A2 B B1 C D D1 E -C- eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 6 CD4070B, CD4077B Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 7