CD4541BH

Semiconductor CD4541B CMOS Programmable Timer High Voltage Types (20V Rating) Description CD4541B programmable timer consists of a 16-stage binary counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on reset circuit, and output control logic. The counter increments on positive-edge clock transitions and can also be reset via the MASTER RESET input. The output from this timer is the Q or Q output from the 8th, 10th, 13th, or 16th counter stage. The desired stage is chosen using time-select inputs A and B (see Frequency Select Table). The output is available in either of two modes selectable via the MODE input, pin 10 (see Truth Table). When this MODE input is a logic “1”, the output will be a continuous square wave having a frequency equal to the oscillator frequency divided by 2N. With the MODE input set to logic “0” and after a MASTER RESET is initiated, the output (assuming Q output has been selected) changes from a low to a high state after 2N-1 counts and remains in that state until another MASTER RESET pulse is applied or the MODE input is set to a logic “1”. Timing is initialized by setting the AUTO RESET input (pin 5) to logic “0” and turning power on. If pin 5 is set to logic “1”, the AUTO RESET circuit is disabled and counting will not start until after a positive MASTER RESET pulse is applied and returns to a low level. The AUTO RESET consumes an appreciable amount of power and should not be used if low-power operation is desired. For reliable automatic power-on reset, VDD should be greater than 5V. The RC oscillator, shown in Figure 2, oscillates with a frequency determined by the RC network and is calculated using: 1 f = ---------------------------------2.3 R TC C TC Where f is between 1kHz and 100kHz and R S ≥ 10k Ω and ≈ 2R TC July 1998 Features • Low Symmetrical Output Resistance, Typically 100Ω at VDD = 15V • Built-In Low-Power RC Oscillator • Oscillator Frequency Range . . . . . . . . . . DC to 100kHz • External Clock (Applied to Pin 3) can be Used Instead of Oscillator • Operates as 2N Frequency Divider or as a SingleTransition Timer • Q/Q Select Provides Output Logic Level Flexibility • AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation • Operates With Very Slow Clock Rise and Fall Times • Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range • Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V, and 15V Parametric Ratings • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Ordering Information PART NUMBER CD4541BF CD4541BE CD4541BH CD4541BM TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld PDIP Chip 14 Ld SOIC PKG. NO. F14.3 E14.3 M14.15 Pinout CD4541B (CERDIP, PDIP, SOIC) TOP VIEW RTC 1 CTC 2 RS 3 NC 4 AUTO RESET 5 MASTER RESET 6 VSS 7 14 VDD 13 B 12 A 11 NC 10 MODE 9 Q/Q SELECT 8 OUTPUT CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 1378.1 1 CD4541B Functional Diagram 12 A 13 B 1 RTC 2 CTC 3 RS 5 AR 6 MR 10 MODE 9 Q/ Q SELECT 8 Q VDD = PIN 14 VSS = PIN 7 Functional Block Diagram 12 13 †A †B R N P 1 OF 3 MUX 216 OR 28 8 Q N P 3 9 †Q/ Q SELECT †RS 2 210 213 OSC 8-STAGE COUNTER R R †CTC †RTC 1 8-STAGE COUNTER R 10 †MODE VDD AUTO RESET† 5 PWR ON RESET 6 VDD = 14 VSS = 7 NC = 4, 11 VSS † All inputs are protected by CMOS Protection Network. MANUAL RESET† FIGURE 1. FREQUENCY SELECTION TABLE A 0 0 1 1 B 0 1 0 1 NO. OF STAGES N 13 10 8 16 TRUTH TABLE STATE PIN 5 6 9 10 0 Auto Reset On Master Reset Off Output Initially Low After Reset (Q) Single Transition Mode 1 Auto Reset Disable Master Reset On Output Initially High After Reset (Q) Recycle Mode FIGURE 2. RC OSCILLATOR CIRCUIT RTC 1 COUNT 2N 8192 1024 256 65536 RS INTERNAL RESET CTC 2 3 TO CLOCK CKT 2 CD4541B Absolute Maximum Ratings DC Supply - Voltage Range, VDD Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to +20V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA Device Dissipation Per Output Transistor For TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Thermal Information Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package . . . . . . . . . . . . . . . . 90 36 SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) At Distance 1/16in ± 1/32in (1.59mm ± 0.79mm) from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range For TA = Full Package Temperature Range . . . . . 3V (Min), 18V (Typ) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC) 25 PARAMETER Quiescent Device Current, (Note 2) IDD (Max) VO (V) Output Low (Sink) Current lOL (Min) 0.4 0.5 1.5 Output High (Source) Current, IOH (Min) 4.6 2.5 9.5 13.5 Output Voltage: Low-Level, VOL (Max) Output Voltage: High-Level, VOH (Min) Input Low Voltage, VIL (Max) 0.5, 4.5 1, 9 1.5, 13.5 VIN (V) 0, 5 0, 10 0, 15 0, 20 0, 5 0, 10 0, 15 0, 5 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 VDD (V) 5 10 15 20 5 10 15 5 5 10 15 5 10 15 5 10 15 5 10 15 -55 5 10 20 100 1.9 5 12.6 -1.9 -6.2 -5 -12.6 -40 5 10 20 100 1.85 4.8 12 -1.85 -6 -4.8 -12 85 150 300 600 3000 1.26 3.3 8.4 -1.26 -4.1 -3.3 -8.4 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3 4 125 150 300 600 3000 1.08 2.8 7.2 -1.08 -3 -2.8 -7.2 MIN 1.55 4 10 -1.55 -5 -4 -10 4.95 9.95 14.95 TYP 0.04 0.04 0.04 0.08 3.1 8 20 -3.1 -10 -8 -20 0 0 0 5 10 15 MAX 5 10 20 100 0.05 0.05 0.05 1.5 3 4 UNITS µA µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA mA V V V 3 CD4541B Electrical Specifications (Continued) CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC) 25 PARAMETER Input High Voltage, VIH (Min) VO (V) 0.5, 4.5 1, 9 1.5, 13.5 Input Current, lIN (Max) NOTE: 2. With AUTO RESET enabled, additional current drain at 25oC is: 7µA (Typ), 200µA (Max) at 5V; 30µA (Typ), 350µA (Max) at 10V; 80µA (Typ), 500µA (Max) at 15V VIN (V) 0, 18 VDD (V) 5 10 15 18 -55 ±0.1 ±0.1 -40 85 3.5 7 11 ±1 ±1 125 MIN 3.5 7 11 TYP ±10-5 MAX ±0.1 UNITS V V V µA Dynamic Electrical Specifications PARAMETER Propagation Delay Times Clock to Q TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ VDD (V) 5 10 15 MIN 900 300 225 TYP 3.5 1.25 0.9 6.0 3.5 2.5 100 50 40 180 90 65 300 100 85 1.5 4 6 Unlimited MAX 10.5 3.8 2.9 18 10 7.5 200 100 80 360 180 130 UNITS µs µs µs µs µs µs ns ns ns ns ns ns ns ns ns MHz MHz MHz µs SYMBOL (28) tPHL , tPLH (216) tPHL , tPLH 5 10 15 Transition Time tTHL 5 10 15 tTHL 5 10 15 MASTER RESET, CLOCK Pulse Width 5 10 15 Maximum Clock Pulse Input Frequency fCL 5 10 15 Maximum Clock Pulse Input Rise or Fall time t r , tf 5, 10, 15 4 CD4541B Digital Timer Application A positive pulse on MASTER RESET resets the counters and latch. The output goes high and remains high until the number of pulses, selected by A and B, are counted. This circuit is retriggerable and is as accurate as the input frequency. If additional accuracy is desired, an external clock can be used on pin 3. A setup time equal to the width of the one-shot output is required immediately following initial power up, during which time the output will be high. VDD 1 CTC RS INPUT AR MR 2 3 4 5 6 7 14 13 12 11 10 9 8 B A 82 80 70 60 50 40 30 RTC 20 10 0 4 - 10 (0.102 - 0.254) OUTPUT t 85 - 93 (2.159 - 2.362) 79 - 87 (2.007 - 2.210) 0 10 20 30 40 50 60 70 80 88 FIGURE 3. DIGITAL TIMER APPLICATION CIRCUIT NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). FIGURE 4. DIMENSIONS AND PAD LAYOUT FOR CD4541B 5 CD4541B Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E E14.3 (JEDEC MS-001-AA ISSUE D) 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93 -C- A2 B B1 C D D1 E E1 e eA eB L N eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 14 2.93 6 CD4541B Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 α eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. α aaa bbb ccc M N 7 CD4541B Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M14.15 (JEDEC MS-012-AB ISSUE C) 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574 A1 B C D E α A1 0.10(0.004) C e B 0.25(0.010) M C AM BS e H h L N 0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 8