HMP8112

Semiconductor N FOR DED 8115 N MME ee HMP ECO S R NOT March 1998 E ES WD IGN S HMP8112 NTSC/PAL Video Decoder Features • Supports ITU-R BT.601 (CCIR601) and Square Pixel • 3 Composite Analog Inputs with Sync Tip AGC, Black Clamping and White Peak Control • Patented Decoding Scheme with Improved 2-Line Comb Filter, Y/C Separation • NTSC M, N, and PAL (B, D, G, H, I, M, N, CN) Operation • Composite or S-Video Input • User-Selectable Color Trap and Low Pass Video Filters • User Selectable Hue, Saturation, Contrast, Sharpness, and Brightness Controls • User Selectable Data Transfer Output Modes - 16-Bit 4:2:2 YCbCr - 8-Bit 4:2:2 YCbCr • User Selectable Clock Range from 20MHz - 30MHz • I2C Interface • VMI Compatible Video Data Bus Description The HMP8112 is a high quality, digital video, color decoder with internal A/D converters. The A/D function includes a 3:1 analog input mux, Sync Tip AGC, Black clamping and two 8-bit A/D Converters. The high quality A/D converters minimize pixel jitter and crosstalk. The decoder function is compatible with NTSC M, PAL B, D, G, H, I, M, N and special combination PAL N video standards. Both composite (CVBS) and S-Video (Y/C) input formats are supported. A 2 line comb filter plus a user selectable Chrominance trap filter provide high quality Y/C separation. Various adjustments are available to optimize the image such as Brightness, Contrast, Saturation, Hue and Sharpness controls. Video synchronization is achieved with a 4xfSC chroma burst lock PLL for color demodulation and line lock PLL for correct pixel alignment. A chrominance subsampling 4:2:2 scheme is provided to reduce chrominance bandwidth. The HMP8112 is ideally suited as the analog video interface to VCR’s and camera’s in any multimedia or video system. The high quality Y/C separation, user flexibility and integrated phase locked loops are ideal for use with today’s powerful compression processors. The HMP8112 operates from a single 5V supply and is TTL/CMOS compatible. Applications • Multimedia PCs • Video Conferencing • Video Editing • Video Security Systems • Settop Boxes (Cable, Satellite, and Telco) • Digital VCRs • Related Products - NTSC/PAL Encoders: HMP8154, HMP8156, HMP8171, HMP8173 - NTSC/PAL Decoders: HMP8115 Ordering Information PART NUMBER HMP8112CN HMP8112EVAL2 HMP8156EVAL2 TEMP. RANGE (oC) 0 to 70 PACKAGE 80 Ld PQFP † PKG.NO. Q80.14x20 PCI Reference Design (Includes Part) Frame Grabber Evaluation Board (Includes Part) † PQFP is also known as QFP and MQFP Table of Contents Page Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Operation Introduction. . . . . . . . . . . . . . . . . . . 6 Internal Register Description Tables . . . . . . . . . . . . . . . . . 14 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC and DC Electrical Specifications . . . . . . . . . . . . . . . . . 24 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . 27 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 File Number 4221.3 1 COMP_FILTER COMP_A/D_IN VID_IN0 + 8-BIT ADC VID_IN1 INPUT MUX Functional Block Diagrams VID_IN2/Y DIGITAL COMPARATORS Y/C SEPARATION COLOR TRAP WHITE PEAK LEVEL BLACK LEVEL SYNC LEVEL CLAMP_CAP USER ADJUST. ACTIVE DVLD OUTPUT SAMPLE RATE CONVERTER Y[7:0] AGC_CAP AGC AND CLAMP LOGIC COLOR DEMODULATION INPUT SAMPLE RATE CONVERTER COLOR ADJUST CbCr[7:0] HMP8112 2 DIGITAL COMPARATOR CLAMP CHROMA PLL VSYNC DETECT + 8-BIT ADC STD_ERR GAIN_CTRL CR_CLAMP_CAP CLAMP LOGIC AND GAIN CONTROL HSYNC DETECT SCL LINE LOCK PLL MICROPROCESSOR INTERFACE AND CONTROL SDA CHROMA_IN LOCKED FIELD VSYNC HSYNC RESET HMP8112 Functional Block Diagrams GAIN_CTRL (Continued) CCLAMP_CAP CLAMP LOGIC AND GAIN CONTROL DIGITAL COMPARATOR CLAMP EXTERNAL ANTIALIASING FILTER CIN3 + EXTERNAL ANTIALIASING FILTER 8-BIT ADC C CR[7:0] SOURCE SELECT L_OUT L_ADIN LIN0 LIN1 LIN2 INPUT MUX + 8-BIT ADC Y, CVBS L[7:0] DIGITAL COMPARATORS LCLAMP_CAP SYNC LEVEL AGC AND CLAMP LOGIC BLACK LEVEL WHITE PEAK LEVEL LAGC_CAP WHITE PEAK ENABLE (WPE) VIDEO INPUT 3 CLK (20MHz - 30MHZ) VSYNC DETECT HUE ADJUST FIELD VSYNC STANDARD ERROR Functional Block Diagrams HSYNC HSYNC DETECT 4FSC CLOCK CHROMA PLL NCO CHROMA PLL LOOP FILTER CHROMA PHASE DETECTOR (Continued) CLK TO 4FSC RATIO AGC ADJUST SATURATION ADJUST C DATA LINE DELAY COMB FILTER CHROMA DEMODULATOR UV UV AGC SATURATION ADJUST Y DATA CHROMA TRAP U,V U,V TO CbCr COLOR SPACE CONVERTER AND COLOR KILLER C,CVBS DATA LP FILTER LINE LOCKED PLL LOOP FILTER ISL LINE LOCKED NCO LOCKED HMP8112 VIDEO DECODER 4 HORIZONTAL M Y DATA AND VERTICAL Y DATA U SHARPNESS X ADJUST ISL SHARPNESS ADJUST CHROMA TRAP ENABLE CR[7:0] C M U X C,CVBS DATA CbCr DATA INPUT SAMPLE RATE CONVERTER LOW PASS FILTER ENABLE OUTPUT SAMPLE RATE CONVERTER Y,CVBS Y DATA L[7:0] Y SYNC DATA STRIPPER, BRIGHTNESS, & CONTRAST ADJUST STANDARD SELECT HMP8112 Functional Block Diagrams (Continued) CONTROL REGISTERS ADDRESS POINTER OEN 0 1 ADDRESS POINTER .... .... .... .... . . . . 25 CbCr[7:0] 8/16 OUTPUT SELECT 32 X 16 DEEP FIFO Y[7:0] M U X CONTROL DATA BUS R E G I S T E R CbCr[7:0] 8 SERIAL SHIFT REGISTER R E G I S T E R Y[7:0] 8 DVLD A0 SCL SDA ACTIVE I2C CONTROL INTERFACE OUTPUT INTERFACE Schematic U1 LUMA0 LUMA1 LUMA2 R3 75 R4 75 R5 75 C4 1.0µF C5 1.0µF C3 1.0µF 5 6 7 LIN2 LIN1 LIN0 CRCB7 CRCB6 CRCB5 CRCB4 CRCB3 CRCB2 CRCB1 CRCB0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 ACTIVE DVLD 51 50 49 48 47 45 43 42 64 63 60 58 57 56 55 54 65 66 CR_CB7 CR_CB6 CR_CB5 CR_CB4 CR_CB3 CR_CB2 CR_CB1 CR_CB0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 CR_CB10. .71 CR_CB10. .71 LOW PASS FILTER 19 CIN Y10. .71 Y10. .71 CHROMA R6 75 C6 1.0µF R7 680 C2 15pF L1 82µH C1 15pF 9 8 R8 5.62K 77 76 VCC VCC VCC VCC VCC VCC VCC R17 4K L_OUT L_ADIN R11 10K R12 10K R13 10K R14 10K R15 10K R16 4K ACTIVE DVLD FIELD HDRIVE VDRIVE C9 0.22µF C8 0.01µF AVCC R1 1K C10 0.1µF R9 5K C7 0.01µF C11 0.1µF 67 FIELD LCLAMP_CAP 71 29 HSYNC CCLAMP_CAP 70 VSYNC 27 WPE 34 RESET 28 40 GAIN_CNTL SDA 41 SCL 38 78 CLK DEC_T 13 CLK 30 36 DEC_L TEST C12 0.1µF R18 10 LAGC_CAP RESET SDA SCL 27MHz 27MHz R10 50 C13 15pF VCC R2 10K JP1 JUMPER 5 HMP8112 Introduction The HMP8112 is an NTSC/PAL compatible Video Decoder with both chroma burst and line locked digital phase locked loops. The HMP8112 contains two 8-bit A/D converters and an I2C port for programming internal registers. Analog Video/Mux Inputs The Luminance channel has three analog video inputs that can be used for composite or the Y input of a S-Video signal, and one analog input for chrominance. LIN2 is used with CIN to interface an S-Video input. Three composite or two composite and one S-Video inputs can be applied to the HMP8112 at any one time. Control of the analog front end is selected by bits 2 and 1 of the Video Input Control Register. Anti-Aliasing Filter An external anti-alias filter is required to achieve optimum performance and prevent high frequency components from being aliased back into the video image. For the LIN inputs a single filter is connected to L_OUT and L_ADIN. For CIN the anti-aliasing filter should be connected to the CIN input. A recommended filter is shown below. L_OUT (PIN 9) 680Ω 15pF 82µH 15pF L_ADIN (PIN 8) 5.62kΩ ming registers. The DC RESTORE pulse can be programmed with the DC RESTORE Start and End time control registers. DC RESTORE should be asserted 6.5µs after the falling edge of horizontal sync (0HSYNC) and held for a duration of 2µs. Both HAGC and DC RESTORE are synchronous to the output sample rate (OSR) converter and are clocked in OSR (pixel clock) clock periods. The OSR clock rate is dependent on the input standard used. See Table 1 for the register values used for the different video standards. TABLE 1. HAGC AND DC RESTORE VALUES VIDEO OUTPUT STANDARD Square Pixel NTSC 640x480 CCIR601 NTSC 720x480 CCIR601 PAL 720X512 Square Pixel PAL 768X512 HAGC START/END VALUES 02F8/0008H DC RESTORE START/END VALUES 0028/0040H HSYNC START/END VALUES 0020/0050H 033F/0000H 033F/0000H 0037/0052H 0037/0052H 033B/0060H 033B/0060H 03A0/0018H 0040/0054H 0020/0070H White Peak Enable AGND LOW PASS FILTER CHROMA IN 75Ω 1.0µF CIN (PIN 19) The white peak enable input, (WPE) enables or disables the white peak control. Enabled, (logic high) when the digital outputs exceed code 248, the AGC will reduce the gain of the video amplifier to prevent over-ranging the A/D. If disabled, the AGC operates normally, keeping the horizontal sync tip at code 0 and allowing the A/D’s range to go to 255 at the maximum peak input. NTSC/PAL Decoder The NTSC/PAL decoder is designed to convert incoming Composite or Separated (SVHS, Y/C) video into it’s YCbCr component parts. The digital phase locked loops are designed to synchronize to the various NTSC/PAL standards. They provide a stable internal 4xfSC (Frequency of the Color Sub-Carrier) video clock for color demodulation, and a line locked clock for vertical spatial pixel alignment. The decoder uses the CLK to run the A/D converters and the phase locked loops. This asynchronous master clock for the decoder eliminates the need for a unique clock source in a Multimedia application. CLK can run from 20MHz to 30MHz when using the 16-bit Synchronous Data output Mode. The user must program the CLK to Color Sub-Carrier Ratio to match the CLK frequency used (see Internal Phase Locked Loops discussion). When using the 8-bit Burst Data Output Mode the CLK should be a 24.5454MHz, 27MHz or 29.5MHz depending on the output video standard chosen. The crystal oscillator must have a ±50ppm accuracy and a 60/40% duty cycle symmetry to ensure proper operation. Since the video data from the external A/D’s are sampled at the CLK frequency a sample rate converter is employed to convert the data from the CLK rate to the FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER AGC And Clamp Circuit Inputs LIN0-2 contain a sync tip AGC amplifier. During the sync tip the value of the A/D is driven to code 0 by gaining up the video input signal. The sync tip AGC is sampled during the HAGC pulse time which is controlled by the HAGC Pulse Start Time and End Time registers. The LIN0-2 inputs apply a DC clamp reference to the back porch of the video. This is controlled by the DC-RESTORE Pulse Start Time and End Time Registers. After a RESET, a change of the video standard, or a PLL Chrominance Subcarrier Ratio Register load, HAGC and DC RESTORE are overlapped, until LOCKED is asserted. (the PLL has acquired a stable line lock). This is the acquisition mode of the PLL where the decoder is trying to lock to a new video source. Once the PLL is LOCKED, HAGC and DC RESTORE are moved out to the default programmed values in the user programming registers. The HAGC should be set coincident to the incoming horizontal sync signal. The HAGC pulse should be set to a width of 2µs. Once the PLL is locked the DC RESTORE signal is moved out to the default programmed values in the user program- 6 HMP8112 internal decoding frequency of 4xfSC. 0HSYNC 0HSYNC VIDEO INPUT VIDEO INPUT 6.5µs DC RESTORE DC RESTORE START TIME HAGC HAGC tPW = 2.0µs OVERLAPPED CONTROL START TIME END TIME END TIME FIGURE 2A. PLL ACQUISITION MODE FIGURE 2B. PLL LOCKED MODE The input sample rate converter will interpolate between existing CLK samples to create the chroma locked (4xfSC) samples needed for the color decoder. An interpolation is done to create the 4xfSC pixel and a correction factor is then applied.. INCOMING VIDEO SAMPLES TIME chrominance information at half line intervals throughout the NTSC video spectrum. Therefore, NTSC has 227.5 cycles of chrominance per NTSC line. The half of a cycle causes the next reference burst to be 180o out of phase with the previous line’s burst. The two line comb efficiently removes the chrominance information from the baseband luminance signal. When decoding NTSC, the decoder maintains full luminance bandwidth horizontally throughout the chrominance carrier frequency range. Unlike most 2 line comb filter separation techniques, vertical bandwidth is maintained by means of a proprietary transform technique. Y I, Q Y RESAMPLED VIDEO AMPLITUDE TIME fH/2 4xfSC fH/2 FIGURE 3. SAMPLE RATE CONVERSION fH FREQUENCY Y I, Q Y The decoder can be used with the following video sources: Analog Composite - NTSC M, - PAL B, D, G, H, I, N And Special Combination PAL N Analog S - VHS (Y/C) - NTSC M, PAL B, D, G, H, I, N And Special Combination PAL N AMPLITUDE FREQUENCY Color Separation, And Demodulation To separate the chrominance modulated color information from the baseband luminance signal, a 2 line comb filter is employed. In NTSC signals the color information changes phase 180o from one line to the next. This interleaves the FIGURE 4. COMPOSITE NTSC INTERLEAVE SCHEME For PAL systems there are 283.75 cycles of chrominance per line. Chrominance information is spaced at quarter line intervals with a reference phase of 135o. The reference 7 HMP8112 phase alternates from line to line by 90o. To fully separate the PAL chrominance and luminance signals the user selectable filters should be enabled. The chroma notch filter built into the luminance channel should be enabled for PAL systems to reduce cross luminance effects. The low pass filter in the chrominance processing chain helps to reduce cross color products. pin. This signal follows the horizontal sync of an input video source. If there is no source the HSYNC pin will continue to run at video rates due to the Line Locked PLL free-running. HSYNC can be moved throughout the video line using the HSYNC Start and End time registers. This 10-bit register allows the HSYNC to be moved in OSR clock increments (12.27MHZ, 13.5MHz or 14.75MHz). Y I, Q I, Q Y Vertical Sync And Field Detection The vertical sync and field detect circuit of the decoder uses a low time counter to detect the vertical sync sequence in the video data stream. The low time counter accumulates the low time encounted after the horizontal sync edge or at the start of each line. When the low time count exceeds the vertical sync detect threshold, VSYNC is asserted immediately. VSYNC will remain asserted for a minimum of 1 line. The FIELD flag is updated at the same time as the VSYNC line. The FIELD pin is a ‘0’ for ODD fields and a ‘1’ for even fields. AMPLITUDE fH/4 fH FREQUENCY Y fH/4 I, Q I, Q Y AMPLITUDE In the case of lost vertical sync or excessive noise that would prevent the detection of vertical sync, the FIELD flag will continue to toggle. Lost vertical sync is declared if after 337 lines a vertical sync period was not detected for 3 successive lines. When this occurs the phase locked loops are initialized to the acquisition state. The VSYNC pulse out of the decoder follows the vertical sync detection and is typically 6.5 lines long. The VSYNC will run at the field rate of the selected video standard selected. For NTSC the field rate is 60Hz and for PAL the field rate is 50Hz. This signal will continue to run even in the event of no incoming video signal. FREQUENCY FIGURE 5. COMPOSITE PAL INTERLEAVE SCHEME The demodulator in the decoder decodes the color components into U and V. The U and V components are converted to Cb and Cr components after the decoding process. YCbCr has a usable data range as shown in Figure 4. The data range for Y is limited to a minimum of 16. 255 248 WHITE 100% 255 240 212 128 128 44 16 16 0 YELLOW 75% YELLOW 100% BLUE 100% BLUE 75% 255 240 212 128 44 16 0 CYAN 75% CYAN 100% RED 100% RED 75% Internal Phase Locked Loops The HMP8112 has two independent digital phase locked loops on chip. A chroma phase-locked loop is implemented to maintain chroma lock for demodulation of the color channel, and a line locked phase lock loop is implemented to maintain vertical spatial alignment. The phase locked loops are designed to maintain lock even in the event of VCR headswitches and multipath noise. The HMP8112 can use a main crystal (CLK) of 20MHz to 30MHz. The crystal is used as a reference frequency for the internal phase locked loops. The ratio of the crystal frequency to the video standard is programmed into an internal register for the PLLs to correctly decode video. The HMP8112 decoder contains 2 sample rate converters and 2 phase locked loops that lock to the incoming video. The input sample rate converter synchronizes the digitized video from the CLK rate to a 4xfSC rate. The chrominance is separated from the luminance and then demodulated. The Chroma phase locked loop uses the CLK source as the PLL reference frequency. To initialize the chroma PLL, the CLK to 4xfSC ratio must be loaded. For example, if the CLK was 27MHz and the video signal is NTSC (4 x 3.579545MHz = 14.318MHz) then the ratio loaded is 0.5302895 in 16-bit precision. BLACK Y DATA RANGE Cb DATA RANGE Cr DATA RANGE FIGURE 6. YCbCr DATA RANGES The decoder is compatible with all NTSC and PAL video formats available throughout the world. Table 2 shows the compatible video standards. Horizontal Sync Detection Horizontal sync is detected in the Output Sample Rate converter (OSR). The OSR spatially aligns the pixels in the vertical direction by using the horizontal sync information embedded in the digital video data stream. The HSYNC sync pulse out of the decoder is a video synchronous output 8 HMP8112 TABLE 2. COMPATIBLE VIDEO INPUT STANDARDS COLOR SUBCARRIER fSC 3.579545MHz 4.43361875MHz 3.579545MHz 4.43361875MHz 3.58205625MHz NUMBER OF FIELDS PER SECOND 60Hz 50Hz 60Hz 50Hz 50Hz NUMBER OF VERTICAL LINES 525 625 525 625 625 LINE FREQUENCY 15,734 (± 0.0003%) 15,625 (± 0.02%) 15,750 (± 0.0003%) 15,625 (± 0.15%) 15,750 (± 0.15%) NOMINAL BANDWIDTH 4.2MHz 5.0MHz 4.2MHz 4.2MHz 4.2MHz BLACK SETUP TO BLANK 7.5 IRE 0 IRE 7.5 IRE 7.5 IRE 7.5 IRE STANDARD NTSC M PAL B, D, G, H, I PAL M PAL N Special Combination PAL N VIDEO INPUT LOW TIME COUNTER VSYNC DETECT THRESHOLD OV VSYNC ‘EVEN’ FIELD 6.5 LINES FIELD FIGURE 7. VSYNC TIMING AND THE EVEN TO ODD TRANSITION VIDEO INPUT LOW TIME COUNTER VSYNC DETECT THRESHOLD OV VSYNC ‘ODD’ FIELD 6.5 LINES FIELD FIGURE 8. VSYNC TIMING AND THE ODD TO EVEN TRANSITION (4 x fSC)/CLK = Chroma PLL Value (4 x 3.579545MHz) / 27MHz = 0.5302895 This value must be loaded to correctly separate and decode the video signal. A default Chroma PLL Value is used after a system RESET is applied. The default assumes a CLK of 27MHz and NTSC as the video standard. The default value is 0.5302895. An ideal 4xfSC line should have 910 pixels for NTSC and 1135 for PAL. The Output Sample rate converter is locked to the horizontal line frequency and is used to spatially align pixels in a field. The LOCKED flag signals when the phase locked loop is within a ±4 pixel range of the horizontal sync edge. When line errors exceed that range the LOCKED flag is cleared. In cases where VCRs are used in Pause, Fast Forward or Fast Reverse, lines are typically dropped or added by the VCR. In a worst case scenario a VCR line tolerance will vary by ±8%. The standard detect logic checks the line count against the given standard to determine an error. VCRs in trick mode cannot cause a standard error. With an NTSC standard VCR the number of lines in a field should not exceed 285. Greater than 285 lines in a field is interpreted as a PAL video source. An ideal NTSC source should have 262.5 lines per field and a PAL source should have 312.5 lines per field. The HMP8112 can detect a STANDARD Error that signals when the video received does not match the standard that was programmed into the Video Input Control Register. This 9 HMP8112 flag, when asserted, tells the user that the video standard that was expected was not found and a different standard should be selected in the Video Input Control register. The error flag is cleared after a RESET or after the Chroma PLL Clock Ratio register has been loaded via the I2C bus. After the flag is cleared the standard error logic verifies the video standard. The error flag is set after 2 vertical sync periods have passed and the line count did not match the expected line count. Brightness The user can control the brightness of the incoming video by programming the Brightness register. The brightness adjustment will offset the Y component. The brightness register is an 8-bit register where the bottom 7 bits are brightness control and the top bit is the IRE setup. The IRE setup for NTSC is 70 and the setup for PAL is 63. When the IRE bit is set (1) then the value of 70 is subtracted from the Y data, and if the IRE bit is cleared (0) then the values of 63 is subtracted. The brightness control bits BR[6-0] will brighten the picture as the value is increased. BR = -64 is the darkest and BR = +63 is the brightest. The default value of the register after a RESET is 0 (80H). Video Adjustments The HMP8112 allows the user to vary such video parameters as Contrast, Brightness, Sharpness, Hue and Color Saturation. These adjustments can be made via the I2C interface. Contrast, brightness and sharpness are luminance controls. The full dynamic range of the luminance channel can be used by selecting the IRE setup cancellation mode. This mode will remove the IRE setup and blanking level offset to take advantage of the full dynamic range of the luminance processing path. The sharpening filters allow the enhancement of low, mid and high frequency components of the luminance signal to compensate for low amplitude video. Vertical sharpness is also controlled via the I2C interface. Hue and Color saturation controls enhance the CbCr components of the incoming video, all under user control. TABLE 3. USER CONTROLLED SETTINGS USER VIDEO SETTINGS Brightness Contrast Hue or Tint Horizontal Sharpness Vertical Sharpness Color Saturation Contrast The contrast adjustment will allow the user to increase and decrease the gain of the Y data. The contrast factor is an 8-bit number (as shown below) that ranges from 0 to 1.999. X.XXXXXXX The default value after a RESET is 1.47 (BDH). Hue or Tint Adjust The Hue adjustment is applied to the U and the V color difference signal. The Hue adjusts the phase of the given UV data. The Hue can be adjusted by ±30o in 1/4o increments. This is achieved by changing the Burst Phase Locked reference point. Figure 10 shows the block diagram for the color adjustment section. This default value for this register is 0 (00H). DEMODULATED UV DATA CHROMA AGC AND USER SETTINGS UV DATA VIDEO DATA COLOR DECODER Luminance Adjustments The Luminance data can be adjusted in the HMP8112. The user can adjust brightness and contrast of the Y or luminance data. The user can also set the IRE or setup subtraction value to eliminate the black pedestal offset from NTSC signals. The Contrast adjustment range can exceed a value of one so as to take full advantage of the 8-bit dynamic range for Y. The user control settings executes the equation YOUT = (Y - IRE Setup + BRIGHTNESS) x CONTRAST BRIGHTNESS (-64 TO +63) HUE OFFSET + HUE ADJUST TO INPUT SAMPLE RATE CONVERTER CHROMA PHASE LOCKED LOOP FIGURE 10. HUE ADJUST BLOCK DIAGRAM Horizontal/Vertical Sharpness Y DATA FROM DECODER + IRE BLACK SETUP (NTSC = 70, PAL = 63) + X 8 CONTRAST (0 TO 1.999) Y’ FIGURE 9. LUMINANCE CONTROL SETTINGS PATH The frequency characteristics of the video waveform can be altered to enhance the sharpness of the picture. The Horizontal Sharpness register acts as a 4 band equalizer where the amplitude of specific frequency ranges can be enhanced or diminished. The Sharpness Control Register allows the Low (LF), Mid (MF) and High Frequency (HF) bands of the luminance signal to be enhanced. Vertical Sharpness can be adjusted to 1 or a factor of 0. The RESET default is a factor of 1.0 10 HMP8112 The 2-bit values allow 4 choices of scaling factors. The sharpness control helps to compensate for losses in the scaling interpolators that can reduce the amplitude of high frequency components. TABLE 4. SHARPNESS GAIN FACTOR SELECTS XF1 0 0 1 1 XF0 0 1 0 1 GAIN FACTOR SCALED BY 1.0 SCALED BY 2.0 SCALED BY 4.0 SCALED BY 0 HMP8112 VIDEO DECODER 41 SDA SCL 40 4kΩ 4kΩ I 2C Control Interface The HMP8112 utilizes an I2C control bus interface to program the internal configuration registers. This standard mode (up to 100 KBPS) interface consists of the bidirectional Serial Data Line (SDA) and the Serial Clock Line (SCL). The implementation on the HMP8112 is a simple slave interface that will not respond to general calls and cannot initiate a transfer. When the device is not active, the SDA and SCL control pins should be pulled high through external 4kΩ pullup resistors. +5V +5V +5V The Color Killer (AGC Hysteresis and Loop Limits) The color killer will disable the color difference path and set the U and V components to zero. The automatic color killer circuitry uses the AGC threshold to determine the maximum and minimum gain factor limits. The loop filter determines how much the AGC gain factor can be changed within one line. The maximum gain factor (Max = 8) and the minimum gain factor (Min = 0.5) will limit the range of the AGC. When the gain factor exceeds the maximum gain factor of 8, the gain factor is limited to 8. Once the signal has an amplitude of 1/16th, the nominal video the color killer is enabled and the chroma phase locked loop holds it’s last phase reference. While the color killer is enabled, the U and V components are forced to zero. Once the input video signal reaches 1/7th the optimum amplitude the color killer is disabled and the color is returned. MAX GAIN FACTOR MIN GAIN FACTOR AGC ENABLE FIGURE 12. PULLUP RESISTOR CONFIGURATION UV DATA ÷4096 COLOR KILLER AGC GAIN FACTOR The I2C clock/data timing is shown below in Figure 13. The HMP8112 contains 29 internal registers used to program and configure the Decoder. The I2C control port contains a pointer register that auto-increments through the entire register space and can be written. The autoincrement pointer will wrap after the last register has been accessed (Product ID Register) and should be set to the desired starting address each time an access is started. For a write transfer, the I2C device base address is the first part of a serial transfer. Then the internal register pointer is loaded. Then a series of registers can be written. If multiple registers are written, the pointer register will autoincrement up through the register address space. A stop cycle is used to end the transfer after the desired number of registers are programmed. For a read transfer, the I2C device address is the first part of the serial transfer. Then the internal register pointer is loaded. At this point another start cycle is initiated to access the individual registers. Figure 14 shows the programming flow for read transfer of the internal registers. Multiple registers can be read and the pointer register will autoincrement up through the pointer register address space. On the last data read, an acknowledge should not be issued. A stop cycle is used to end the transfer after the desired number of registers are read. I2C LINE COUNT FIGURE 11. LOOP FILTER BLOCK DIAGRAM (HYSTERESIS) The dynamic range of the AGC allows it to compensate for video that is 1/8 to 2 times the specified nominal of 1VP-P. Saturation The color saturation component is controlled via the Color Saturation Registers. The color saturation is applied to the UV components after the AGC function. The saturation value is multiplied by the UV data to increase the color intensity. The data range is from 0 to 1.96875 where 1.96875 is the brightest intensity. This is an 8-bit number in the form: X.XXX XXXX The default value after a RESET is 1.2074 (9DH). Product ID Register The HMP8112 contains a product ID register that can be used to identify the presence of a board during a Plug ’n Play detection software algorithm. The Product ID code is 12H and the register is the last register in the HMP8112 (1BH). Output Data Port Modes The HMP8112 can output data in 2 formats, an 8-bit Burst mode and a 16-bit Synchronous Pixel Transfer mode. In 16-bit Synchronous Pixel Transfer Mode pixel data is output at the 11 HMP8112 CLK frequency and Table 5 shows the number of data points per video line to expect for a given standard. Data is output as 4:2:2 subsampled data in a Y-Cb/Y-Cr 16-bit sequence. The Data Valid (DVLD) flag is asserted when video data is present on the 16-bit output port of the HMP8112 (Y[7:0], CbCr[7:0]). The ACTIVE flag is asserted when the active video portion of the horizontal scan line is present on the data output port. See Figure 15 for Synchronous Pixel Transfer Mode timing. DVLD is asserted every time the output sample rate converter has a valid output. When DVLD and ACTIVE are used together the visual portion of the image can be captured. When DVLD is used alone all valid data during the Horizontal, Vertical and Reference Burst Timing are available. ACTIVE is asserted from lines 22 through 262.5 and lines 285.5 through 525 for NTSC (and PAL M). Active is asserted from lines 23.5 through 310 and lines 336 through 623.5 for PAL (B, D, G, H, I, N, Comb N). The CLK can be run on a 20MHz - 30MHz clock source. Data will be output (on average) at the Output Data Rate shown in Table 5 for a given standard. Data is clocked out synchronous to CLK and will come in bursts. To smooth out the data rate to a regular rate a CLK of 2X the average output data rate can be used. In the 16-bit pixel transfer, data is sequenced on the CbCr[7:0] data bus, starting with Cb and then Cr. TABLE 5. OUTPUT MODE STANDARDS OUTPUT ACTIVE DATA PIXELS/ RATE LINE 12.27MHz 13.5MHz 640 720 720 TOTAL PIXELS/ LINE 780 858 864 TOTAL LINES/ FIELD 262.5 262.5 312.5 STANDARD NTSC Square Pixel NTSC CCIR 601 PAL B, D, G, H, I, N, 13.5MHz COMB N, CCIR601 PAL M CCIR 601 13.5MHz 720 768 858 944 262.5 312.5 PAL B, D, G, H, I, N 14.74MHz Square Pixel PAL M Square Pixel 14.74MHz 640 780 312.5 For Burst Mode output format the Y[7:0] output bus is used to transfer all YCbCr data in 8-bit format. The data is also 4:2:2 subsampled but will only contain the active video portion of the line. The HMP8112 uses an internal 32 deep fifo to handle latencies between the output sample rate and the CLK frequency. In this mode, the data is clocked out at the CLK rate and only clock frequencies of 24.5454MHz, 27MHz and 29.5MHz can be used. In 8-bit data mode, the data is sequenced on the Y[7:0] bus in Cb, Y, Cr, Y format. ACTIVE is asserted as soon as the mode is selected. DVLD when asserted indicates a valid active pixel is available. Pixels during the horizontal and vertical blanking are not available. Only the active portions of the video line are output. SDA SCL S START CONDITION 1-7 ADDRESS 8 R/W 9 ACK 1-7 DATA 8 9 ACK P STOP CONDITION FIGURE 13. I2C SERIAL TIMING FLOW DATA WRITE S 1000 100 (R/W) CHIP ADDR 0x88 A SUB ADDR A DATA REGISTER POINTED TO BY SUBADDR A DATA AP S = START CYCLE P = STOP CYCLE A = ACKNOWLEDGE NA = NO ACKNOWLEDGE FROM MASTER FROM HMP8112 DATA READ S 1000 100 (R/W) CHIP ADDR 0x88 A SUB ADDR AS CHIP ADDR 0x89 A DATA REGISTER POINTED TO BY SUBADDR A DATA NA P FIGURE 14. REGISTER WRITE PROGRAMMING FLOW 12 HMP8112 Reset The RESET pin is used to return the decoder to an initialization state. This pin should be used after a power-up to set the part into a known state. The internal registers are returned to their RESET state and the Serial I2C port is returned to inactive state. The RESET pin is an active low signal and should be asserted for minimum of 1 CLK cycle. After a RESET or a software reset has occurred all output pins are three-stated. The following pins must be pulled high to ensure proper operation: tDLY CLK HSYNC VSYNC DVLD ACTIVE FIELD A 10K or smaller pullup resistor to VCC is recommended. DVLD NOTE 2 ACTIVE Y[7-0] tDVLD CbCr[7-0] YN NOTE 1 CrN Y0 Y1 Y2 Cb0 Cr0 Cb1 NOTES: 1. Y0 is the first active luminance pixel of a line. Cb0 and Cr0 are first active chrominance pixels in a line. Cb and Cr will alternate every cycle due to the 4:2:2 subsampling. 2. Active is asserted for lines 22-262.5 and 285.5-525. DVLD is asserted for every valid pixel during both active and blanking regions. DVLD is asserted during vertical and horizontal sync. FIGURE 15A. OUTPUT TIMING 16-BIT MODE / NTSC M, N PAL M LINES 1-21